1 /*
2 * Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver
3 * Basic data header
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #ifndef _NSP32_H
17 #define _NSP32_H
18
19 //#define NSP32_DEBUG 9
20
21 /*
22 * VENDOR/DEVICE ID
23 */
24 #define PCI_VENDOR_ID_IODATA 0x10fc
25
26 #define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005
27 #define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007
28 #define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007
29 #define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010
30 #define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011
31 #define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012
32 #define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013
33 #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015
34 #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009
35
36 /*
37 * MODEL NAME
38 *
39 * note: Model number and model string must be same order.
40 */
41 enum {
42 MODEL_IODATA = 0,
43 MODEL_KME = 1,
44 MODEL_WORKBIT = 2,
45 MODEL_LOGITEC = 3,
46 MODEL_PCI_WORKBIT = 4,
47 MODEL_PCI_LOGITEC = 5,
48 MODEL_PCI_MELCO = 6,
49 };
50
51 static char * nsp32_model[] = {
52 "I-O DATA CBSC-II CardBus card",
53 "KME SCSI CardBus card",
54 "Workbit duo SCSI CardBus card",
55 "Logitec CardBus card with external ROM",
56 "Workbit / I-O DATA PCI card",
57 "Logitec PCI card with external ROM",
58 "Melco CardBus/PCI card with external ROM",
59 };
60
61
62 /*
63 * SCSI generic message definitions
64 */
65 #define EXTENDED_SDTR_LEN 0x03
66
67 /* Little Endian */
68 typedef u32 u32_le;
69 typedef u16 u16_le;
70
71 /*
72 * MACRO
73 */
74 /* from X11/Intrinsic.h */
75 #define NUMBER(arr) ((int) (sizeof(arr) / sizeof(arr[0])))
76 #define ARRAY_OFFSET(type,num) ((int) (((type *) 0) + (num)))
77 #define BIT(x) (1UL << (x))
78 #ifndef MIN
79 # define MIN(a,b) ((a) > (b) ? (b) : (a))
80 #endif
81
82 /*
83 * BASIC Definitions
84 */
85 #ifndef TRUE
86 # define TRUE 1
87 #endif
88 #ifndef FALSE
89 # define FALSE 0
90 #endif
91 #define ASSERT 1
92 #define NEGATE 0
93
94
95 /*******************/
96 /* normal register */
97 /*******************/
98 /*
99 * Don't access below register with Double Word:
100 * +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0.
101 */
102 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
103 #define IRQ_STATUS 0x00 /* BASE+00, W, R */
104 # define IRQSTATUS_LATCHED_MSG BIT(0)
105 # define IRQSTATUS_LATCHED_IO BIT(1)
106 # define IRQSTATUS_LATCHED_CD BIT(2)
107 # define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
108 # define IRQSTATUS_RESELECT_OCCUER BIT(4)
109 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
110 # define IRQSTATUS_SCSIRESET_IRQ BIT(6)
111 # define IRQSTATUS_TIMER_IRQ BIT(7)
112 # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
113 # define IRQSTATUS_PCI_IRQ BIT(9)
114 # define IRQSTATUS_BMCNTERR_IRQ BIT(10)
115 # define IRQSTATUS_AUTOSCSI_IRQ BIT(11)
116 # define PCI_IRQ_MASK BIT(12)
117 # define TIMER_IRQ_MASK BIT(13)
118 # define FIFO_IRQ_MASK BIT(14)
119 # define SCSI_IRQ_MASK BIT(15)
120 # define IRQ_CONTROL_ALL_IRQ_MASK (PCI_IRQ_MASK | \
121 TIMER_IRQ_MASK | \
122 FIFO_IRQ_MASK | \
123 SCSI_IRQ_MASK )
124 # define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \
125 IRQSTATUS_PHASE_CHANGE_IRQ | \
126 IRQSTATUS_SCSIRESET_IRQ | \
127 IRQSTATUS_TIMER_IRQ | \
128 IRQSTATUS_FIFO_SHLD_IRQ | \
129 IRQSTATUS_PCI_IRQ | \
130 IRQSTATUS_BMCNTERR_IRQ | \
131 IRQSTATUS_AUTOSCSI_IRQ )
132
133 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
134 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
135 # define CB_MMIO_MODE BIT(0)
136 # define CB_IO_MODE BIT(1)
137 # define BM_TEST BIT(2)
138 # define BM_TEST_DIR BIT(3)
139 # define DUAL_EDGE_ENABLE BIT(4)
140 # define NO_TRANSFER_TO_HOST BIT(5)
141 # define TRANSFER_GO BIT(7)
142 # define BLIEND_MODE BIT(8)
143 # define BM_START BIT(9)
144 # define ADVANCED_BM_WRITE BIT(10)
145 # define BM_SINGLE_MODE BIT(11)
146 # define FIFO_TRUE_FULL BIT(12)
147 # define FIFO_TRUE_EMPTY BIT(13)
148 # define ALL_COUNTER_CLR BIT(14)
149 # define FIFOTEST BIT(15)
150
151 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
152
153 #define TIMER_SET 0x06 /* BASE+06, W, R/W */
154 # define TIMER_CNT_MASK (0xff)
155 # define TIMER_STOP BIT(8)
156
157 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
158 #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
159
160 #define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
161 # define FIFO_REST_MASK 0x1ff
162 # define FIFO_EMPTY_SHLD_FLAG BIT(14)
163 # define FIFO_FULL_SHLD_FLAG BIT(15)
164
165 #define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
166 # define SREQSMPLRATE_RATE0 BIT(0)
167 # define SREQSMPLRATE_RATE1 BIT(1)
168 # define SAMPLING_ENABLE BIT(2)
169 # define SMPL_40M (0) /* 40MHz: 0-100ns/period */
170 # define SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */
171 # define SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */
172
173 #define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */
174 # define BUSCTL_SEL BIT(0)
175 # define BUSCTL_RST BIT(1)
176 # define BUSCTL_DATAOUT_ENB BIT(2)
177 # define BUSCTL_ATN BIT(3)
178 # define BUSCTL_ACK BIT(4)
179 # define BUSCTL_BSY BIT(5)
180 # define AUTODIRECTION BIT(6)
181 # define ACKENB BIT(7)
182
183 #define CLR_COUNTER 0x12 /* BASE+12, B, W */
184 # define ACK_COUNTER_CLR BIT(0)
185 # define SREQ_COUNTER_CLR BIT(1)
186 # define FIFO_HOST_POINTER_CLR BIT(2)
187 # define FIFO_REST_COUNT_CLR BIT(3)
188 # define BM_COUNTER_CLR BIT(4)
189 # define SAVED_ACK_CLR BIT(5)
190 # define CLRCOUNTER_ALLMASK (ACK_COUNTER_CLR | \
191 SREQ_COUNTER_CLR | \
192 FIFO_HOST_POINTER_CLR | \
193 FIFO_REST_COUNT_CLR | \
194 BM_COUNTER_CLR | \
195 SAVED_ACK_CLR )
196
197 #define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */
198 # define BUSMON_MSG BIT(0)
199 # define BUSMON_IO BIT(1)
200 # define BUSMON_CD BIT(2)
201 # define BUSMON_BSY BIT(3)
202 # define BUSMON_ACK BIT(4)
203 # define BUSMON_REQ BIT(5)
204 # define BUSMON_SEL BIT(6)
205 # define BUSMON_ATN BIT(7)
206
207 #define COMMAND_DATA 0x14 /* BASE+14, B, R/W */
208
209 #define PARITY_CONTROL 0x16 /* BASE+16, B, W */
210 # define PARITY_CHECK_ENABLE BIT(0)
211 # define PARITY_ERROR_CLEAR BIT(1)
212 #define PARITY_STATUS 0x16 /* BASE+16, B, R */
213 //# define PARITY_CHECK_ENABLE BIT(0)
214 # define PARITY_ERROR_NORMAL BIT(1)
215 # define PARITY_ERROR_LSB BIT(1)
216 # define PARITY_ERROR_MSB BIT(2)
217
218 #define RESELECT_ID 0x18 /* BASE+18, B, R */
219
220 #define COMMAND_CONTROL 0x18 /* BASE+18, W, W */
221 # define CLEAR_CDB_FIFO_POINTER BIT(0)
222 # define AUTO_COMMAND_PHASE BIT(1)
223 # define AUTOSCSI_START BIT(2)
224 # define AUTOSCSI_RESTART BIT(3)
225 # define AUTO_PARAMETER BIT(4)
226 # define AUTO_ATN BIT(5)
227 # define AUTO_MSGIN_00_OR_04 BIT(6)
228 # define AUTO_MSGIN_02 BIT(7)
229 # define AUTO_MSGIN_03 BIT(8)
230
231 #define SET_ARBIT 0x1a /* BASE+1a, B, W */
232 # define ARBIT_GO BIT(0)
233 # define ARBIT_CLEAR BIT(1)
234
235 #define ARBIT_STATUS 0x1a /* BASE+1a, B, R */
236 //# define ARBIT_GO BIT(0)
237 # define ARBIT_WIN BIT(1)
238 # define ARBIT_FAIL BIT(2)
239 # define AUTO_PARAMETER_VALID BIT(3)
240 # define SGT_VALID BIT(4)
241
242 #define SYNC_REG 0x1c /* BASE+1c, B, R/W */
243
244 #define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */
245
246 #define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */
247 #define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */
248 #define SCSI_DATA_IN 0x22 /* BASE+22, B, R */
249
250 #define SCAM_CONTROL 0x24 /* BASE+24, B, W */
251 #define SCAM_STATUS 0x24 /* BASE+24, B, R */
252 # define SCAM_MSG BIT(0)
253 # define SCAM_IO BIT(1)
254 # define SCAM_CD BIT(2)
255 # define SCAM_BSY BIT(3)
256 # define SCAM_SEL BIT(4)
257 # define SCAM_XFEROK BIT(5)
258
259 #define SCAM_DATA 0x26 /* BASE+26, B, R/W */
260 # define SD0 BIT(0)
261 # define SD1 BIT(1)
262 # define SD2 BIT(2)
263 # define SD3 BIT(3)
264 # define SD4 BIT(4)
265 # define SD5 BIT(5)
266 # define SD6 BIT(6)
267 # define SD7 BIT(7)
268
269 #define SACK_CNT 0x28 /* BASE+28, DW, R/W */
270 #define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */
271
272 #define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */
273 #define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */
274 #define BM_START_ADR 0x34 /* BASE+34, DW, R/W */
275
276 #define BM_CNT 0x38 /* BASE+38, DW, R/W */
277 # define BM_COUNT_MASK 0x0001ffffUL
278 # define SGTEND BIT(31) /* Last SGT marker */
279
280 #define SGT_ADR 0x3c /* BASE+3c, DW, R/W */
281 #define WAIT_REG 0x40 /* Bi only */
282
283 #define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */
284 # define COMMAND_PHASE BIT(0)
285 # define DATA_IN_PHASE BIT(1)
286 # define DATA_OUT_PHASE BIT(2)
287 # define MSGOUT_PHASE BIT(3)
288 # define STATUS_PHASE BIT(4)
289 # define ILLEGAL_PHASE BIT(5)
290 # define BUS_FREE_OCCUER BIT(6)
291 # define MSG_IN_OCCUER BIT(7)
292 # define MSG_OUT_OCCUER BIT(8)
293 # define SELECTION_TIMEOUT BIT(9)
294 # define MSGIN_00_VALID BIT(10)
295 # define MSGIN_02_VALID BIT(11)
296 # define MSGIN_03_VALID BIT(12)
297 # define MSGIN_04_VALID BIT(13)
298 # define AUTOSCSI_BUSY BIT(15)
299
300 #define SCSI_CSB_IN 0x42 /* BASE+42, B, R */
301
302 #define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */
303 # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
304 # define MSGOUT_VALID BIT(7)
305
306 #define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */
307 #define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */
308
309 #define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */
310 #define STOHDATADELAY 0x54 /* BASE+54, B, R/W */
311 #define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */
312 #define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */
313
314
315 /********************/
316 /* indexed register */
317 /********************/
318
319 #define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */
320 # define CLOCK_2 BIT(0) /* MCLK/2 */
321 # define CLOCK_4 BIT(1) /* MCLK/4 */
322 # define PCICLK BIT(7) /* PCICLK (33MHz) */
323
324 #define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */
325 # define BPWR BIT(0)
326 # define SENSE BIT(1) /* Read Only */
327
328 #define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */
329 #define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */
330 # define LED_ON (0)
331 # define LED_OFF BIT(0)
332
333 #define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */
334 # define IRQSELECT_RESELECT_IRQ BIT(0)
335 # define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
336 # define IRQSELECT_SCSIRESET_IRQ BIT(2)
337 # define IRQSELECT_TIMER_IRQ BIT(3)
338 # define IRQSELECT_FIFO_SHLD_IRQ BIT(4)
339 # define IRQSELECT_TARGET_ABORT_IRQ BIT(5)
340 # define IRQSELECT_MASTER_ABORT_IRQ BIT(6)
341 # define IRQSELECT_SERR_IRQ BIT(7)
342 # define IRQSELECT_PERR_IRQ BIT(8)
343 # define IRQSELECT_BMCNTERR_IRQ BIT(9)
344 # define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
345
346 #define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */
347 # define OLD_MSG BIT(0)
348 # define OLD_IO BIT(1)
349 # define OLD_CD BIT(2)
350 # define OLD_BUSY BIT(3)
351
352 #define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */
353 #define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */
354
355 #define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */
356 # define ROM_WRITE_ENB BIT(0)
357 # define IO_ACCESS_ENB BIT(1)
358 # define ROM_ADR_CLEAR BIT(2)
359
360 #define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */
361
362 #define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */
363
364 #define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */
365 # define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
366 # define OEM1 BIT(2) /* OEM select */
367 # define OPTB BIT(3) /* KME mode select */
368 # define OPTC BIT(4) /* KME mode select */
369 # define OPTD BIT(5) /* KME mode select */
370 # define OPTE BIT(6) /* KME mode select */
371 # define OPTF BIT(7) /* Power management */
372
373 #define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */
374 #define MISC_RD 0x0c
375 # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
376 # define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */
377 # define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */
378 # define DELAYED_BMSTART BIT(3)
379 # define MASTER_TERMINATION_SELECT BIT(4)
380 # define BMREQ_NEGATE_TIMING_SEL BIT(5)
381 # define AUTOSEL_TIMING_SEL BIT(6)
382 # define MISC_MABORT_MASK BIT(7)
383 # define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
384
385 #define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */
386 # define BM_CYCLE0 BIT(0)
387 # define BM_CYCLE1 BIT(1)
388 # define BM_FRAME_ASSERT_TIMING BIT(2)
389 # define BM_IRDY_ASSERT_TIMING BIT(3)
390 # define BM_SINGLE_BUS_MASTER BIT(4)
391 # define MEMRD_CMD0 BIT(5)
392 # define SGT_AUTO_PARA_MEMED_CMD BIT(6)
393 # define MEMRD_CMD1 BIT(7)
394
395
396 #define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */
397 # define SREQ_EDGH_SELECT BIT(0)
398
399 #define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */ /* For hardware testing. Don't use it. */
400 # define REQCNT_UP BIT(0)
401 # define ACKCNT_UP BIT(1)
402 # define BMADR_UP BIT(4)
403 # define BMCNT_UP BIT(5)
404 # define SGT_CNT_UP BIT(7)
405
406 #define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */
407 #define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */
408 #define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */
409 #define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */
410 #define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */
411
412 #define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */
413 # define SROM_CTL BIT(0)
414 # define SROM_ENABLE BIT(1)
415 # define SROM_DATA BIT(2)
416
417 #define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */
418 #define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */
419 #define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */
420 #define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */
421 #define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */
422 #define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */
423 #define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */
424 #define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */
425 #define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */
426 #define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */
427 #define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */
428 #define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */
429 #define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */
430 #define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */
431
432
433 /*
434 * Useful Bus Monitor status combinations.
435 */
436 #define BUSMON_BUS_FREE 0
437 #define BUSMON_COMMAND ( BUSMON_BSY | BUSMON_CD | BUSMON_REQ )
438 #define BUSMON_MESSAGE_IN ( BUSMON_BSY | BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
439 #define BUSMON_MESSAGE_OUT ( BUSMON_BSY | BUSMON_MSG | BUSMON_CD | BUSMON_REQ )
440 #define BUSMON_DATA_IN ( BUSMON_BSY | BUSMON_IO | BUSMON_REQ )
441 #define BUSMON_DATA_OUT ( BUSMON_BSY | BUSMON_REQ )
442 #define BUSMON_STATUS ( BUSMON_BSY | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
443 #define BUSMON_RESELECT ( BUSMON_IO | BUSMON_SEL)
444 #define BUSMON_PHASE_MASK ( BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_SEL)
445
446 #define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK )
447 #define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK )
448 #define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK )
449 #define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK )
450 #define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK )
451 #define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK )
452 #define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO )
453
454
455 /************************************************************************
456 * structure for DMA/Scatter Gather list
457 */
458 #define NSP32_SG_SIZE SG_ALL
459
460 /* All values must be little endian */
461 typedef struct _nsp32_sgtable {
462 u32_le addr; /* transfer address */
463 u32_le len; /* transfer length. BIT(31) is for SGTEND mark */
464 } __attribute__ ((packed)) nsp32_sgtable;
465
466 /* All values must be little endian */
467 typedef struct _nsp32_sglun {
468 nsp32_sgtable sgt[NSP32_SG_SIZE+1]; /* SG table */
469 } __attribute__ ((packed)) nsp32_sglun;
470 #define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN)
471
472 /* Auto parameter mode memory map. */
473 /* All values must be little endian. */
474 typedef struct _nsp32_autoparam {
475 u8 cdb[4 * 0x10]; /* SCSI Command */
476 u32_le msgout; /* outgoing messages */
477 u8 syncreg; /* sync register value */
478 u8 ackwidth; /* ack width register value */
479 u8 target_id; /* target/host device id */
480 u8 sample_reg; /* hazard killer sampling rate */
481 u16_le command_control; /* command control register */
482 u16_le transfer_control; /* transfer control register */
483 u32_le sgt_pointer; /* SG table physical address for DMA */
484 u32_le dummy[2];
485 } __attribute__ ((packed)) nsp32_autoparam; /* must be packed struct */
486
487 /*
488 * host data structure
489 */
490 /* message in/out buffer */
491 #define MSGOUTBUF_MAX 20
492 #define MSGINBUF_MAX 20
493
494 /* flag for trans_method */
495 #define NSP32_TRANSFER_BUSMASTER BIT(0)
496 #define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */
497 #define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */
498
499
500 /*
501 * structure for connected LUN dynamic data
502 *
503 * Note: Currently tagged queuing is disabled, each nsp32_lunt holds
504 * one SCSI command and one state.
505 */
506 #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
507 #define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */
508
509 typedef struct _nsp32_lunt {
510 Scsi_Cmnd *SCpnt; /* Current Handling Scsi_Cmnd */
511 unsigned long save_datp; /* Save Data Pointer - saved position from initial address */
512 int msgin03; /* auto msg in 03 flag */
513 unsigned int sg_num; /* Total number of SG entries */
514 int cur_entry; /* Current SG entry number */
515 nsp32_sglun *sglun; /* sg table per lun */
516 dma_addr_t sglun_paddr; /* sglun physical address */
517 } nsp32_lunt;
518
519
520 /*
521 * SCSI TARGET/LUN definition
522 */
523 #define NSP32_HOST_SCSIID 7 /* SCSI initiator is everytime defined as 7 */
524 #define MAX_TARGET 8
525 #define MAX_LUN 8 /* XXX: In SPI3, max number of LUN is 64. */
526
527
528 typedef struct _nsp32_sync_table {
529 unsigned char period_num; /* period number */
530 unsigned char ackwidth; /* ack width designated by period */
531 unsigned char start_period; /* search range - start period */
532 unsigned char end_period; /* search range - end period */
533 unsigned char sample_rate; /* hazard killer parameter */
534 } nsp32_sync_table;
535
536
537 /*
538 * structure for target device static data
539 */
540 /* flag for nsp32_target.sync_flag */
541 #define SDTR_NONE 0 /* initial state */
542 #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
543 #define SDTR_TARGET BIT(1) /* sending SDTR from target */
544 #define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */
545
546 /* syncronous period value for nsp32_target.config_max */
547 #define FAST5M 0x32
548 #define FAST10M 0x19
549 #define ULTRA20M 0x0c
550
551 /* flag for nsp32_target.{sync_offset, period} */
552 #define ASYNC_OFFSET 0 /* asynchronous transfer */
553 #define MAX_OFFSET 0xf /* synchronous transfer max offset */
554
555 /* syncreg:
556 bit:07 06 05 04 03 02 01 00
557 ---PERIOD-- ---OFFSET-- */
558 #define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f))
559
560 typedef struct _nsp32_target {
561 unsigned char syncreg; /* value for SYNCREG */
562 unsigned char ackwidth; /* value for ACKWIDTH */
563 unsigned char period; /* sync period (0-255) */
564 unsigned char offset; /* sync offset (0-15) */
565 int sync_flag; /* SDTR_*, 0 */
566 int limit_entry; /* max speed limit entry designated
567 by EEPROM configuration */
568 unsigned char sample_reg; /* SREQ hazard killer register */
569 } nsp32_target;
570
571 typedef struct _nsp32_hw_data {
572 int IrqNumber;
573 int BaseAddress;
574 int NumAddress;
575 unsigned long MmioAddress;
576 #define NSP32_MMIO_OFFSET 0x0800
577 unsigned long MmioLength;
578
579 Scsi_Cmnd *CurrentSC;
580
581 struct pci_dev *Pci;
582 const struct pci_device_id *pci_devid;
583 struct Scsi_Host *Host;
584 spinlock_t Lock;
585
586 char info_str[100];
587
588 /* allocated memory region */
589 nsp32_sglun *sg_list; /* sglist virtuxal address */
590 dma_addr_t sg_paddr; /* physical address of hw_sg_table */
591 nsp32_autoparam *autoparam; /* auto parameter transfer region */
592 dma_addr_t auto_paddr; /* physical address of autoparam */
593 int cur_entry; /* current sgt entry */
594
595 /* target/LUN */
596 nsp32_lunt *cur_lunt; /* Current connected LUN table */
597 nsp32_lunt lunt[MAX_TARGET][MAX_LUN]; /* All LUN table */
598
599 nsp32_target *cur_target; /* Current connected SCSI ID */
600 nsp32_target target[MAX_TARGET]; /* SCSI ID */
601 int cur_id; /* Current connected target ID */
602 int cur_lun; /* Current connected target LUN */
603
604 /* behavior setting parameters */
605 int trans_method; /* transfer method flag */
606 int resettime; /* Reset time */
607 int clock; /* clock dividing flag */
608 nsp32_sync_table *synct; /* sync_table determined by clock */
609 int syncnum; /* the max number of synct element */
610
611 /* message buffer */
612 unsigned char msgoutbuf[MSGOUTBUF_MAX]; /* msgout buffer */
613 char msgout_len; /* msgoutbuf length */
614 unsigned char msginbuf [MSGINBUF_MAX]; /* megin buffer */
615 char msgin_len; /* msginbuf length */
616
617 #ifdef CONFIG_PM
618 u32 PciState[16]; /* save PCI state to this area */
619 #endif
620 } nsp32_hw_data;
621
622 /*
623 * TIME definition
624 */
625 #define RESET_HOLD_TIME 10000 /* reset time in us (SCSI-2 says the
626 minimum is 25us) */
627 #define SEL_TIMEOUT_TIME 10000 /* 250ms defined in SCSI specification
628 (25.6us/1unit) */
629 #define ARBIT_TIMEOUT_TIME 100 /* 100us */
630 #define REQSACK_TIMEOUT_TIME 10000 /* max wait time for REQ/SACK assertion
631 or negation, 10000us == 10ms */
632
633 /**************************************************************************
634 * Compatibility functions
635 */
636
637 /* for Kernel 2.4 */
638 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
639 # define scsi_register_host(template) scsi_register_module(MODULE_SCSI_HA, template)
640 # define scsi_unregister_host(template) scsi_unregister_module(MODULE_SCSI_HA, template)
641 # define scsi_host_put(host) scsi_unregister(host)
642 # define pci_name(pci_dev) ((pci_dev)->slot_name)
643
644 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23))
645 typedef void irqreturn_t;
646 # define IRQ_NONE /* */
647 # define IRQ_HANDLED /* */
648 # define IRQ_RETVAL(x) /* */
649 #endif
650
651 /* This is ad-hoc version of scsi_host_get_next() */
scsi_host_get_next(struct Scsi_Host * host)652 static inline struct Scsi_Host *scsi_host_get_next(struct Scsi_Host *host)
653 {
654 if (host == NULL) {
655 return scsi_hostlist;
656 } else {
657 return host->next;
658 }
659 }
660
661 /* This is ad-hoc version of scsi_host_hn_get() */
scsi_host_hn_get(unsigned short hostno)662 static inline struct Scsi_Host *scsi_host_hn_get(unsigned short hostno)
663 {
664 struct Scsi_Host *host;
665
666 for (host = scsi_host_get_next(NULL); host != NULL;
667 host = scsi_host_get_next(host)) {
668 if (host->host_no == hostno) {
669 break;
670 }
671 }
672
673 return host;
674 }
675
676 /* host spin lock */
677 # define HOST_LOCK (&io_request_lock)
678 #endif
679
680 /* for Kernel 2.6 */
681 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
682 # define __devinitdata /* */
683
684 /* host spin lock */
685 # define HOST_LOCK (data->Host->host_lock)
686 #endif
687
688 #endif /* _NSP32_H */
689 /* end */
690