1 /******************************************************************************* 2 3 4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 2 of the License, or (at your option) 9 any later version. 10 11 This program is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 59 18 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 20 The full GNU General Public License is included in this distribution in the 21 file called LICENSE. 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 *******************************************************************************/ 27 28 #ifndef _E100_INC_ 29 #define _E100_INC_ 30 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/init.h> 34 #include <linux/mm.h> 35 #include <linux/errno.h> 36 #include <linux/ioport.h> 37 #include <linux/pci.h> 38 #include <linux/kernel.h> 39 #include <linux/netdevice.h> 40 #include <linux/etherdevice.h> 41 #include <linux/skbuff.h> 42 #include <linux/delay.h> 43 #include <linux/timer.h> 44 #include <linux/slab.h> 45 #include <linux/interrupt.h> 46 #include <linux/version.h> 47 #include <linux/string.h> 48 #include <linux/wait.h> 49 #include <linux/reboot.h> 50 #include <asm/io.h> 51 #include <asm/unaligned.h> 52 #include <asm/processor.h> 53 #include <linux/ethtool.h> 54 #include <linux/inetdevice.h> 55 #include <linux/bitops.h> 56 57 #include <linux/if.h> 58 #include <asm/uaccess.h> 59 #include <linux/ip.h> 60 #include <linux/if_vlan.h> 61 #include <linux/mii.h> 62 63 #define E100_CABLE_UNKNOWN 0 64 #define E100_CABLE_OK 1 65 #define E100_CABLE_OPEN_NEAR 2 /* Open Circuit Near End */ 66 #define E100_CABLE_OPEN_FAR 3 /* Open Circuit Far End */ 67 #define E100_CABLE_SHORT_NEAR 4 /* Short Circuit Near End */ 68 #define E100_CABLE_SHORT_FAR 5 /* Short Circuit Far End */ 69 70 #define E100_REGS_LEN 2 71 /* 72 * Configure parameters for buffers per controller. 73 * If the machine this is being used on is a faster machine (i.e. > 150MHz) 74 * and running on a 10MBS network then more queueing of data occurs. This 75 * may indicate the some of the numbers below should be adjusted. Here are 76 * some typical numbers: 77 * MAX_TCB 64 78 * MAX_RFD 64 79 * The default numbers give work well on most systems tests so no real 80 * adjustments really need to take place. Also, if the machine is connected 81 * to a 100MBS network the numbers described above can be lowered from the 82 * defaults as considerably less data will be queued. 83 */ 84 85 #define TX_FRAME_CNT 8 /* consecutive transmit frames per interrupt */ 86 /* TX_FRAME_CNT must be less than MAX_TCB */ 87 88 #define E100_DEFAULT_TCB 64 89 #define E100_MIN_TCB 2*TX_FRAME_CNT + 3 /* make room for at least 2 interrupts */ 90 #define E100_MAX_TCB 1024 91 92 #define E100_DEFAULT_RFD 64 93 #define E100_MIN_RFD 8 94 #define E100_MAX_RFD 1024 95 96 #define E100_DEFAULT_XSUM true 97 #define E100_DEFAULT_BER ZLOCK_MAX_ERRORS 98 #define E100_DEFAULT_SPEED_DUPLEX 0 99 #define E100_DEFAULT_FC 0 100 #define E100_DEFAULT_IFS true 101 #define E100_DEFAULT_UCODE true 102 103 #define TX_THRSHLD 8 104 105 /* IFS parameters */ 106 #define MIN_NUMBER_OF_TRANSMITS_100 1000 107 #define MIN_NUMBER_OF_TRANSMITS_10 100 108 109 #define E100_MAX_NIC 16 110 111 #define E100_MAX_SCB_WAIT 100 /* Max udelays in wait_scb */ 112 #define E100_MAX_CU_IDLE_WAIT 50 /* Max udelays in wait_cus_idle */ 113 114 /* HWI feature related constant */ 115 #define HWI_REGISTER_GRANULARITY 80 /* register granularity = 80 Cm */ 116 #define HWI_NEAR_END_BOUNDARY 1000 /* Near end is defined as < 10 meters */ 117 118 /* CPUSAVER_BUNDLE_MAX: Sets the maximum number of frames that will be bundled. 119 * In some situations, such as the TCP windowing algorithm, it may be 120 * better to limit the growth of the bundle size than let it go as 121 * high as it can, because that could cause too much added latency. 122 * The default is six, because this is the number of packets in the 123 * default TCP window size. A value of 1 would make CPUSaver indicate 124 * an interrupt for every frame received. If you do not want to put 125 * a limit on the bundle size, set this value to xFFFF. 126 */ 127 #define E100_DEFAULT_CPUSAVER_BUNDLE_MAX 6 128 #define E100_DEFAULT_CPUSAVER_INTERRUPT_DELAY 0x600 129 #define E100_DEFAULT_BUNDLE_SMALL_FR false 130 131 /* end of configurables */ 132 133 /* ====================================================================== */ 134 /* hw */ 135 /* ====================================================================== */ 136 137 /* timeout for command completion */ 138 #define E100_CMD_WAIT 100 /* iterations */ 139 140 struct driver_stats { 141 struct net_device_stats net_stats; 142 143 unsigned long tx_late_col; 144 unsigned long tx_ok_defrd; 145 unsigned long tx_one_retry; 146 unsigned long tx_mt_one_retry; 147 unsigned long rcv_cdt_frames; 148 unsigned long xmt_fc_pkts; 149 unsigned long rcv_fc_pkts; 150 unsigned long rcv_fc_unsupported; 151 unsigned long xmt_tco_pkts; 152 unsigned long rcv_tco_pkts; 153 unsigned long rx_intr_pkts; 154 }; 155 156 /* TODO: kill me when we can do C99 */ 157 #define false (0) 158 #define true (1) 159 160 /* Changed for 82558 and 82559 enhancements */ 161 /* defines for 82558/9 flow control CSR values */ 162 #define DFLT_FC_THLD 0x00 /* Rx FIFO threshold of 0.5KB free */ 163 #define DFLT_FC_CMD 0x00 /* FC Command in CSR */ 164 165 /* ====================================================================== */ 166 /* equates */ 167 /* ====================================================================== */ 168 169 /* 170 * These are general purpose defines 171 */ 172 173 /* Bit Mask definitions */ 174 #define BIT_0 0x0001 175 #define BIT_1 0x0002 176 #define BIT_2 0x0004 177 #define BIT_3 0x0008 178 #define BIT_4 0x0010 179 #define BIT_5 0x0020 180 #define BIT_6 0x0040 181 #define BIT_7 0x0080 182 #define BIT_8 0x0100 183 #define BIT_9 0x0200 184 #define BIT_10 0x0400 185 #define BIT_11 0x0800 186 #define BIT_12 0x1000 187 #define BIT_13 0x2000 188 #define BIT_14 0x4000 189 #define BIT_15 0x8000 190 #define BIT_28 0x10000000 191 192 #define BIT_0_2 0x0007 193 #define BIT_0_3 0x000F 194 #define BIT_0_4 0x001F 195 #define BIT_0_5 0x003F 196 #define BIT_0_6 0x007F 197 #define BIT_0_7 0x00FF 198 #define BIT_0_8 0x01FF 199 #define BIT_0_13 0x3FFF 200 #define BIT_0_15 0xFFFF 201 #define BIT_1_2 0x0006 202 #define BIT_1_3 0x000E 203 #define BIT_2_5 0x003C 204 #define BIT_3_4 0x0018 205 #define BIT_4_5 0x0030 206 #define BIT_4_6 0x0070 207 #define BIT_4_7 0x00F0 208 #define BIT_5_7 0x00E0 209 #define BIT_5_12 0x1FE0 210 #define BIT_5_15 0xFFE0 211 #define BIT_6_7 0x00c0 212 #define BIT_7_11 0x0F80 213 #define BIT_8_10 0x0700 214 #define BIT_9_13 0x3E00 215 #define BIT_12_15 0xF000 216 #define BIT_8_15 0xFF00 217 218 #define BIT_16_20 0x001F0000 219 #define BIT_21_25 0x03E00000 220 #define BIT_26_27 0x0C000000 221 222 /* Transmit Threshold related constants */ 223 #define DEFAULT_TX_PER_UNDERRUN 20000 224 225 #define MAX_MULTICAST_ADDRS 64 226 #define MAX_FILTER 16 227 228 #define FULL_DUPLEX 2 229 #define HALF_DUPLEX 1 230 231 /* 232 * These defines are specific to the 82557 233 */ 234 235 /* E100 PORT functions -- lower 4 bits */ 236 #define PORT_SOFTWARE_RESET 0 237 #define PORT_SELFTEST 1 238 #define PORT_SELECTIVE_RESET 2 239 #define PORT_DUMP 3 240 241 /* SCB Status Word bit definitions */ 242 /* Interrupt status/ack fields */ 243 /* ER and FCP interrupts for 82558 masks */ 244 #define SCB_STATUS_ACK_MASK BIT_8_15 /* Status Mask */ 245 #define SCB_STATUS_ACK_CX BIT_15 /* CU Completed Action Cmd */ 246 #define SCB_STATUS_ACK_FR BIT_14 /* RU Received A Frame */ 247 #define SCB_STATUS_ACK_CNA BIT_13 /* CU Became Inactive (IDLE) */ 248 #define SCB_STATUS_ACK_RNR BIT_12 /* RU Became Not Ready */ 249 #define SCB_STATUS_ACK_MDI BIT_11 /* MDI read or write done */ 250 #define SCB_STATUS_ACK_SWI BIT_10 /* S/W generated interrupt */ 251 #define SCB_STATUS_ACK_ER BIT_9 /* Early Receive */ 252 #define SCB_STATUS_ACK_FCP BIT_8 /* Flow Control Pause */ 253 254 /*- CUS Fields */ 255 #define SCB_CUS_MASK (BIT_6 | BIT_7) /* CUS 2-bit Mask */ 256 #define SCB_CUS_IDLE 0 /* CU Idle */ 257 #define SCB_CUS_SUSPEND BIT_6 /* CU Suspended */ 258 #define SCB_CUS_ACTIVE BIT_7 /* CU Active */ 259 260 /*- RUS Fields */ 261 #define SCB_RUS_IDLE 0 /* RU Idle */ 262 #define SCB_RUS_MASK BIT_2_5 /* RUS 3-bit Mask */ 263 #define SCB_RUS_SUSPEND BIT_2 /* RU Suspended */ 264 #define SCB_RUS_NO_RESOURCES BIT_3 /* RU Out Of Resources */ 265 #define SCB_RUS_READY BIT_4 /* RU Ready */ 266 #define SCB_RUS_SUSP_NO_RBDS (BIT_2 | BIT_5) /* RU No More RBDs */ 267 #define SCB_RUS_NO_RBDS (BIT_3 | BIT_5) /* RU No More RBDs */ 268 #define SCB_RUS_READY_NO_RBDS (BIT_4 | BIT_5) /* RU Ready, No RBDs */ 269 270 /* SCB Command Word bit definitions */ 271 /*- CUC fields */ 272 /* Changing mask to 4 bits */ 273 #define SCB_CUC_MASK BIT_4_7 /* CUC 4-bit Mask */ 274 #define SCB_CUC_NOOP 0 275 #define SCB_CUC_START BIT_4 /* CU Start */ 276 #define SCB_CUC_RESUME BIT_5 /* CU Resume */ 277 #define SCB_CUC_UNKNOWN BIT_7 /* CU unknown command */ 278 /* Changed for 82558 enhancements */ 279 #define SCB_CUC_STATIC_RESUME (BIT_5 | BIT_7) /* 82558/9 Static Resume */ 280 #define SCB_CUC_DUMP_ADDR BIT_6 /* CU Dump Counters Address */ 281 #define SCB_CUC_DUMP_STAT (BIT_4 | BIT_6) /* CU Dump stat. counters */ 282 #define SCB_CUC_LOAD_BASE (BIT_5 | BIT_6) /* Load the CU base */ 283 /* Below was defined as BIT_4_7 */ 284 #define SCB_CUC_DUMP_RST_STAT BIT_4_6 /* CU Dump & reset statistics cntrs */ 285 286 /*- RUC fields */ 287 #define SCB_RUC_MASK BIT_0_2 /* RUC 3-bit Mask */ 288 #define SCB_RUC_START BIT_0 /* RU Start */ 289 #define SCB_RUC_RESUME BIT_1 /* RU Resume */ 290 #define SCB_RUC_ABORT BIT_2 /* RU Abort */ 291 #define SCB_RUC_LOAD_HDS (BIT_0 | BIT_2) /* Load RFD Header Data Size */ 292 #define SCB_RUC_LOAD_BASE (BIT_1 | BIT_2) /* Load the RU base */ 293 #define SCB_RUC_RBD_RESUME BIT_0_2 /* RBD resume */ 294 295 /* Interrupt fields (assuming byte addressing) */ 296 #define SCB_INT_MASK BIT_0 /* Mask interrupts */ 297 #define SCB_SOFT_INT BIT_1 /* Generate a S/W interrupt */ 298 /* Specific Interrupt Mask Bits (upper byte of SCB Command word) */ 299 #define SCB_FCP_INT_MASK BIT_2 /* Flow Control Pause */ 300 #define SCB_ER_INT_MASK BIT_3 /* Early Receive */ 301 #define SCB_RNR_INT_MASK BIT_4 /* RU Not Ready */ 302 #define SCB_CNA_INT_MASK BIT_5 /* CU Not Active */ 303 #define SCB_FR_INT_MASK BIT_6 /* Frame Received */ 304 #define SCB_CX_INT_MASK BIT_7 /* CU eXecution w/ I-bit done */ 305 #define SCB_BACHELOR_INT_MASK BIT_2_7 /* 82558 interrupt mask bits */ 306 307 #define SCB_GCR2_EEPROM_ACCESS_SEMAPHORE BIT_7 308 309 /* EEPROM bit definitions */ 310 /*- EEPROM control register bits */ 311 #define EEPROM_FLAG_ASF 0x8000 312 #define EEPROM_FLAG_GCL 0x4000 313 314 #define EN_TRNF 0x10 /* Enable turnoff */ 315 #define EEDO 0x08 /* EEPROM data out */ 316 #define EEDI 0x04 /* EEPROM data in (set for writing data) */ 317 #define EECS 0x02 /* EEPROM chip select (1=hi, 0=lo) */ 318 #define EESK 0x01 /* EEPROM shift clock (1=hi, 0=lo) */ 319 320 /*- EEPROM opcodes */ 321 #define EEPROM_READ_OPCODE 06 322 #define EEPROM_WRITE_OPCODE 05 323 #define EEPROM_ERASE_OPCODE 07 324 #define EEPROM_EWEN_OPCODE 19 /* Erase/write enable */ 325 #define EEPROM_EWDS_OPCODE 16 /* Erase/write disable */ 326 327 /*- EEPROM data locations */ 328 #define EEPROM_NODE_ADDRESS_BYTE_0 0 329 #define EEPROM_COMPATIBILITY_WORD 3 330 #define EEPROM_PWA_NO 8 331 #define EEPROM_ID_WORD 0x0A 332 #define EEPROM_CONFIG_ASF 0x0D 333 #define EEPROM_SMBUS_ADDR 0x90 334 335 #define EEPROM_SUM 0xbaba 336 337 // Zero Locking Algorithm definitions: 338 #define ZLOCK_ZERO_MASK 0x00F0 339 #define ZLOCK_MAX_READS 50 340 #define ZLOCK_SET_ZERO 0x2010 341 #define ZLOCK_MAX_SLEEP 300 * HZ 342 #define ZLOCK_MAX_ERRORS 300 343 344 /* E100 Action Commands */ 345 #define CB_IA_ADDRESS 1 346 #define CB_CONFIGURE 2 347 #define CB_MULTICAST 3 348 #define CB_TRANSMIT 4 349 #define CB_LOAD_MICROCODE 5 350 #define CB_LOAD_FILTER 8 351 #define CB_MAX_NONTX_CMD 9 352 #define CB_IPCB_TRANSMIT 9 353 354 /* Pre-defined Filter Bits */ 355 #define CB_FILTER_EL 0x80000000 356 #define CB_FILTER_FIX 0x40000000 357 #define CB_FILTER_ARP 0x08000000 358 #define CB_FILTER_IA_MATCH 0x02000000 359 360 /* Command Block (CB) Field Definitions */ 361 /*- CB Command Word */ 362 #define CB_EL_BIT BIT_15 /* CB EL Bit */ 363 #define CB_S_BIT BIT_14 /* CB Suspend Bit */ 364 #define CB_I_BIT BIT_13 /* CB Interrupt Bit */ 365 #define CB_TX_SF_BIT BIT_3 /* TX CB Flexible Mode */ 366 #define CB_CMD_MASK BIT_0_3 /* CB 4-bit CMD Mask */ 367 #define CB_CID_DEFAULT (0x1f << 8) /* CB 5-bit CID (max value) */ 368 369 /*- CB Status Word */ 370 #define CB_STATUS_MASK BIT_12_15 /* CB Status Mask (4-bits) */ 371 #define CB_STATUS_COMPLETE BIT_15 /* CB Complete Bit */ 372 #define CB_STATUS_OK BIT_13 /* CB OK Bit */ 373 #define CB_STATUS_VLAN BIT_12 /* CB Valn detected Bit */ 374 #define CB_STATUS_FAIL BIT_11 /* CB Fail (F) Bit */ 375 376 /*misc command bits */ 377 #define CB_TX_EOF_BIT BIT_15 /* TX CB/TBD EOF Bit */ 378 379 /* Config params */ 380 #define CB_CFIG_BYTE_COUNT 22 /* 22 config bytes */ 381 #define CB_CFIG_D102_BYTE_COUNT 10 382 383 /* Receive Frame Descriptor Fields */ 384 385 /*- RFD Status Bits */ 386 #define RFD_RECEIVE_COLLISION BIT_0 /* Collision detected on Receive */ 387 #define RFD_IA_MATCH BIT_1 /* Indv Address Match Bit */ 388 #define RFD_RX_ERR BIT_4 /* RX_ERR pin on Phy was set */ 389 #define RFD_FRAME_TOO_SHORT BIT_7 /* Receive Frame Short */ 390 #define RFD_DMA_OVERRUN BIT_8 /* Receive DMA Overrun */ 391 #define RFD_NO_RESOURCES BIT_9 /* No Buffer Space */ 392 #define RFD_ALIGNMENT_ERROR BIT_10 /* Alignment Error */ 393 #define RFD_CRC_ERROR BIT_11 /* CRC Error */ 394 #define RFD_STATUS_OK BIT_13 /* RFD OK Bit */ 395 #define RFD_STATUS_COMPLETE BIT_15 /* RFD Complete Bit */ 396 397 /*- RFD Command Bits*/ 398 #define RFD_EL_BIT BIT_15 /* RFD EL Bit */ 399 #define RFD_S_BIT BIT_14 /* RFD Suspend Bit */ 400 #define RFD_H_BIT BIT_4 /* Header RFD Bit */ 401 #define RFD_SF_BIT BIT_3 /* RFD Flexible Mode */ 402 403 /*- RFD misc bits*/ 404 #define RFD_EOF_BIT BIT_15 /* RFD End-Of-Frame Bit */ 405 #define RFD_F_BIT BIT_14 /* RFD Buffer Fetch Bit */ 406 #define RFD_ACT_COUNT_MASK BIT_0_13 /* RFD Actual Count Mask */ 407 408 /* Receive Buffer Descriptor Fields*/ 409 #define RBD_EOF_BIT BIT_15 /* RBD End-Of-Frame Bit */ 410 #define RBD_F_BIT BIT_14 /* RBD Buffer Fetch Bit */ 411 #define RBD_ACT_COUNT_MASK BIT_0_13 /* RBD Actual Count Mask */ 412 413 #define SIZE_FIELD_MASK BIT_0_13 /* Size of the associated buffer */ 414 #define RBD_EL_BIT BIT_15 /* RBD EL Bit */ 415 416 /* Self Test Results*/ 417 #define CB_SELFTEST_FAIL_BIT BIT_12 418 #define CB_SELFTEST_DIAG_BIT BIT_5 419 #define CB_SELFTEST_REGISTER_BIT BIT_3 420 #define CB_SELFTEST_ROM_BIT BIT_2 421 422 #define CB_SELFTEST_ERROR_MASK ( \ 423 CB_SELFTEST_FAIL_BIT | CB_SELFTEST_DIAG_BIT | \ 424 CB_SELFTEST_REGISTER_BIT | CB_SELFTEST_ROM_BIT) 425 426 /* adapter vendor & device ids */ 427 #define PCI_OHIO_BOARD 0x10f0 /* subdevice ID, Ohio dual port nic */ 428 429 /* Values for PCI_REV_ID_REGISTER values */ 430 #define D101A4_REV_ID 4 /* 82558 A4 stepping */ 431 #define D101B0_REV_ID 5 /* 82558 B0 stepping */ 432 #define D101MA_REV_ID 8 /* 82559 A0 stepping */ 433 #define D101S_REV_ID 9 /* 82559S A-step */ 434 #define D102_REV_ID 12 435 #define D102C_REV_ID 13 /* 82550 step C */ 436 #define D102E_REV_ID 15 437 #define D102E_A1_REV_ID 16 438 439 /* ############Start of 82555 specific defines################## */ 440 441 #define PHY_82555_LED_SWITCH_CONTROL 0x1b /* 82555 led switch control register */ 442 443 /* 82555 led switch control reg. opcodes */ 444 #define PHY_82555_LED_NORMAL_CONTROL 0 // control back to the 8255X 445 #define PHY_82555_LED_DRIVER_CONTROL BIT_2 // the driver is in control 446 #define PHY_82555_LED_OFF BIT_2 // activity LED is off 447 #define PHY_82555_LED_ON_559 (BIT_0 | BIT_2) // activity LED is on for 559 and later 448 #define PHY_82555_LED_ON_PRE_559 (BIT_0 | BIT_1 | BIT_2) // activity LED is on for 558 and before 449 450 // Describe the state of the phy led. 451 // needed for the function : 'e100_blink_timer' 452 enum led_state_e { 453 LED_OFF = 0, 454 LED_ON, 455 }; 456 457 /* ############End of 82555 specific defines##################### */ 458 459 #define RFD_PARSE_BIT BIT_3 460 #define RFD_TCP_PACKET 0x00 461 #define RFD_UDP_PACKET 0x01 462 #define TCPUDP_CHECKSUM_BIT_VALID BIT_4 463 #define TCPUDP_CHECKSUM_VALID BIT_5 464 #define CHECKSUM_PROTOCOL_MASK 0x03 465 466 #define VLAN_SIZE 4 467 #define CHKSUM_SIZE 2 468 #define RFD_DATA_SIZE (ETH_FRAME_LEN + CHKSUM_SIZE + VLAN_SIZE) 469 470 /* Bits for bdp->flags */ 471 #define DF_LINK_FC_CAP 0x00000001 /* Link is flow control capable */ 472 #define DF_CSUM_OFFLOAD 0x00000002 473 #define DF_UCODE_LOADED 0x00000004 474 #define USE_IPCB 0x00000008 /* set if using ipcb for transmits */ 475 #define IS_BACHELOR 0x00000010 /* set if 82558 or newer board */ 476 #define IS_ICH 0x00000020 477 #define DF_SPEED_FORCED 0x00000040 /* set if speed is forced */ 478 #define LED_IS_ON 0x00000080 /* LED is turned ON by the driver */ 479 #define DF_LINK_FC_TX_ONLY 0x00000100 /* Received PAUSE frames are honored*/ 480 481 typedef struct net_device_stats net_dev_stats_t; 482 483 /* needed macros */ 484 /* These macros use the bdp pointer. If you use them it better be defined */ 485 #define PREV_TCB_USED(X) ((X).tail ? (X).tail - 1 : bdp->params.TxDescriptors - 1) 486 #define NEXT_TCB_TOUSE(X) ((((X) + 1) >= bdp->params.TxDescriptors) ? 0 : (X) + 1) 487 #define TCB_TO_USE(X) ((X).tail) 488 #define TCBS_AVAIL(X) (NEXT_TCB_TOUSE( NEXT_TCB_TOUSE((X).tail)) != (X).head) 489 490 #define RFD_POINTER(skb,bdp) ((rfd_t *) (((unsigned char *)((skb)->data))-((bdp)->rfd_size))) 491 #define SKB_RFD_STATUS(skb,bdp) ((RFD_POINTER((skb),(bdp)))->rfd_header.cb_status) 492 493 /* ====================================================================== */ 494 /* 82557 */ 495 /* ====================================================================== */ 496 497 /* Changed for 82558 enhancement */ 498 typedef struct _d101_scb_ext_t { 499 u32 scb_rx_dma_cnt; /* Rx DMA byte count */ 500 u8 scb_early_rx_int; /* Early Rx DMA byte count */ 501 u8 scb_fc_thld; /* Flow Control threshold */ 502 u8 scb_fc_xon_xoff; /* Flow Control XON/XOFF values */ 503 u8 scb_pmdr; /* Power Mgmt. Driver Reg */ 504 } __attribute__ ((__packed__)) d101_scb_ext; 505 506 /* Changed for 82559 enhancement */ 507 typedef struct _d101m_scb_ext_t { 508 u32 scb_rx_dma_cnt; /* Rx DMA byte count */ 509 u8 scb_early_rx_int; /* Early Rx DMA byte count */ 510 u8 scb_fc_thld; /* Flow Control threshold */ 511 u8 scb_fc_xon_xoff; /* Flow Control XON/XOFF values */ 512 u8 scb_pmdr; /* Power Mgmt. Driver Reg */ 513 u8 scb_gen_ctrl; /* General Control */ 514 u8 scb_gen_stat; /* General Status */ 515 u16 scb_reserved; /* Reserved */ 516 u32 scb_function_event; /* Cardbus Function Event */ 517 u32 scb_function_event_mask; /* Cardbus Function Mask */ 518 u32 scb_function_present_state; /* Cardbus Function state */ 519 u32 scb_force_event; /* Cardbus Force Event */ 520 } __attribute__ ((__packed__)) d101m_scb_ext; 521 522 /* Changed for 82550 enhancement */ 523 typedef struct _d102_scb_ext_t { 524 u32 scb_rx_dma_cnt; /* Rx DMA byte count */ 525 u8 scb_early_rx_int; /* Early Rx DMA byte count */ 526 u8 scb_fc_thld; /* Flow Control threshold */ 527 u8 scb_fc_xon_xoff; /* Flow Control XON/XOFF values */ 528 u8 scb_pmdr; /* Power Mgmt. Driver Reg */ 529 u8 scb_gen_ctrl; /* General Control */ 530 u8 scb_gen_stat; /* General Status */ 531 u8 scb_gen_ctrl2; 532 u8 scb_reserved; /* Reserved */ 533 u32 scb_scheduling_reg; 534 u32 scb_reserved2; 535 u32 scb_function_event; /* Cardbus Function Event */ 536 u32 scb_function_event_mask; /* Cardbus Function Mask */ 537 u32 scb_function_present_state; /* Cardbus Function state */ 538 u32 scb_force_event; /* Cardbus Force Event */ 539 } __attribute__ ((__packed__)) d102_scb_ext; 540 541 /* 542 * 82557 status control block. this will be memory mapped & will hang of the 543 * the bdp, which hangs of the bdp. This is the brain of it. 544 */ 545 typedef struct _scb_t { 546 u16 scb_status; /* SCB Status register */ 547 u8 scb_cmd_low; /* SCB Command register (low byte) */ 548 u8 scb_cmd_hi; /* SCB Command register (high byte) */ 549 u32 scb_gen_ptr; /* SCB General pointer */ 550 u32 scb_port; /* PORT register */ 551 u16 scb_flsh_cntrl; /* Flash Control register */ 552 u16 scb_eprm_cntrl; /* EEPROM control register */ 553 u32 scb_mdi_cntrl; /* MDI Control Register */ 554 /* Changed for 82558 enhancement */ 555 union { 556 u32 scb_rx_dma_cnt; /* Rx DMA byte count */ 557 d101_scb_ext d101_scb; /* 82558/9 specific fields */ 558 d101m_scb_ext d101m_scb; /* 82559 specific fields */ 559 d102_scb_ext d102_scb; 560 } scb_ext; 561 } __attribute__ ((__packed__)) scb_t; 562 563 /* Self test 564 * This is used to dump results of the self test 565 */ 566 typedef struct _self_test_t { 567 u32 st_sign; /* Self Test Signature */ 568 u32 st_result; /* Self Test Results */ 569 } __attribute__ ((__packed__)) self_test_t; 570 571 /* 572 * Statistical Counters 573 */ 574 /* 82557 counters */ 575 typedef struct _basic_cntr_t { 576 u32 xmt_gd_frames; /* Good frames transmitted */ 577 u32 xmt_max_coll; /* Fatal frames -- had max collisions */ 578 u32 xmt_late_coll; /* Fatal frames -- had a late coll. */ 579 u32 xmt_uruns; /* Xmit underruns (fatal or re-transmit) */ 580 u32 xmt_lost_crs; /* Frames transmitted without CRS */ 581 u32 xmt_deferred; /* Deferred transmits */ 582 u32 xmt_sngl_coll; /* Transmits that had 1 and only 1 coll. */ 583 u32 xmt_mlt_coll; /* Transmits that had multiple coll. */ 584 u32 xmt_ttl_coll; /* Transmits that had 1+ collisions. */ 585 u32 rcv_gd_frames; /* Good frames received */ 586 u32 rcv_crc_errs; /* Aligned frames that had a CRC error */ 587 u32 rcv_algn_errs; /* Receives that had alignment errors */ 588 u32 rcv_rsrc_err; /* Good frame dropped cuz no resources */ 589 u32 rcv_oruns; /* Overrun errors - bus was busy */ 590 u32 rcv_err_coll; /* Received frms. that encountered coll. */ 591 u32 rcv_shrt_frames; /* Received frames that were to short */ 592 } basic_cntr_t; 593 594 /* 82558 extended statistic counters */ 595 typedef struct _ext_cntr_t { 596 u32 xmt_fc_frames; 597 u32 rcv_fc_frames; 598 u32 rcv_fc_unsupported; 599 } ext_cntr_t; 600 601 /* 82559 TCO statistic counters */ 602 typedef struct _tco_cntr_t { 603 u16 xmt_tco_frames; 604 u16 rcv_tco_frames; 605 } tco_cntr_t; 606 607 /* Structures to access thet physical dump area */ 608 /* Use one of these types, according to the statisitcal counters mode, 609 to cast the pointer to the physical dump area and access the cmd_complete 610 DWORD. */ 611 612 /* 557-mode : only basic counters + cmd_complete */ 613 typedef struct _err_cntr_557_t { 614 basic_cntr_t basic_stats; 615 u32 cmd_complete; 616 } err_cntr_557_t; 617 618 /* 558-mode : basic + extended counters + cmd_complete */ 619 typedef struct _err_cntr_558_t { 620 basic_cntr_t basic_stats; 621 ext_cntr_t extended_stats; 622 u32 cmd_complete; 623 } err_cntr_558_t; 624 625 /* 559-mode : basic + extended + TCO counters + cmd_complete */ 626 typedef struct _err_cntr_559_t { 627 basic_cntr_t basic_stats; 628 ext_cntr_t extended_stats; 629 tco_cntr_t tco_stats; 630 u32 cmd_complete; 631 } err_cntr_559_t; 632 633 /* This typedef defines the struct needed to hold the largest number of counters */ 634 typedef err_cntr_559_t max_counters_t; 635 636 /* Different statistical-counters mode the controller may be in */ 637 typedef enum _stat_mode_t { 638 E100_BASIC_STATS = 0, /* 82557 stats : 16 counters / 16 dw */ 639 E100_EXTENDED_STATS, /* 82558 stats : 19 counters / 19 dw */ 640 E100_TCO_STATS /* 82559 stats : 21 counters / 20 dw */ 641 } stat_mode_t; 642 643 /* dump statistical counters complete codes */ 644 #define DUMP_STAT_COMPLETED 0xA005 645 #define DUMP_RST_STAT_COMPLETED 0xA007 646 647 /* Command Block (CB) Generic Header Structure*/ 648 typedef struct _cb_header_t { 649 u16 cb_status; /* Command Block Status */ 650 u16 cb_cmd; /* Command Block Command */ 651 u32 cb_lnk_ptr; /* Link To Next CB */ 652 } __attribute__ ((__packed__)) cb_header_t; 653 654 //* Individual Address Command Block (IA_CB)*/ 655 typedef struct _ia_cb_t { 656 cb_header_t ia_cb_hdr; 657 u8 ia_addr[ETH_ALEN]; 658 } __attribute__ ((__packed__)) ia_cb_t; 659 660 /* Configure Command Block (CONFIG_CB)*/ 661 typedef struct _config_cb_t { 662 cb_header_t cfg_cbhdr; 663 u8 cfg_byte[CB_CFIG_BYTE_COUNT + CB_CFIG_D102_BYTE_COUNT]; 664 } __attribute__ ((__packed__)) config_cb_t; 665 666 /* MultiCast Command Block (MULTICAST_CB)*/ 667 typedef struct _multicast_cb_t { 668 cb_header_t mc_cbhdr; 669 u16 mc_count; /* Number of multicast addresses */ 670 u8 mc_addr[(ETH_ALEN * MAX_MULTICAST_ADDRS)]; 671 } __attribute__ ((__packed__)) mltcst_cb_t; 672 673 #define UCODE_MAX_DWORDS 134 674 /* Load Microcode Command Block (LOAD_UCODE_CB)*/ 675 typedef struct _load_ucode_cb_t { 676 cb_header_t load_ucode_cbhdr; 677 u32 ucode_dword[UCODE_MAX_DWORDS]; 678 } __attribute__ ((__packed__)) load_ucode_cb_t; 679 680 /* Load Programmable Filter Data*/ 681 typedef struct _filter_cb_t { 682 cb_header_t filter_cb_hdr; 683 u32 filter_data[MAX_FILTER]; 684 } __attribute__ ((__packed__)) filter_cb_t; 685 686 /* NON_TRANSMIT_CB -- Generic Non-Transmit Command Block 687 */ 688 typedef struct _nxmit_cb_t { 689 union { 690 config_cb_t config; 691 ia_cb_t setup; 692 load_ucode_cb_t load_ucode; 693 mltcst_cb_t multicast; 694 filter_cb_t filter; 695 } ntcb; 696 } __attribute__ ((__packed__)) nxmit_cb_t; 697 698 /*Block for queuing for postponed execution of the non-transmit commands*/ 699 typedef struct _nxmit_cb_entry_t { 700 struct list_head list_elem; 701 nxmit_cb_t *non_tx_cmd; 702 dma_addr_t dma_addr; 703 unsigned long expiration_time; 704 } nxmit_cb_entry_t; 705 706 /* States for postponed non tx commands execution */ 707 typedef enum _non_tx_cmd_state_t { 708 E100_NON_TX_IDLE = 0, /* No queued NON-TX commands */ 709 E100_WAIT_TX_FINISH, /* Wait for completion of the TX activities */ 710 E100_WAIT_NON_TX_FINISH /* Wait for completion of the non TX command */ 711 } non_tx_cmd_state_t; 712 713 /* some defines for the ipcb */ 714 #define IPCB_IP_CHECKSUM_ENABLE BIT_4 715 #define IPCB_TCPUDP_CHECKSUM_ENABLE BIT_5 716 #define IPCB_TCP_PACKET BIT_6 717 #define IPCB_LARGESEND_ENABLE BIT_7 718 #define IPCB_HARDWAREPARSING_ENABLE BIT_0 719 #define IPCB_INSERTVLAN_ENABLE BIT_1 720 #define IPCB_IP_ACTIVATION_DEFAULT IPCB_HARDWAREPARSING_ENABLE 721 722 /* Transmit Buffer Descriptor (TBD)*/ 723 typedef struct _tbd_t { 724 u32 tbd_buf_addr; /* Physical Transmit Buffer Address */ 725 u16 tbd_buf_cnt; /* Actual Count Of Bytes */ 726 u16 padd; 727 } __attribute__ ((__packed__)) tbd_t; 728 729 /* d102 specific fields */ 730 typedef struct _tcb_ipcb_t { 731 u16 schedule_low; 732 u8 ip_schedule; 733 u8 ip_activation_high; 734 u16 vlan; 735 u8 ip_header_offset; 736 u8 tcp_header_offset; 737 union { 738 u32 sec_rec_phys_addr; 739 u32 tbd_zero_address; 740 } tbd_sec_addr; 741 union { 742 u16 sec_rec_size; 743 u16 tbd_zero_size; 744 } tbd_sec_size; 745 u16 total_tcp_payload; 746 } __attribute__ ((__packed__)) tcb_ipcb_t; 747 748 #define E100_TBD_ARRAY_SIZE (2+MAX_SKB_FRAGS) 749 750 /* Transmit Command Block (TCB)*/ 751 struct _tcb_t { 752 cb_header_t tcb_hdr; 753 u32 tcb_tbd_ptr; /* TBD address */ 754 u16 tcb_cnt; /* Data Bytes In TCB past header */ 755 u8 tcb_thrshld; /* TX Threshold for FIFO Extender */ 756 u8 tcb_tbd_num; 757 758 union { 759 tcb_ipcb_t ipcb; /* d102 ipcb fields */ 760 tbd_t tbd_array[E100_TBD_ARRAY_SIZE]; 761 } tcbu; 762 763 /* From here onward we can dump anything we want as long as the 764 * size of the total structure is a multiple of a paragraph 765 * boundary ( i.e. -16 bit aligned ). 766 */ 767 tbd_t *tbd_ptr; 768 769 u32 tcb_tbd_dflt_ptr; /* TBD address for non-segmented packet */ 770 u32 tcb_tbd_expand_ptr; /* TBD address for segmented packet */ 771 772 struct sk_buff *tcb_skb; /* the associated socket buffer */ 773 dma_addr_t tcb_phys; /* phys addr of the TCB */ 774 } __attribute__ ((__packed__)); 775 776 #define _TCB_T_ 777 typedef struct _tcb_t tcb_t; 778 779 /* Receive Frame Descriptor (RFD) - will be using the simple model*/ 780 struct _rfd_t { 781 /* 8255x */ 782 cb_header_t rfd_header; 783 u32 rfd_rbd_ptr; /* Receive Buffer Descriptor Addr */ 784 u16 rfd_act_cnt; /* Number Of Bytes Received */ 785 u16 rfd_sz; /* Number Of Bytes In RFD */ 786 /* D102 aka Gamla */ 787 u16 vlanid; 788 u8 rcvparserstatus; 789 u8 reserved; 790 u16 securitystatus; 791 u8 checksumstatus; 792 u8 zerocopystatus; 793 u8 pad[8]; /* data should be 16 byte aligned */ 794 u8 data[RFD_DATA_SIZE]; 795 796 } __attribute__ ((__packed__)); 797 798 #define _RFD_T_ 799 typedef struct _rfd_t rfd_t; 800 801 /* Receive Buffer Descriptor (RBD)*/ 802 typedef struct _rbd_t { 803 u16 rbd_act_cnt; /* Number Of Bytes Received */ 804 u16 rbd_filler; 805 u32 rbd_lnk_addr; /* Link To Next RBD */ 806 u32 rbd_rcb_addr; /* Receive Buffer Address */ 807 u16 rbd_sz; /* Receive Buffer Size */ 808 u16 rbd_filler1; 809 } __attribute__ ((__packed__)) rbd_t; 810 811 /* 812 * This structure is used to maintain a FIFO access to a resource that is 813 * maintained as a circular queue. The resource to be maintained is pointed 814 * to by the "data" field in the structure below. In this driver the TCBs', 815 * TBDs' & RFDs' are maintained as a circular queue & are managed thru this 816 * structure. 817 */ 818 typedef struct _buf_pool_t { 819 unsigned int head; /* index to first used resource */ 820 unsigned int tail; /* index to last used resource */ 821 void *data; /* points to resource pool */ 822 } buf_pool_t; 823 824 /*Rx skb holding structure*/ 825 struct rx_list_elem { 826 struct list_head list_elem; 827 dma_addr_t dma_addr; 828 struct sk_buff *skb; 829 }; 830 831 enum next_cu_cmd_e { RESUME_NO_WAIT = 0, RESUME_WAIT, START_WAIT }; 832 enum zlock_state_e { ZLOCK_INITIAL, ZLOCK_READING, ZLOCK_SLEEPING }; 833 enum tx_queue_stop_type { LONG_STOP = 0, SHORT_STOP }; 834 835 /* 64 bit aligned size */ 836 #define E100_SIZE_64A(X) ((sizeof(X) + 7) & ~0x7) 837 838 typedef struct _bd_dma_able_t { 839 char selftest[E100_SIZE_64A(self_test_t)]; 840 char stats_counters[E100_SIZE_64A(max_counters_t)]; 841 } bd_dma_able_t; 842 843 /* bit masks for bool parameters */ 844 #define PRM_XSUMRX 0x00000001 845 #define PRM_UCODE 0x00000002 846 #define PRM_FC 0x00000004 847 #define PRM_IFS 0x00000008 848 #define PRM_BUNDLE_SMALL 0x00000010 849 850 struct cfg_params { 851 int e100_speed_duplex; 852 int RxDescriptors; 853 int TxDescriptors; 854 int IntDelay; 855 int BundleMax; 856 int ber; 857 u32 b_params; 858 }; 859 struct ethtool_lpbk_data{ 860 dma_addr_t dma_handle; 861 tcb_t *tcb; 862 rfd_t *rfd; 863 864 }; 865 866 struct e100_private { 867 struct vlan_group *vlgrp; 868 u32 flags; /* board management flags */ 869 u32 tx_per_underrun; /* number of good tx frames per underrun */ 870 unsigned int tx_count; /* count of tx frames, so we can request an interrupt */ 871 u8 tx_thld; /* stores transmit threshold */ 872 u16 eeprom_size; 873 u32 pwa_no; /* PWA: xxxxxx-0xx */ 874 u8 perm_node_address[ETH_ALEN]; 875 struct list_head active_rx_list; /* list of rx buffers */ 876 struct list_head rx_struct_pool; /* pool of rx buffer struct headers */ 877 u16 rfd_size; /* size of the adapter's RFD struct */ 878 int skb_req; /* number of skbs neede by the adapter */ 879 u8 intr_mask; /* mask for interrupt status */ 880 881 void *dma_able; /* dma allocated structs */ 882 dma_addr_t dma_able_phys; 883 self_test_t *selftest; /* pointer to self test area */ 884 dma_addr_t selftest_phys; /* phys addr of selftest */ 885 max_counters_t *stats_counters; /* pointer to stats table */ 886 dma_addr_t stat_cnt_phys; /* phys addr of stat counter area */ 887 888 stat_mode_t stat_mode; /* statistics mode: extended, TCO, basic */ 889 scb_t *scb; /* memory mapped ptr to 82557 scb */ 890 891 tcb_t *last_tcb; /* pointer to last tcb sent */ 892 buf_pool_t tcb_pool; /* adapter's TCB array */ 893 dma_addr_t tcb_phys; /* phys addr of start of TCBs */ 894 895 u16 cur_line_speed; 896 u16 cur_dplx_mode; 897 898 struct net_device *device; 899 struct pci_dev *pdev; 900 struct driver_stats drv_stats; 901 902 u8 rev_id; /* adapter PCI revision ID */ 903 904 unsigned int phy_addr; /* address of PHY component */ 905 unsigned int PhyId; /* ID of PHY component */ 906 unsigned int PhyState; /* state for the fix squelch algorithm */ 907 unsigned int PhyDelay; /* delay for the fix squelch algorithm */ 908 909 /* Lock defintions for the driver */ 910 spinlock_t bd_lock; /* board lock */ 911 spinlock_t bd_non_tx_lock; /* Non transmit command lock */ 912 spinlock_t config_lock; /* config block lock */ 913 spinlock_t mdi_access_lock; /* mdi lock */ 914 915 struct timer_list watchdog_timer; /* watchdog timer id */ 916 917 /* non-tx commands parameters */ 918 struct timer_list nontx_timer_id; /* non-tx timer id */ 919 struct list_head non_tx_cmd_list; 920 non_tx_cmd_state_t non_tx_command_state; 921 nxmit_cb_entry_t *same_cmd_entry[CB_MAX_NONTX_CMD]; 922 923 enum next_cu_cmd_e next_cu_cmd; 924 925 /* Zero Locking Algorithm data members */ 926 enum zlock_state_e zlock_state; 927 u8 zlock_read_data[16]; /* number of times each value 0-15 was read */ 928 u16 zlock_read_cnt; /* counts number of reads */ 929 ulong zlock_sleep_cnt; /* keeps track of "sleep" time */ 930 931 u8 config[CB_CFIG_BYTE_COUNT + CB_CFIG_D102_BYTE_COUNT]; 932 933 /* IFS params */ 934 u8 ifs_state; 935 u8 ifs_value; 936 937 struct cfg_params params; /* adapter's command line parameters */ 938 939 u32 speed_duplex_caps; /* adapter's speed/duplex capabilities */ 940 941 /* WOL params for ethtool */ 942 u32 wolsupported; 943 u32 wolopts; 944 u16 ip_lbytes; 945 struct ethtool_lpbk_data loopback; 946 struct timer_list blink_timer; /* led blink timer id */ 947 948 #ifdef CONFIG_PM 949 u32 pci_state[16]; 950 #endif 951 #ifdef E100_CU_DEBUG 952 u8 last_cmd; 953 u8 last_sub_cmd; 954 #endif 955 }; 956 957 #define E100_AUTONEG 0 958 #define E100_SPEED_10_HALF 1 959 #define E100_SPEED_10_FULL 2 960 #define E100_SPEED_100_HALF 3 961 #define E100_SPEED_100_FULL 4 962 963 /********* function prototypes *************/ 964 extern int e100_open(struct net_device *); 965 extern int e100_close(struct net_device *); 966 extern void e100_isolate_driver(struct e100_private *bdp); 967 extern unsigned char e100_hw_init(struct e100_private *); 968 extern void e100_sw_reset(struct e100_private *bdp, u32 reset_cmd); 969 extern u8 e100_start_cu(struct e100_private *bdp, tcb_t *tcb); 970 extern void e100_free_non_tx_cmd(struct e100_private *bdp, 971 nxmit_cb_entry_t *non_tx_cmd); 972 extern nxmit_cb_entry_t *e100_alloc_non_tx_cmd(struct e100_private *bdp); 973 extern unsigned char e100_exec_non_cu_cmd(struct e100_private *bdp, 974 nxmit_cb_entry_t *cmd); 975 extern unsigned char e100_selftest(struct e100_private *bdp, u32 *st_timeout, 976 u32 *st_result); 977 extern unsigned char e100_get_link_state(struct e100_private *bdp); 978 extern unsigned char e100_wait_scb(struct e100_private *bdp); 979 980 extern void e100_deisolate_driver(struct e100_private *bdp, u8 full_reset); 981 extern unsigned char e100_configure_device(struct e100_private *bdp); 982 #ifdef E100_CU_DEBUG 983 extern unsigned char e100_cu_unknown_state(struct e100_private *bdp); 984 #endif 985 986 #define ROM_TEST_FAIL 0x01 987 #define REGISTER_TEST_FAIL 0x02 988 #define SELF_TEST_FAIL 0x04 989 #define TEST_TIMEOUT 0x08 990 991 enum test_offsets { 992 test_link, 993 test_eeprom, 994 test_self_test, 995 test_loopback_mac, 996 test_loopback_phy, 997 cable_diag, 998 max_test_res, /* must be last */ 999 }; 1000 1001 #endif 1002