1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7 #ifndef _ROCKCHIP_DRM_VOP_H
8 #define _ROCKCHIP_DRM_VOP_H
9
10 /*
11 * major: IP major version, used for IP structure
12 * minor: big feature change under same structure
13 */
14 #define VOP_VERSION(major, minor) ((major) << 8 | (minor))
15 #define VOP_MAJOR(version) ((version) >> 8)
16 #define VOP_MINOR(version) ((version) & 0xff)
17
18 #define NUM_YUV2YUV_COEFFICIENTS 12
19
20 /* AFBC supports a number of configurable modes. Relevant to us is block size
21 * (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like
22 * colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode
23 * could be enabled via the hreg_block_split register, but is not currently
24 * handled. The colourspace transform is implicitly always assumed by the
25 * decoder, so consumers must use this transform as well.
26 *
27 * Failure to match modifiers will cause errors displaying AFBC buffers
28 * produced by conformant AFBC producers, including Mesa.
29 */
30 #define ROCKCHIP_AFBC_MOD \
31 DRM_FORMAT_MOD_ARM_AFBC( \
32 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE \
33 | AFBC_FORMAT_MOD_YTR \
34 )
35
36 enum vop_data_format {
37 VOP_FMT_ARGB8888 = 0,
38 VOP_FMT_RGB888,
39 VOP_FMT_RGB565,
40 VOP_FMT_YUV420SP = 4,
41 VOP_FMT_YUV422SP,
42 VOP_FMT_YUV444SP,
43 };
44
45 struct vop_rect {
46 int width;
47 int height;
48 };
49
50 struct vop_reg {
51 uint32_t mask;
52 uint16_t offset;
53 uint8_t shift;
54 bool write_mask;
55 bool relaxed;
56 };
57
58 struct vop_afbc {
59 struct vop_reg enable;
60 struct vop_reg win_sel;
61 struct vop_reg format;
62 struct vop_reg rb_swap;
63 struct vop_reg uv_swap;
64 struct vop_reg auto_gating_en;
65 struct vop_reg block_split_en;
66 struct vop_reg pic_vir_width;
67 struct vop_reg tile_num;
68 struct vop_reg hreg_block_split;
69 struct vop_reg pic_offset;
70 struct vop_reg pic_size;
71 struct vop_reg dsp_offset;
72 struct vop_reg transform_offset;
73 struct vop_reg hdr_ptr;
74 struct vop_reg half_block_en;
75 struct vop_reg xmirror;
76 struct vop_reg ymirror;
77 struct vop_reg rotate_270;
78 struct vop_reg rotate_90;
79 struct vop_reg rstn;
80 };
81
82 struct vop_modeset {
83 struct vop_reg htotal_pw;
84 struct vop_reg hact_st_end;
85 struct vop_reg hpost_st_end;
86 struct vop_reg vtotal_pw;
87 struct vop_reg vact_st_end;
88 struct vop_reg vpost_st_end;
89 };
90
91 struct vop_output {
92 struct vop_reg pin_pol;
93 struct vop_reg dp_pin_pol;
94 struct vop_reg dp_dclk_pol;
95 struct vop_reg edp_pin_pol;
96 struct vop_reg edp_dclk_pol;
97 struct vop_reg hdmi_pin_pol;
98 struct vop_reg hdmi_dclk_pol;
99 struct vop_reg mipi_pin_pol;
100 struct vop_reg mipi_dclk_pol;
101 struct vop_reg rgb_pin_pol;
102 struct vop_reg rgb_dclk_pol;
103 struct vop_reg dp_en;
104 struct vop_reg edp_en;
105 struct vop_reg hdmi_en;
106 struct vop_reg mipi_en;
107 struct vop_reg mipi_dual_channel_en;
108 struct vop_reg rgb_en;
109 };
110
111 struct vop_common {
112 struct vop_reg cfg_done;
113 struct vop_reg dsp_blank;
114 struct vop_reg data_blank;
115 struct vop_reg pre_dither_down;
116 struct vop_reg dither_down_sel;
117 struct vop_reg dither_down_mode;
118 struct vop_reg dither_down_en;
119 struct vop_reg dither_up;
120 struct vop_reg dsp_lut_en;
121 struct vop_reg update_gamma_lut;
122 struct vop_reg lut_buffer_index;
123 struct vop_reg gate_en;
124 struct vop_reg mmu_en;
125 struct vop_reg out_mode;
126 struct vop_reg standby;
127 };
128
129 struct vop_misc {
130 struct vop_reg global_regdone_en;
131 };
132
133 struct vop_intr {
134 const int *intrs;
135 uint32_t nintrs;
136
137 struct vop_reg line_flag_num[2];
138 struct vop_reg enable;
139 struct vop_reg clear;
140 struct vop_reg status;
141 };
142
143 struct vop_scl_extension {
144 struct vop_reg cbcr_vsd_mode;
145 struct vop_reg cbcr_vsu_mode;
146 struct vop_reg cbcr_hsd_mode;
147 struct vop_reg cbcr_ver_scl_mode;
148 struct vop_reg cbcr_hor_scl_mode;
149 struct vop_reg yrgb_vsd_mode;
150 struct vop_reg yrgb_vsu_mode;
151 struct vop_reg yrgb_hsd_mode;
152 struct vop_reg yrgb_ver_scl_mode;
153 struct vop_reg yrgb_hor_scl_mode;
154 struct vop_reg line_load_mode;
155 struct vop_reg cbcr_axi_gather_num;
156 struct vop_reg yrgb_axi_gather_num;
157 struct vop_reg vsd_cbcr_gt2;
158 struct vop_reg vsd_cbcr_gt4;
159 struct vop_reg vsd_yrgb_gt2;
160 struct vop_reg vsd_yrgb_gt4;
161 struct vop_reg bic_coe_sel;
162 struct vop_reg cbcr_axi_gather_en;
163 struct vop_reg yrgb_axi_gather_en;
164 struct vop_reg lb_mode;
165 };
166
167 struct vop_scl_regs {
168 const struct vop_scl_extension *ext;
169
170 struct vop_reg scale_yrgb_x;
171 struct vop_reg scale_yrgb_y;
172 struct vop_reg scale_cbcr_x;
173 struct vop_reg scale_cbcr_y;
174 };
175
176 struct vop_yuv2yuv_phy {
177 struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS];
178 };
179
180 struct vop_win_phy {
181 const struct vop_scl_regs *scl;
182 const uint32_t *data_formats;
183 uint32_t nformats;
184 const uint64_t *format_modifiers;
185
186 struct vop_reg enable;
187 struct vop_reg gate;
188 struct vop_reg format;
189 struct vop_reg rb_swap;
190 struct vop_reg uv_swap;
191 struct vop_reg act_info;
192 struct vop_reg dsp_info;
193 struct vop_reg dsp_st;
194 struct vop_reg yrgb_mst;
195 struct vop_reg uv_mst;
196 struct vop_reg yrgb_vir;
197 struct vop_reg uv_vir;
198 struct vop_reg y_mir_en;
199 struct vop_reg x_mir_en;
200
201 struct vop_reg dst_alpha_ctl;
202 struct vop_reg src_alpha_ctl;
203 struct vop_reg alpha_pre_mul;
204 struct vop_reg alpha_mode;
205 struct vop_reg alpha_en;
206 struct vop_reg channel;
207 };
208
209 struct vop_win_yuv2yuv_data {
210 uint32_t base;
211 const struct vop_yuv2yuv_phy *phy;
212 struct vop_reg y2r_en;
213 };
214
215 struct vop_win_data {
216 uint32_t base;
217 const struct vop_win_phy *phy;
218 enum drm_plane_type type;
219 };
220
221 struct vop_data {
222 uint32_t version;
223 const struct vop_intr *intr;
224 const struct vop_common *common;
225 const struct vop_misc *misc;
226 const struct vop_modeset *modeset;
227 const struct vop_output *output;
228 const struct vop_afbc *afbc;
229 const struct vop_win_yuv2yuv_data *win_yuv2yuv;
230 const struct vop_win_data *win;
231 unsigned int win_size;
232 unsigned int lut_size;
233 struct vop_rect max_output;
234
235 #define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
236 #define VOP_FEATURE_INTERNAL_RGB BIT(1)
237 u64 feature;
238 };
239
240 /* interrupt define */
241 #define DSP_HOLD_VALID_INTR (1 << 0)
242 #define FS_INTR (1 << 1)
243 #define LINE_FLAG_INTR (1 << 2)
244 #define BUS_ERROR_INTR (1 << 3)
245
246 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
247 LINE_FLAG_INTR | BUS_ERROR_INTR)
248
249 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
250 #define FS_INTR_EN(x) ((x) << 5)
251 #define LINE_FLAG_INTR_EN(x) ((x) << 6)
252 #define BUS_ERROR_INTR_EN(x) ((x) << 7)
253 #define DSP_HOLD_VALID_INTR_MASK (1 << 4)
254 #define FS_INTR_MASK (1 << 5)
255 #define LINE_FLAG_INTR_MASK (1 << 6)
256 #define BUS_ERROR_INTR_MASK (1 << 7)
257
258 #define INTR_CLR_SHIFT 8
259 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
260 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
261 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
262 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
263
264 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
265 #define DSP_LINE_NUM_MASK (0x1fff << 12)
266
267 /* src alpha ctrl define */
268 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
269 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
270 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
271 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
272 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
273 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
274 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
275 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
276 /* dst alpha ctrl define */
277 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
278
279 /*
280 * display output interface supported by rockchip lcdc
281 */
282 #define ROCKCHIP_OUT_MODE_P888 0
283 #define ROCKCHIP_OUT_MODE_P666 1
284 #define ROCKCHIP_OUT_MODE_P565 2
285 /* for use special outface */
286 #define ROCKCHIP_OUT_MODE_AAAA 15
287
288 /* output flags */
289 #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0)
290
291 enum alpha_mode {
292 ALPHA_STRAIGHT,
293 ALPHA_INVERSE,
294 };
295
296 enum global_blend_mode {
297 ALPHA_GLOBAL,
298 ALPHA_PER_PIX,
299 ALPHA_PER_PIX_GLOBAL,
300 };
301
302 enum alpha_cal_mode {
303 ALPHA_SATURATION,
304 ALPHA_NO_SATURATION,
305 };
306
307 enum color_mode {
308 ALPHA_SRC_PRE_MUL,
309 ALPHA_SRC_NO_PRE_MUL,
310 };
311
312 enum factor_mode {
313 ALPHA_ZERO,
314 ALPHA_ONE,
315 ALPHA_SRC,
316 ALPHA_SRC_INVERSE,
317 ALPHA_SRC_GLOBAL,
318 };
319
320 enum scale_mode {
321 SCALE_NONE = 0x0,
322 SCALE_UP = 0x1,
323 SCALE_DOWN = 0x2
324 };
325
326 enum lb_mode {
327 LB_YUV_3840X5 = 0x0,
328 LB_YUV_2560X8 = 0x1,
329 LB_RGB_3840X2 = 0x2,
330 LB_RGB_2560X4 = 0x3,
331 LB_RGB_1920X5 = 0x4,
332 LB_RGB_1280X8 = 0x5
333 };
334
335 enum sacle_up_mode {
336 SCALE_UP_BIL = 0x0,
337 SCALE_UP_BIC = 0x1
338 };
339
340 enum scale_down_mode {
341 SCALE_DOWN_BIL = 0x0,
342 SCALE_DOWN_AVG = 0x1
343 };
344
345 enum dither_down_mode {
346 RGB888_TO_RGB565 = 0x0,
347 RGB888_TO_RGB666 = 0x1
348 };
349
350 enum dither_down_mode_sel {
351 DITHER_DOWN_ALLEGRO = 0x0,
352 DITHER_DOWN_FRC = 0x1
353 };
354
355 enum vop_pol {
356 HSYNC_POSITIVE = 0,
357 VSYNC_POSITIVE = 1,
358 DEN_NEGATIVE = 2
359 };
360
361 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
362 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
363 #define SCL_MAX_VSKIPLINES 4
364 #define MIN_SCL_FT_AFTER_VSKIP 1
365
scl_cal_scale(int src,int dst,int shift)366 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
367 {
368 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
369 }
370
scl_cal_scale2(int src,int dst)371 static inline uint16_t scl_cal_scale2(int src, int dst)
372 {
373 return ((src - 1) << 12) / (dst - 1);
374 }
375
376 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
377 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
378 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
379
scl_get_bili_dn_vskip(int src_h,int dst_h,int vskiplines)380 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
381 int vskiplines)
382 {
383 int act_height;
384
385 act_height = DIV_ROUND_UP(src_h, vskiplines);
386
387 if (act_height == dst_h)
388 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
389
390 return GET_SCL_FT_BILI_DN(act_height, dst_h);
391 }
392
scl_get_scl_mode(int src,int dst)393 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
394 {
395 if (src < dst)
396 return SCALE_UP;
397 else if (src > dst)
398 return SCALE_DOWN;
399
400 return SCALE_NONE;
401 }
402
scl_get_vskiplines(uint32_t srch,uint32_t dsth)403 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
404 {
405 uint32_t vskiplines;
406
407 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
408 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
409 break;
410
411 return vskiplines;
412 }
413
scl_vop_cal_lb_mode(int width,bool is_yuv)414 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
415 {
416 int lb_mode;
417
418 if (is_yuv) {
419 if (width > 1280)
420 lb_mode = LB_YUV_3840X5;
421 else
422 lb_mode = LB_YUV_2560X8;
423 } else {
424 if (width > 2560)
425 lb_mode = LB_RGB_3840X2;
426 else if (width > 1920)
427 lb_mode = LB_RGB_2560X4;
428 else
429 lb_mode = LB_RGB_1920X5;
430 }
431
432 return lb_mode;
433 }
434
435 extern const struct component_ops vop_component_ops;
436 #endif /* _ROCKCHIP_DRM_VOP_H */
437