1 /* MN10300 on-board serial port module registers 2 * 3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public Licence 8 * as published by the Free Software Foundation; either version 9 * 2 of the Licence, or (at your option) any later version. 10 */ 11 12 #ifndef _ASM_SERIAL_REGS_H 13 #define _ASM_SERIAL_REGS_H 14 15 #include <asm/cpu-regs.h> 16 #include <asm/intctl-regs.h> 17 18 #ifdef __KERNEL__ 19 20 /* serial port 0 */ 21 #define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */ 22 #define SC01CTR_CK 0x0007 /* clock source select */ 23 #define SC01CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */ 24 #define SC01CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */ 25 #define SC01CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */ 26 #define SC01CTR_CK_EXTERN 0x0007 /* - external closk */ 27 #if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) 28 #define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */ 29 #define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */ 30 #define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 0 underflow (serial port 0 only) */ 31 #define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */ 32 #define SC1CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow (serial port 1 only) */ 33 #define SC1CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow (serial port 1 only) */ 34 #define SC1CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 1 underflow (serial port 1 only) */ 35 #define SC1CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow (serial port 1 only) */ 36 #else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ 37 #define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */ 38 #define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 0 underflow (serial port 0 only) */ 39 #define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */ 40 #define SC1CTR_CK_TM12UFLOW_8 0x0000 /* - 1/8 timer 12 underflow (serial port 1 only) */ 41 #endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ 42 #define SC01CTR_STB 0x0008 /* stop bit select */ 43 #define SC01CTR_STB_1BIT 0x0000 /* - 1 stop bit */ 44 #define SC01CTR_STB_2BIT 0x0008 /* - 2 stop bits */ 45 #define SC01CTR_PB 0x0070 /* parity bit select */ 46 #define SC01CTR_PB_NONE 0x0000 /* - no parity */ 47 #define SC01CTR_PB_FIXED0 0x0040 /* - fixed at 0 */ 48 #define SC01CTR_PB_FIXED1 0x0050 /* - fixed at 1 */ 49 #define SC01CTR_PB_EVEN 0x0060 /* - even parity */ 50 #define SC01CTR_PB_ODD 0x0070 /* - odd parity */ 51 #define SC01CTR_CLN 0x0080 /* character length */ 52 #define SC01CTR_CLN_7BIT 0x0000 /* - 7 bit chars */ 53 #define SC01CTR_CLN_8BIT 0x0080 /* - 8 bit chars */ 54 #define SC01CTR_TOE 0x0100 /* T input output enable */ 55 #define SC01CTR_OD 0x0200 /* bit order select */ 56 #define SC01CTR_OD_LSBFIRST 0x0000 /* - LSB first */ 57 #define SC01CTR_OD_MSBFIRST 0x0200 /* - MSB first */ 58 #define SC01CTR_MD 0x0c00 /* mode select */ 59 #define SC01CTR_MD_STST_SYNC 0x0000 /* - start-stop synchronous */ 60 #define SC01CTR_MD_CLOCK_SYNC1 0x0400 /* - clock synchronous 1 */ 61 #define SC01CTR_MD_I2C 0x0800 /* - I2C mode */ 62 #define SC01CTR_MD_CLOCK_SYNC2 0x0c00 /* - clock synchronous 2 */ 63 #define SC01CTR_IIC 0x1000 /* I2C mode select */ 64 #define SC01CTR_BKE 0x2000 /* break transmit enable */ 65 #define SC01CTR_RXE 0x4000 /* receive enable */ 66 #define SC01CTR_TXE 0x8000 /* transmit enable */ 67 68 #define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */ 69 #define SC01ICR_DMD 0x80 /* output data mode */ 70 #define SC01ICR_TD 0x20 /* transmit DMA trigger cause */ 71 #define SC01ICR_TI 0x10 /* transmit interrupt cause */ 72 #define SC01ICR_RES 0x04 /* receive error select */ 73 #define SC01ICR_RI 0x01 /* receive interrupt cause */ 74 75 #define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */ 76 #define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */ 77 78 #define SC0STR __SYSREG(0xd400200c, u16) /* status reg */ 79 #define SC01STR_OEF 0x0001 /* overrun error found */ 80 #define SC01STR_PEF 0x0002 /* parity error found */ 81 #define SC01STR_FEF 0x0004 /* framing error found */ 82 #define SC01STR_RBF 0x0010 /* receive buffer status */ 83 #define SC01STR_TBF 0x0020 /* transmit buffer status */ 84 #define SC01STR_RXF 0x0040 /* receive status */ 85 #define SC01STR_TXF 0x0080 /* transmit status */ 86 #define SC01STR_STF 0x0100 /* I2C start sequence found */ 87 #define SC01STR_SPF 0x0200 /* I2C stop sequence found */ 88 89 #define SC0RXIRQ 20 /* timer 0 Receive IRQ */ 90 #define SC0TXIRQ 21 /* timer 0 Transmit IRQ */ 91 92 #define SC0RXICR GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */ 93 #define SC0TXICR GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */ 94 95 /* serial port 1 */ 96 #define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */ 97 #define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */ 98 #define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */ 99 #define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */ 100 #define SC1STR __SYSREG(0xd400201c, u16) /* status reg */ 101 102 #define SC1RXIRQ 22 /* timer 1 Receive IRQ */ 103 #define SC1TXIRQ 23 /* timer 1 Transmit IRQ */ 104 105 #define SC1RXICR GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */ 106 #define SC1TXICR GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */ 107 108 /* serial port 2 */ 109 #define SC2CTR __SYSREG(0xd4002020, u16) /* control reg */ 110 #ifdef CONFIG_AM33_2 111 #define SC2CTR_CK 0x0003 /* clock source select */ 112 #define SC2CTR_CK_TM10UFLOW 0x0000 /* - timer 10 underflow */ 113 #define SC2CTR_CK_TM2UFLOW 0x0001 /* - timer 2 underflow */ 114 #define SC2CTR_CK_EXTERN 0x0002 /* - external closk */ 115 #define SC2CTR_CK_TM3UFLOW 0x0003 /* - timer 3 underflow */ 116 #else /* CONFIG_AM33_2 */ 117 #define SC2CTR_CK 0x0007 /* clock source select */ 118 #define SC2CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow */ 119 #define SC2CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */ 120 #define SC2CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */ 121 #define SC2CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow */ 122 #define SC2CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 1 underflow */ 123 #define SC2CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow */ 124 #define SC2CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */ 125 #define SC2CTR_CK_EXTERN 0x0007 /* - external closk */ 126 #endif /* CONFIG_AM33_2 */ 127 #define SC2CTR_STB 0x0008 /* stop bit select */ 128 #define SC2CTR_STB_1BIT 0x0000 /* - 1 stop bit */ 129 #define SC2CTR_STB_2BIT 0x0008 /* - 2 stop bits */ 130 #define SC2CTR_PB 0x0070 /* parity bit select */ 131 #define SC2CTR_PB_NONE 0x0000 /* - no parity */ 132 #define SC2CTR_PB_FIXED0 0x0040 /* - fixed at 0 */ 133 #define SC2CTR_PB_FIXED1 0x0050 /* - fixed at 1 */ 134 #define SC2CTR_PB_EVEN 0x0060 /* - even parity */ 135 #define SC2CTR_PB_ODD 0x0070 /* - odd parity */ 136 #define SC2CTR_CLN 0x0080 /* character length */ 137 #define SC2CTR_CLN_7BIT 0x0000 /* - 7 bit chars */ 138 #define SC2CTR_CLN_8BIT 0x0080 /* - 8 bit chars */ 139 #define SC2CTR_TWE 0x0100 /* transmit wait enable (enable XCTS control) */ 140 #define SC2CTR_OD 0x0200 /* bit order select */ 141 #define SC2CTR_OD_LSBFIRST 0x0000 /* - LSB first */ 142 #define SC2CTR_OD_MSBFIRST 0x0200 /* - MSB first */ 143 #define SC2CTR_TWS 0x1000 /* transmit wait select */ 144 #define SC2CTR_TWS_XCTS_HIGH 0x0000 /* - interrupt TX when XCTS high */ 145 #define SC2CTR_TWS_XCTS_LOW 0x1000 /* - interrupt TX when XCTS low */ 146 #define SC2CTR_BKE 0x2000 /* break transmit enable */ 147 #define SC2CTR_RXE 0x4000 /* receive enable */ 148 #define SC2CTR_TXE 0x8000 /* transmit enable */ 149 150 #define SC2ICR __SYSREG(0xd4002024, u8) /* interrupt control reg */ 151 #define SC2ICR_TD 0x20 /* transmit DMA trigger cause */ 152 #define SC2ICR_TI 0x10 /* transmit interrupt cause */ 153 #define SC2ICR_RES 0x04 /* receive error select */ 154 #define SC2ICR_RI 0x01 /* receive interrupt cause */ 155 156 #define SC2TXB __SYSREG(0xd4002028, u8) /* transmit buffer reg */ 157 #define SC2RXB __SYSREG(0xd4002029, u8) /* receive buffer reg */ 158 159 #ifdef CONFIG_AM33_2 160 #define SC2STR __SYSREG(0xd400202c, u8) /* status reg */ 161 #else /* CONFIG_AM33_2 */ 162 #define SC2STR __SYSREG(0xd400202c, u16) /* status reg */ 163 #endif /* CONFIG_AM33_2 */ 164 #define SC2STR_OEF 0x0001 /* overrun error found */ 165 #define SC2STR_PEF 0x0002 /* parity error found */ 166 #define SC2STR_FEF 0x0004 /* framing error found */ 167 #define SC2STR_CTS 0x0008 /* XCTS input pin status (0 means high) */ 168 #define SC2STR_RBF 0x0010 /* receive buffer status */ 169 #define SC2STR_TBF 0x0020 /* transmit buffer status */ 170 #define SC2STR_RXF 0x0040 /* receive status */ 171 #define SC2STR_TXF 0x0080 /* transmit status */ 172 173 #ifdef CONFIG_AM33_2 174 #define SC2TIM __SYSREG(0xd400202d, u8) /* status reg */ 175 #endif 176 177 #ifdef CONFIG_AM33_2 178 #define SC2RXIRQ 24 /* serial 2 Receive IRQ */ 179 #define SC2TXIRQ 25 /* serial 2 Transmit IRQ */ 180 #else /* CONFIG_AM33_2 */ 181 #define SC2RXIRQ 68 /* serial 2 Receive IRQ */ 182 #define SC2TXIRQ 69 /* serial 2 Transmit IRQ */ 183 #endif /* CONFIG_AM33_2 */ 184 185 #define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */ 186 #define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */ 187 188 189 #endif /* __KERNEL__ */ 190 191 #endif /* _ASM_SERIAL_REGS_H */ 192