1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _SBSDIO_H 18 #define _SBSDIO_H 19 20 #define SBSDIO_NUM_FUNCTION 3 /* as of sdiod rev 0, supports 3 functions */ 21 22 /* function 1 miscellaneous registers */ 23 #define SBSDIO_SPROM_CS 0x10000 /* sprom command and status */ 24 #define SBSDIO_SPROM_INFO 0x10001 /* sprom info register */ 25 #define SBSDIO_SPROM_DATA_LOW 0x10002 /* sprom indirect access data byte 0 */ 26 #define SBSDIO_SPROM_DATA_HIGH 0x10003 /* sprom indirect access data byte 1 */ 27 #define SBSDIO_SPROM_ADDR_LOW 0x10004 /* sprom indirect access addr byte 0 */ 28 #define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* sprom indirect access addr byte 0 */ 29 #define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu (gpio) output */ 30 #define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu (gpio) enable */ 31 #define SBSDIO_WATERMARK 0x10008 /* rev < 7, watermark for sdio device */ 32 #define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */ 33 34 /* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */ 35 #define SBSDIO_FUNC1_SBADDRLOW 0x1000A /* SB Address Window Low (b15) */ 36 #define SBSDIO_FUNC1_SBADDRMID 0x1000B /* SB Address Window Mid (b23:b16) */ 37 #define SBSDIO_FUNC1_SBADDRHIGH 0x1000C /* SB Address Window High (b31:b24) */ 38 #define SBSDIO_FUNC1_FRAMECTRL 0x1000D /* Frame Control (frame term/abort) */ 39 #define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E /* ChipClockCSR (ALP/HT ctl/status) */ 40 #define SBSDIO_FUNC1_SDIOPULLUP 0x1000F /* SdioPullUp (on cmd, d0-d2) */ 41 #define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 /* Write Frame Byte Count Low */ 42 #define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A /* Write Frame Byte Count High */ 43 #define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B /* Read Frame Byte Count Low */ 44 #define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C /* Read Frame Byte Count High */ 45 46 #define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */ 47 #define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */ 48 49 /* SBSDIO_SPROM_CS */ 50 #define SBSDIO_SPROM_IDLE 0 51 #define SBSDIO_SPROM_WRITE 1 52 #define SBSDIO_SPROM_READ 2 53 #define SBSDIO_SPROM_WEN 4 54 #define SBSDIO_SPROM_WDS 7 55 #define SBSDIO_SPROM_DONE 8 56 57 /* SBSDIO_SPROM_INFO */ 58 #define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */ 59 #define SROM_BLANK 0x04 /* depreciated in corerev 6 */ 60 #define SROM_OTP 0x80 /* OTP present */ 61 62 /* SBSDIO_CHIP_CTRL */ 63 #define SBSDIO_CHIP_CTRL_XTAL 0x01 /* or'd with onchip xtal_pu, 64 * 1: power on oscillator 65 * (for 4318 only) 66 */ 67 /* SBSDIO_WATERMARK */ 68 #define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device 69 * to wait before sending data to host 70 */ 71 72 /* SBSDIO_DEVICE_CTL */ 73 #define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when 74 * receiving CMD53 75 */ 76 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is 77 * synchronous to the sdio clock 78 */ 79 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host 80 * except the chipActive (rev 8) 81 */ 82 #define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put 83 * external pads in tri-state; requires 84 * sdio bus power cycle to clear (rev 9) 85 */ 86 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */ 87 #define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */ 88 #define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */ 89 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */ 90 91 /* SBSDIO_FUNC1_CHIPCLKCSR */ 92 #define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */ 93 #define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */ 94 #define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */ 95 #define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */ 96 #define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */ 97 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */ 98 #define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */ 99 #define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */ 100 /* In rev8, actual avail bits followed original docs */ 101 #define SBSDIO_Rev8_HT_AVAIL 0x40 102 #define SBSDIO_Rev8_ALP_AVAIL 0x80 103 104 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 105 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 106 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 107 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 108 #define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \ 109 (alponly ? 1 : SBSDIO_HTAV(regval))) 110 111 /* SBSDIO_FUNC1_SDIOPULLUP */ 112 #define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */ 113 #define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */ 114 #define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */ 115 #define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */ 116 #define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */ 117 118 /* function 1 OCP space */ 119 #define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */ 120 #define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 121 #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 /* with b15, maps to 32-bit SB access */ 122 123 /* some duplication with sbsdpcmdev.h here */ 124 /* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */ 125 #define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */ 126 #define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */ 127 #define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */ 128 #define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */ 129 130 /* direct(mapped) cis space */ 131 #define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */ 132 #define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */ 133 #define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */ 134 135 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */ 136 137 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple, 138 * link bytes 139 */ 140 141 /* indirect cis access (in sprom) */ 142 #define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from 143 * 8th byte 144 */ 145 146 #define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one 147 * data command 148 */ 149 150 #define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */ 151 152 #endif /* _SBSDIO_H */ 153