1 /* linux/arch/arm/mach-exynos/include/mach/map.h 2 * 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com/ 5 * 6 * EXYNOS4 - Memory map definitions 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __ASM_ARCH_MAP_H 14 #define __ASM_ARCH_MAP_H __FILE__ 15 16 #include <plat/map-base.h> 17 18 /* 19 * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400. 20 * So need to define it, and here is to avoid redefinition warning. 21 */ 22 #define S3C_UART_OFFSET (0x10000) 23 24 #include <plat/map-s5p.h> 25 26 #define EXYNOS4_PA_SYSRAM0 0x02025000 27 #define EXYNOS4_PA_SYSRAM1 0x02020000 28 #define EXYNOS5_PA_SYSRAM 0x02020000 29 30 #define EXYNOS4_PA_FIMC0 0x11800000 31 #define EXYNOS4_PA_FIMC1 0x11810000 32 #define EXYNOS4_PA_FIMC2 0x11820000 33 #define EXYNOS4_PA_FIMC3 0x11830000 34 35 #define EXYNOS4_PA_JPEG 0x11840000 36 37 #define EXYNOS4_PA_G2D 0x12800000 38 39 #define EXYNOS4_PA_I2S0 0x03830000 40 #define EXYNOS4_PA_I2S1 0xE3100000 41 #define EXYNOS4_PA_I2S2 0xE2A00000 42 43 #define EXYNOS4_PA_PCM0 0x03840000 44 #define EXYNOS4_PA_PCM1 0x13980000 45 #define EXYNOS4_PA_PCM2 0x13990000 46 47 #define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) 48 49 #define EXYNOS4_PA_ONENAND 0x0C000000 50 #define EXYNOS4_PA_ONENAND_DMA 0x0C600000 51 52 #define EXYNOS_PA_CHIPID 0x10000000 53 54 #define EXYNOS4_PA_SYSCON 0x10010000 55 #define EXYNOS5_PA_SYSCON 0x10050100 56 57 #define EXYNOS4_PA_PMU 0x10020000 58 #define EXYNOS5_PA_PMU 0x10040000 59 60 #define EXYNOS4_PA_CMU 0x10030000 61 #define EXYNOS5_PA_CMU 0x10010000 62 63 #define EXYNOS4_PA_SYSTIMER 0x10050000 64 #define EXYNOS5_PA_SYSTIMER 0x101C0000 65 66 #define EXYNOS4_PA_WATCHDOG 0x10060000 67 #define EXYNOS5_PA_WATCHDOG 0x101D0000 68 69 #define EXYNOS4_PA_RTC 0x10070000 70 71 #define EXYNOS4_PA_KEYPAD 0x100A0000 72 73 #define EXYNOS4_PA_DMC0 0x10400000 74 #define EXYNOS4_PA_DMC1 0x10410000 75 76 #define EXYNOS4_PA_COMBINER 0x10440000 77 #define EXYNOS5_PA_COMBINER 0x10440000 78 79 #define EXYNOS4_PA_GIC_CPU 0x10480000 80 #define EXYNOS4_PA_GIC_DIST 0x10490000 81 #define EXYNOS5_PA_GIC_CPU 0x10480000 82 #define EXYNOS5_PA_GIC_DIST 0x10490000 83 84 #define EXYNOS4_PA_COREPERI 0x10500000 85 #define EXYNOS4_PA_TWD 0x10500600 86 #define EXYNOS4_PA_L2CC 0x10502000 87 88 #define EXYNOS4_PA_MDMA0 0x10810000 89 #define EXYNOS4_PA_MDMA1 0x12840000 90 #define EXYNOS4_PA_PDMA0 0x12680000 91 #define EXYNOS4_PA_PDMA1 0x12690000 92 #define EXYNOS5_PA_MDMA0 0x10800000 93 #define EXYNOS5_PA_MDMA1 0x11C10000 94 #define EXYNOS5_PA_PDMA0 0x121A0000 95 #define EXYNOS5_PA_PDMA1 0x121B0000 96 97 #define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000 98 #define EXYNOS4_PA_SYSMMU_SSS 0x10A50000 99 #define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000 100 #define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000 101 #define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000 102 #define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000 103 #define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000 104 #define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000 105 #define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000 106 #define EXYNOS4_PA_SYSMMU_PCIe 0x12620000 107 #define EXYNOS4_PA_SYSMMU_G2D 0x12A20000 108 #define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000 109 #define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000 110 #define EXYNOS4_PA_SYSMMU_TV 0x12E20000 111 #define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 112 #define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 113 #define EXYNOS4_PA_SPI0 0x13920000 114 #define EXYNOS4_PA_SPI1 0x13930000 115 #define EXYNOS4_PA_SPI2 0x13940000 116 117 #define EXYNOS4_PA_GPIO1 0x11400000 118 #define EXYNOS4_PA_GPIO2 0x11000000 119 #define EXYNOS4_PA_GPIO3 0x03860000 120 #define EXYNOS5_PA_GPIO1 0x11400000 121 #define EXYNOS5_PA_GPIO2 0x13400000 122 #define EXYNOS5_PA_GPIO3 0x10D10000 123 #define EXYNOS5_PA_GPIO4 0x03860000 124 125 #define EXYNOS4_PA_MIPI_CSIS0 0x11880000 126 #define EXYNOS4_PA_MIPI_CSIS1 0x11890000 127 128 #define EXYNOS4_PA_FIMD0 0x11C00000 129 130 #define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 131 #define EXYNOS4_PA_DWMCI 0x12550000 132 133 #define EXYNOS4_PA_SATA 0x12560000 134 #define EXYNOS4_PA_SATAPHY 0x125D0000 135 #define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000 136 137 #define EXYNOS4_PA_SROMC 0x12570000 138 #define EXYNOS5_PA_SROMC 0x12250000 139 140 #define EXYNOS4_PA_EHCI 0x12580000 141 #define EXYNOS4_PA_OHCI 0x12590000 142 #define EXYNOS4_PA_HSPHY 0x125B0000 143 #define EXYNOS4_PA_MFC 0x13400000 144 145 #define EXYNOS4_PA_UART 0x13800000 146 #define EXYNOS5_PA_UART 0x12C00000 147 148 #define EXYNOS4_PA_VP 0x12C00000 149 #define EXYNOS4_PA_MIXER 0x12C10000 150 #define EXYNOS4_PA_SDO 0x12C20000 151 #define EXYNOS4_PA_HDMI 0x12D00000 152 #define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000 153 154 #define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) 155 #define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000)) 156 157 #define EXYNOS4_PA_ADC 0x13910000 158 #define EXYNOS4_PA_ADC1 0x13911000 159 160 #define EXYNOS4_PA_AC97 0x139A0000 161 162 #define EXYNOS4_PA_SPDIF 0x139B0000 163 164 #define EXYNOS4_PA_TIMER 0x139D0000 165 #define EXYNOS5_PA_TIMER 0x12DD0000 166 167 #define EXYNOS4_PA_SDRAM 0x40000000 168 #define EXYNOS5_PA_SDRAM 0x40000000 169 170 /* Compatibiltiy Defines */ 171 172 #define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0) 173 #define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1) 174 #define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2) 175 #define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3) 176 #define S3C_PA_IIC EXYNOS4_PA_IIC(0) 177 #define S3C_PA_IIC1 EXYNOS4_PA_IIC(1) 178 #define S3C_PA_IIC2 EXYNOS4_PA_IIC(2) 179 #define S3C_PA_IIC3 EXYNOS4_PA_IIC(3) 180 #define S3C_PA_IIC4 EXYNOS4_PA_IIC(4) 181 #define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) 182 #define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) 183 #define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) 184 #define S3C_PA_RTC EXYNOS4_PA_RTC 185 #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 186 #define S3C_PA_SPI0 EXYNOS4_PA_SPI0 187 #define S3C_PA_SPI1 EXYNOS4_PA_SPI1 188 #define S3C_PA_SPI2 EXYNOS4_PA_SPI2 189 190 #define S5P_PA_EHCI EXYNOS4_PA_EHCI 191 #define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 192 #define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 193 #define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2 194 #define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 195 #define S5P_PA_JPEG EXYNOS4_PA_JPEG 196 #define S5P_PA_G2D EXYNOS4_PA_G2D 197 #define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0 198 #define S5P_PA_HDMI EXYNOS4_PA_HDMI 199 #define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY 200 #define S5P_PA_MFC EXYNOS4_PA_MFC 201 #define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 202 #define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 203 #define S5P_PA_MIXER EXYNOS4_PA_MIXER 204 #define S5P_PA_ONENAND EXYNOS4_PA_ONENAND 205 #define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA 206 #define S5P_PA_SDO EXYNOS4_PA_SDO 207 #define S5P_PA_SDRAM EXYNOS4_PA_SDRAM 208 #define S5P_PA_VP EXYNOS4_PA_VP 209 210 #define SAMSUNG_PA_ADC EXYNOS4_PA_ADC 211 #define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 212 #define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD 213 214 /* Compatibility UART */ 215 216 #define EXYNOS4_PA_UART0 0x13800000 217 #define EXYNOS4_PA_UART1 0x13810000 218 #define EXYNOS4_PA_UART2 0x13820000 219 #define EXYNOS4_PA_UART3 0x13830000 220 #define EXYNOS4_SZ_UART SZ_256 221 222 #define EXYNOS5_PA_UART0 0x12C00000 223 #define EXYNOS5_PA_UART1 0x12C10000 224 #define EXYNOS5_PA_UART2 0x12C20000 225 #define EXYNOS5_PA_UART3 0x12C30000 226 #define EXYNOS5_SZ_UART SZ_256 227 228 #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 229 230 #endif /* __ASM_ARCH_MAP_H */ 231