1 /* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
2  *
3  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4  *		http://www.samsung.com
5  *
6  * S5P64X0 - Clock register definitions
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11 */
12 
13 #ifndef __ASM_ARCH_REGS_CLOCK_H
14 #define __ASM_ARCH_REGS_CLOCK_H __FILE__
15 
16 #include <mach/map.h>
17 
18 #define S5P_CLKREG(x)			(S3C_VA_SYS + (x))
19 
20 #define S5P64X0_APLL_CON		S5P_CLKREG(0x0C)
21 #define S5P64X0_MPLL_CON		S5P_CLKREG(0x10)
22 #define S5P64X0_EPLL_CON		S5P_CLKREG(0x14)
23 #define S5P64X0_EPLL_CON_K		S5P_CLKREG(0x18)
24 
25 #define S5P64X0_CLK_SRC0		S5P_CLKREG(0x1C)
26 
27 #define S5P64X0_CLK_DIV0		S5P_CLKREG(0x20)
28 #define S5P64X0_CLK_DIV1		S5P_CLKREG(0x24)
29 #define S5P64X0_CLK_DIV2		S5P_CLKREG(0x28)
30 
31 #define S5P64X0_CLK_GATE_HCLK0		S5P_CLKREG(0x30)
32 #define S5P64X0_CLK_GATE_PCLK		S5P_CLKREG(0x34)
33 #define S5P64X0_CLK_GATE_SCLK0		S5P_CLKREG(0x38)
34 #define S5P64X0_CLK_GATE_MEM0		S5P_CLKREG(0x3C)
35 
36 #define S5P64X0_CLK_DIV3		S5P_CLKREG(0x40)
37 
38 #define S5P64X0_CLK_GATE_HCLK1		S5P_CLKREG(0x44)
39 #define S5P64X0_CLK_GATE_SCLK1		S5P_CLKREG(0x48)
40 
41 #define S5P6450_DPLL_CON		S5P_CLKREG(0x50)
42 #define S5P6450_DPLL_CON_K		S5P_CLKREG(0x54)
43 
44 #define S5P64X0_AHB_CON0		S5P_CLKREG(0x100)
45 #define S5P64X0_CLK_SRC1		S5P_CLKREG(0x10C)
46 
47 #define S5P64X0_SYS_ID			S5P_CLKREG(0x118)
48 #define S5P64X0_SYS_OTHERS		S5P_CLKREG(0x11C)
49 
50 #define S5P64X0_PWR_CFG			S5P_CLKREG(0x804)
51 #define S5P64X0_EINT_WAKEUP_MASK	S5P_CLKREG(0x808)
52 #define S5P64X0_SLEEP_CFG		S5P_CLKREG(0x818)
53 #define S5P64X0_PWR_STABLE		S5P_CLKREG(0x828)
54 
55 #define S5P64X0_OTHERS			S5P_CLKREG(0x900)
56 #define S5P64X0_WAKEUP_STAT		S5P_CLKREG(0x908)
57 
58 #define S5P64X0_INFORM0			S5P_CLKREG(0xA00)
59 
60 #define S5P64X0_CLKDIV0_HCLK_SHIFT	(8)
61 #define S5P64X0_CLKDIV0_HCLK_MASK	(0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
62 
63 /* HCLK GATE Registers */
64 #define S5P64X0_CLK_GATE_HCLK1_FIMGVG	(1 << 2)
65 #define S5P64X0_CLK_GATE_SCLK1_FIMGVG	(1 << 2)
66 
67 /* PCLK GATE Registers */
68 #define S5P64X0_CLK_GATE_PCLK_UART3	(1 << 4)
69 #define S5P64X0_CLK_GATE_PCLK_UART2	(1 << 3)
70 #define S5P64X0_CLK_GATE_PCLK_UART1	(1 << 2)
71 #define S5P64X0_CLK_GATE_PCLK_UART0	(1 << 1)
72 
73 #define S5P64X0_PWR_CFG_MMC1_DISABLE		(1 << 15)
74 #define S5P64X0_PWR_CFG_MMC0_DISABLE		(1 << 14)
75 #define S5P64X0_PWR_CFG_RTC_TICK_DISABLE	(1 << 11)
76 #define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE	(1 << 10)
77 #define S5P64X0_PWR_CFG_WFI_MASK		(3 << 5)
78 #define S5P64X0_PWR_CFG_WFI_SLEEP		(3 << 5)
79 
80 #define S5P64X0_SLEEP_CFG_OSC_EN	(1 << 0)
81 
82 #define S5P64X0_PWR_STABLE_PWR_CNT_VAL4	(4 << 0)
83 
84 #define S5P6450_OTHERS_DISABLE_INT	(1 << 31)
85 #define S5P64X0_OTHERS_RET_UART		(1 << 26)
86 #define S5P64X0_OTHERS_RET_MMC1		(1 << 25)
87 #define S5P64X0_OTHERS_RET_MMC0		(1 << 24)
88 #define S5P64X0_OTHERS_USB_SIG_MASK	(1 << 16)
89 
90 /* Compatibility defines */
91 
92 #define ARM_CLK_DIV			S5P64X0_CLK_DIV0
93 #define ARM_DIV_RATIO_SHIFT		0
94 #define ARM_DIV_MASK			(0xF << ARM_DIV_RATIO_SHIFT)
95 
96 #define S5P_EPLL_CON			S5P64X0_EPLL_CON
97 
98 #endif /* __ASM_ARCH_REGS_CLOCK_H */
99