1 /* arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2443 clock register definitions
12 */
13
14 #ifndef __ASM_ARM_REGS_S3C2443_CLOCK
15 #define __ASM_ARM_REGS_S3C2443_CLOCK
16
17 #define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
18
19 #define S3C2443_PLLCON_MDIVSHIFT 16
20 #define S3C2443_PLLCON_PDIVSHIFT 8
21 #define S3C2443_PLLCON_SDIVSHIFT 0
22 #define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
23 #define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1)
24 #define S3C2443_PLLCON_SDIVMASK (3)
25
26 #define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
27 #define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
28 #define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
29 #define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
30 #define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
31 #define S3C2443_HCLKCON S3C2443_CLKREG(0x30)
32 #define S3C2443_PCLKCON S3C2443_CLKREG(0x34)
33 #define S3C2443_SCLKCON S3C2443_CLKREG(0x38)
34 #define S3C2443_PWRMODE S3C2443_CLKREG(0x40)
35 #define S3C2443_SWRST S3C2443_CLKREG(0x44)
36 #define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50)
37 #define S3C2443_SYSID S3C2443_CLKREG(0x5C)
38 #define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
39 #define S3C2443_RSTCON S3C2443_CLKREG(0x64)
40
41 #define S3C2443_SWRST_RESET (0x533c2443)
42
43 #define S3C2443_PLLCON_OFF (1<<24)
44
45 #define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
46 #define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7)
47 #define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7)
48 #define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7)
49 #define S3C2443_CLKSRC_EPLLREF_MASK (3<<7)
50
51 #define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
52
53 #define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
54 #define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
55
56 #define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0)
57
58 #define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
59 #define S3C2443_CLKDIV0_EXTDIV_SHIFT (6)
60
61 #define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
62 #define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
63
64 #define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
65 #define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
66 #define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
67 #define S3C2443_CLKDIV0_ARMDIV_2 (8<<9)
68 #define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
69 #define S3C2443_CLKDIV0_ARMDIV_4 (9<<9)
70 #define S3C2443_CLKDIV0_ARMDIV_6 (10<<9)
71 #define S3C2443_CLKDIV0_ARMDIV_8 (11<<9)
72 #define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
73 #define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
74
75 /* S3C2443_CLKDIV1 removed, only used in clock.c code */
76
77 #define S3C2443_CLKCON_NAND
78
79 #define S3C2443_HCLKCON_DMA0 (1<<0)
80 #define S3C2443_HCLKCON_DMA1 (1<<1)
81 #define S3C2443_HCLKCON_DMA2 (1<<2)
82 #define S3C2443_HCLKCON_DMA3 (1<<3)
83 #define S3C2443_HCLKCON_DMA4 (1<<4)
84 #define S3C2443_HCLKCON_DMA5 (1<<5)
85 #define S3C2443_HCLKCON_CAMIF (1<<8)
86 #define S3C2443_HCLKCON_LCDC (1<<9)
87 #define S3C2443_HCLKCON_USBH (1<<11)
88 #define S3C2443_HCLKCON_USBD (1<<12)
89 #define S3C2416_HCLKCON_HSMMC0 (1<<15)
90 #define S3C2443_HCLKCON_HSMMC (1<<16)
91 #define S3C2443_HCLKCON_CFC (1<<17)
92 #define S3C2443_HCLKCON_SSMC (1<<18)
93 #define S3C2443_HCLKCON_DRAMC (1<<19)
94
95 #define S3C2443_PCLKCON_UART0 (1<<0)
96 #define S3C2443_PCLKCON_UART1 (1<<1)
97 #define S3C2443_PCLKCON_UART2 (1<<2)
98 #define S3C2443_PCLKCON_UART3 (1<<3)
99 #define S3C2443_PCLKCON_IIC (1<<4)
100 #define S3C2443_PCLKCON_SDI (1<<5)
101 #define S3C2443_PCLKCON_ADC (1<<7)
102 #define S3C2443_PCLKCON_AC97 (1<<8)
103 #define S3C2443_PCLKCON_IIS (1<<9)
104 #define S3C2443_PCLKCON_PWMT (1<<10)
105 #define S3C2443_PCLKCON_WDT (1<<11)
106 #define S3C2443_PCLKCON_RTC (1<<12)
107 #define S3C2443_PCLKCON_GPIO (1<<13)
108 #define S3C2443_PCLKCON_SPI0 (1<<14)
109 #define S3C2443_PCLKCON_SPI1 (1<<15)
110
111 #define S3C2443_SCLKCON_DDRCLK (1<<16)
112 #define S3C2443_SCLKCON_SSMCCLK (1<<15)
113 #define S3C2443_SCLKCON_HSSPICLK (1<<14)
114 #define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13)
115 #define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12)
116 #define S3C2443_SCLKCON_CAMCLK (1<<11)
117 #define S3C2443_SCLKCON_DISPCLK (1<<10)
118 #define S3C2443_SCLKCON_I2SCLK (1<<9)
119 #define S3C2443_SCLKCON_UARTCLK (1<<8)
120 #define S3C2443_SCLKCON_USBHOST (1<<1)
121
122 #define S3C2443_PWRCFG_SLEEP (1<<15)
123
124 #include <asm/div64.h>
125
126 static inline unsigned int
s3c2443_get_mpll(unsigned int pllval,unsigned int baseclk)127 s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
128 {
129 unsigned int mdiv, pdiv, sdiv;
130 uint64_t fvco;
131
132 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
133 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
134 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
135
136 mdiv &= S3C2443_PLLCON_MDIVMASK;
137 pdiv &= S3C2443_PLLCON_PDIVMASK;
138 sdiv &= S3C2443_PLLCON_SDIVMASK;
139
140 fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
141 do_div(fvco, pdiv << sdiv);
142
143 return (unsigned int)fvco;
144 }
145
146 static inline unsigned int
s3c2443_get_epll(unsigned int pllval,unsigned int baseclk)147 s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
148 {
149 unsigned int mdiv, pdiv, sdiv;
150 uint64_t fvco;
151
152 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
153 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
154 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
155
156 mdiv &= S3C2443_PLLCON_MDIVMASK;
157 pdiv &= S3C2443_PLLCON_PDIVMASK;
158 sdiv &= S3C2443_PLLCON_SDIVMASK;
159
160 fvco = (uint64_t)baseclk * (mdiv + 8);
161 do_div(fvco, (pdiv + 2) << sdiv);
162
163 return (unsigned int)fvco;
164 }
165
166 #endif /* __ASM_ARM_REGS_S3C2443_CLOCK */
167
168