1 /* arch/arm/plat-samsung/include/plat/regs-spi.h 2 * 3 * Copyright (c) 2004 Fetron GmbH 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * S3C2410 SPI register definition 10 */ 11 12 #ifndef __ASM_ARCH_REGS_SPI_H 13 #define __ASM_ARCH_REGS_SPI_H 14 15 #define S3C2410_SPI1 (0x20) 16 #define S3C2412_SPI1 (0x100) 17 18 #define S3C2410_SPCON (0x00) 19 20 #define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */ 21 #define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */ 22 #define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */ 23 #define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */ 24 #define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */ 25 #define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */ 26 #define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */ 27 28 #define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */ 29 #define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */ 30 31 #define S3C2410_SPSTA (0x04) 32 33 #define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */ 34 #define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */ 35 #define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */ 36 #define S3C2412_SPSTA_READY_ORG (1 << 3) 37 38 #define S3C2410_SPPIN (0x08) 39 40 #define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */ 41 #define S3C2410_SPPIN_RESERVED (1 << 1) 42 #define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */ 43 44 #define S3C2410_SPPRE (0x0C) 45 #define S3C2410_SPTDAT (0x10) 46 #define S3C2410_SPRDAT (0x14) 47 48 #endif /* __ASM_ARCH_REGS_SPI_H */ 49