1 /* arch/arm/mach-s3c2410/include/mach/dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #ifndef __ASM_ARCH_DMA_H
14 #define __ASM_ARCH_DMA_H __FILE__
15
16 #include <plat/dma.h>
17 #include <linux/sysdev.h>
18
19 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
20
21 /* We use `virtual` dma channels to hide the fact we have only a limited
22 * number of DMA channels, and not of all of them (dependent on the device)
23 * can be attached to any DMA source. We therefore let the DMA core handle
24 * the allocation of hardware channels to clients.
25 */
26
27 enum dma_ch {
28 DMACH_XD0,
29 DMACH_XD1,
30 DMACH_SDI,
31 DMACH_SPI0,
32 DMACH_SPI1,
33 DMACH_UART0,
34 DMACH_UART1,
35 DMACH_UART2,
36 DMACH_TIMER,
37 DMACH_I2S_IN,
38 DMACH_I2S_OUT,
39 DMACH_PCM_IN,
40 DMACH_PCM_OUT,
41 DMACH_MIC_IN,
42 DMACH_USB_EP1,
43 DMACH_USB_EP2,
44 DMACH_USB_EP3,
45 DMACH_USB_EP4,
46 DMACH_UART0_SRC2, /* s3c2412 second uart sources */
47 DMACH_UART1_SRC2,
48 DMACH_UART2_SRC2,
49 DMACH_UART3, /* s3c2443 has extra uart */
50 DMACH_UART3_SRC2,
51 DMACH_MAX, /* the end entry */
52 };
53
54 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
55
56 /* we have 4 dma channels */
57 #if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
58 #define S3C_DMA_CHANNELS (4)
59 #else
60 #define S3C_DMA_CHANNELS (6)
61 #endif
62
63 /* types */
64
65 enum s3c2410_dma_state {
66 S3C2410_DMA_IDLE,
67 S3C2410_DMA_RUNNING,
68 S3C2410_DMA_PAUSED
69 };
70
71 /* enum s3c2410_dma_loadst
72 *
73 * This represents the state of the DMA engine, wrt to the loaded / running
74 * transfers. Since we don't have any way of knowing exactly the state of
75 * the DMA transfers, we need to know the state to make decisions on wether
76 * we can
77 *
78 * S3C2410_DMA_NONE
79 *
80 * There are no buffers loaded (the channel should be inactive)
81 *
82 * S3C2410_DMA_1LOADED
83 *
84 * There is one buffer loaded, however it has not been confirmed to be
85 * loaded by the DMA engine. This may be because the channel is not
86 * yet running, or the DMA driver decided that it was too costly to
87 * sit and wait for it to happen.
88 *
89 * S3C2410_DMA_1RUNNING
90 *
91 * The buffer has been confirmed running, and not finisged
92 *
93 * S3C2410_DMA_1LOADED_1RUNNING
94 *
95 * There is a buffer waiting to be loaded by the DMA engine, and one
96 * currently running.
97 */
98
99 enum s3c2410_dma_loadst {
100 S3C2410_DMALOAD_NONE,
101 S3C2410_DMALOAD_1LOADED,
102 S3C2410_DMALOAD_1RUNNING,
103 S3C2410_DMALOAD_1LOADED_1RUNNING,
104 };
105
106
107 /* flags */
108
109 #define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
110 * waiting for reloads */
111 #define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
112
113 #define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
114
115 /* dma buffer */
116
117 struct s3c2410_dma_buf;
118
119 /* s3c2410_dma_buf
120 *
121 * internally used buffer structure to describe a queued or running
122 * buffer.
123 */
124
125 struct s3c2410_dma_buf {
126 struct s3c2410_dma_buf *next;
127 int magic; /* magic */
128 int size; /* buffer size in bytes */
129 dma_addr_t data; /* start of DMA data */
130 dma_addr_t ptr; /* where the DMA got to [1] */
131 void *id; /* client's id */
132 };
133
134 /* [1] is this updated for both recv/send modes? */
135
136 struct s3c2410_dma_stats {
137 unsigned long loads;
138 unsigned long timeout_longest;
139 unsigned long timeout_shortest;
140 unsigned long timeout_avg;
141 unsigned long timeout_failed;
142 };
143
144 struct s3c2410_dma_map;
145
146 /* struct s3c2410_dma_chan
147 *
148 * full state information for each DMA channel
149 */
150
151 struct s3c2410_dma_chan {
152 /* channel state flags and information */
153 unsigned char number; /* number of this dma channel */
154 unsigned char in_use; /* channel allocated */
155 unsigned char irq_claimed; /* irq claimed for channel */
156 unsigned char irq_enabled; /* irq enabled for channel */
157 unsigned char xfer_unit; /* size of an transfer */
158
159 /* channel state */
160
161 enum s3c2410_dma_state state;
162 enum s3c2410_dma_loadst load_state;
163 struct s3c2410_dma_client *client;
164
165 /* channel configuration */
166 enum s3c2410_dmasrc source;
167 enum dma_ch req_ch;
168 unsigned long dev_addr;
169 unsigned long load_timeout;
170 unsigned int flags; /* channel flags */
171
172 struct s3c24xx_dma_map *map; /* channel hw maps */
173
174 /* channel's hardware position and configuration */
175 void __iomem *regs; /* channels registers */
176 void __iomem *addr_reg; /* data address register */
177 unsigned int irq; /* channel irq */
178 unsigned long dcon; /* default value of DCON */
179
180 /* driver handles */
181 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
182 s3c2410_dma_opfn_t op_fn; /* channel op callback */
183
184 /* stats gathering */
185 struct s3c2410_dma_stats *stats;
186 struct s3c2410_dma_stats stats_store;
187
188 /* buffer list and information */
189 struct s3c2410_dma_buf *curr; /* current dma buffer */
190 struct s3c2410_dma_buf *next; /* next buffer to load */
191 struct s3c2410_dma_buf *end; /* end of queue */
192
193 /* system device */
194 struct sys_device dev;
195 };
196
197 typedef unsigned long dma_device_t;
198
s3c_dma_has_circular(void)199 static inline bool s3c_dma_has_circular(void)
200 {
201 return false;
202 }
203
204 #endif /* __ASM_ARCH_DMA_H */
205