1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 /*
32 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
33 */
34
35 #ifndef _AU1000_H_
36 #define _AU1000_H_
37
38 #ifndef _LANGUAGE_ASSEMBLY
39
40 #include <linux/delay.h>
41 #include <asm/io.h>
42
43 /* cpu pipeline flush */
au_sync(void)44 void static inline au_sync(void)
45 {
46 __asm__ volatile ("sync");
47 }
48
au_sync_udelay(int us)49 void static inline au_sync_udelay(int us)
50 {
51 __asm__ volatile ("sync");
52 udelay(us);
53 }
54
au_sync_delay(int ms)55 void static inline au_sync_delay(int ms)
56 {
57 __asm__ volatile ("sync");
58 mdelay(ms);
59 }
60
au_writeb(u8 val,int reg)61 void static inline au_writeb(u8 val, int reg)
62 {
63 *(volatile u8 *)(reg) = val;
64 }
65
au_writew(u16 val,int reg)66 void static inline au_writew(u16 val, int reg)
67 {
68 *(volatile u16 *)(reg) = val;
69 }
70
au_writel(u32 val,int reg)71 void static inline au_writel(u32 val, int reg)
72 {
73 *(volatile u32 *)(reg) = val;
74 }
75
au_readb(unsigned long port)76 static inline u8 au_readb(unsigned long port)
77 {
78 return (*(volatile u8 *)port);
79 }
80
au_readw(unsigned long port)81 static inline u16 au_readw(unsigned long port)
82 {
83 return (*(volatile u16 *)port);
84 }
85
au_readl(unsigned long port)86 static inline u32 au_readl(unsigned long port)
87 {
88 return (*(volatile u32 *)port);
89 }
90
91 /* These next three functions should be a generic part of the MIPS
92 * kernel (with the 'au_' removed from the name) and selected for
93 * processors that support the instructions.
94 * Taken from PPC tree. -- Dan
95 */
96 /* Return the bit position of the most significant 1 bit in a word */
__ilog2(unsigned int x)97 static __inline__ int __ilog2(unsigned int x)
98 {
99 int lz;
100
101 asm volatile (
102 ".set\tnoreorder\n\t"
103 ".set\tnoat\n\t"
104 ".set\tmips32\n\t"
105 "clz\t%0,%1\n\t"
106 ".set\tmips0\n\t"
107 ".set\tat\n\t"
108 ".set\treorder"
109 : "=r" (lz)
110 : "r" (x));
111
112 return 31 - lz;
113 }
114
au_ffz(unsigned int x)115 static __inline__ int au_ffz(unsigned int x)
116 {
117 if ((x = ~x) == 0)
118 return 32;
119 return __ilog2(x & -x);
120 }
121
122 /*
123 * ffs: find first bit set. This is defined the same way as
124 * the libc and compiler builtin ffs routines, therefore
125 * differs in spirit from the above ffz (man ffs).
126 */
au_ffs(int x)127 static __inline__ int au_ffs(int x)
128 {
129 return __ilog2(x & -x) + 1;
130 }
131
132 /* arch/mips/au1000/common/clocks.c */
133 extern void set_au1x00_speed(unsigned int new_freq);
134 extern unsigned int get_au1x00_speed(void);
135 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
136 extern unsigned long get_au1x00_uart_baud_base(void);
137 extern void set_au1x00_lcd_clock(void);
138 extern unsigned int get_au1x00_lcd_clock(void);
139
140 /*
141 * Every board describes its IRQ mapping with this table.
142 */
143 typedef struct au1xxx_irqmap {
144 int im_irq;
145 int im_type;
146 int im_request;
147 } au1xxx_irq_map_t;
148
149 /*
150 * init_IRQ looks for a table with this name.
151 */
152 extern au1xxx_irq_map_t au1xxx_irq_map[];
153
154 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
155
156 #ifdef CONFIG_PM
157 /* no CP0 timer irq */
158 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
159 #else
160 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
161 #endif
162
163 /* SDRAM Controller */
164 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
165 #define MEM_SDMODE0 0xB4000000
166 #define MEM_SDMODE1 0xB4000004
167 #define MEM_SDMODE2 0xB4000008
168
169 #define MEM_SDADDR0 0xB400000C
170 #define MEM_SDADDR1 0xB4000010
171 #define MEM_SDADDR2 0xB4000014
172
173 #define MEM_SDREFCFG 0xB4000018
174 #define MEM_SDPRECMD 0xB400001C
175 #define MEM_SDAUTOREF 0xB4000020
176
177 #define MEM_SDWRMD0 0xB4000024
178 #define MEM_SDWRMD1 0xB4000028
179 #define MEM_SDWRMD2 0xB400002C
180
181 #define MEM_SDSLEEP 0xB4000030
182 #define MEM_SDSMCKE 0xB4000034
183 #endif
184
185 /* Static Bus Controller */
186 #define MEM_STCFG0 0xB4001000
187 #define MEM_STTIME0 0xB4001004
188 #define MEM_STADDR0 0xB4001008
189
190 #define MEM_STCFG1 0xB4001010
191 #define MEM_STTIME1 0xB4001014
192 #define MEM_STADDR1 0xB4001018
193
194 #define MEM_STCFG2 0xB4001020
195 #define MEM_STTIME2 0xB4001024
196 #define MEM_STADDR2 0xB4001028
197
198 #define MEM_STCFG3 0xB4001030
199 #define MEM_STTIME3 0xB4001034
200 #define MEM_STADDR3 0xB4001038
201
202 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
203 #define MEM_STNDCTL 0xB4001100
204 #define MEM_STSTAT 0xB4001104
205
206 #define MEM_STNAND_CMD (0x0)
207 #define MEM_STNAND_ADDR (0x4)
208 #define MEM_STNAND_DATA (0x20)
209 #endif
210
211 /* Interrupt Controller 0 */
212 #define IC0_CFG0RD 0xB0400040
213 #define IC0_CFG0SET 0xB0400040
214 #define IC0_CFG0CLR 0xB0400044
215
216 #define IC0_CFG1RD 0xB0400048
217 #define IC0_CFG1SET 0xB0400048
218 #define IC0_CFG1CLR 0xB040004C
219
220 #define IC0_CFG2RD 0xB0400050
221 #define IC0_CFG2SET 0xB0400050
222 #define IC0_CFG2CLR 0xB0400054
223
224 #define IC0_REQ0INT 0xB0400054
225 #define IC0_SRCRD 0xB0400058
226 #define IC0_SRCSET 0xB0400058
227 #define IC0_SRCCLR 0xB040005C
228 #define IC0_REQ1INT 0xB040005C
229
230 #define IC0_ASSIGNRD 0xB0400060
231 #define IC0_ASSIGNSET 0xB0400060
232 #define IC0_ASSIGNCLR 0xB0400064
233
234 #define IC0_WAKERD 0xB0400068
235 #define IC0_WAKESET 0xB0400068
236 #define IC0_WAKECLR 0xB040006C
237
238 #define IC0_MASKRD 0xB0400070
239 #define IC0_MASKSET 0xB0400070
240 #define IC0_MASKCLR 0xB0400074
241
242 #define IC0_RISINGRD 0xB0400078
243 #define IC0_RISINGCLR 0xB0400078
244 #define IC0_FALLINGRD 0xB040007C
245 #define IC0_FALLINGCLR 0xB040007C
246
247 #define IC0_TESTBIT 0xB0400080
248
249 /* Interrupt Controller 1 */
250 #define IC1_CFG0RD 0xB1800040
251 #define IC1_CFG0SET 0xB1800040
252 #define IC1_CFG0CLR 0xB1800044
253
254 #define IC1_CFG1RD 0xB1800048
255 #define IC1_CFG1SET 0xB1800048
256 #define IC1_CFG1CLR 0xB180004C
257
258 #define IC1_CFG2RD 0xB1800050
259 #define IC1_CFG2SET 0xB1800050
260 #define IC1_CFG2CLR 0xB1800054
261
262 #define IC1_REQ0INT 0xB1800054
263 #define IC1_SRCRD 0xB1800058
264 #define IC1_SRCSET 0xB1800058
265 #define IC1_SRCCLR 0xB180005C
266 #define IC1_REQ1INT 0xB180005C
267
268 #define IC1_ASSIGNRD 0xB1800060
269 #define IC1_ASSIGNSET 0xB1800060
270 #define IC1_ASSIGNCLR 0xB1800064
271
272 #define IC1_WAKERD 0xB1800068
273 #define IC1_WAKESET 0xB1800068
274 #define IC1_WAKECLR 0xB180006C
275
276 #define IC1_MASKRD 0xB1800070
277 #define IC1_MASKSET 0xB1800070
278 #define IC1_MASKCLR 0xB1800074
279
280 #define IC1_RISINGRD 0xB1800078
281 #define IC1_RISINGCLR 0xB1800078
282 #define IC1_FALLINGRD 0xB180007C
283 #define IC1_FALLINGCLR 0xB180007C
284
285 #define IC1_TESTBIT 0xB1800080
286
287 /* Interrupt Configuration Modes */
288 #define INTC_INT_DISABLED 0
289 #define INTC_INT_RISE_EDGE 0x1
290 #define INTC_INT_FALL_EDGE 0x2
291 #define INTC_INT_RISE_AND_FALL_EDGE 0x3
292 #define INTC_INT_HIGH_LEVEL 0x5
293 #define INTC_INT_LOW_LEVEL 0x6
294 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
295
296 /* Interrupt Numbers */
297 /* Au1000 */
298 #ifdef CONFIG_SOC_AU1000
299 #define AU1000_UART0_INT 0
300 #define AU1000_UART1_INT 1 /* au1000 */
301 #define AU1000_UART2_INT 2 /* au1000 */
302 #define AU1000_UART3_INT 3
303 #define AU1000_SSI0_INT 4 /* au1000 */
304 #define AU1000_SSI1_INT 5 /* au1000 */
305 #define AU1000_DMA_INT_BASE 6
306 #define AU1000_TOY_INT 14
307 #define AU1000_TOY_MATCH0_INT 15
308 #define AU1000_TOY_MATCH1_INT 16
309 #define AU1000_TOY_MATCH2_INT 17
310 #define AU1000_RTC_INT 18
311 #define AU1000_RTC_MATCH0_INT 19
312 #define AU1000_RTC_MATCH1_INT 20
313 #define AU1000_RTC_MATCH2_INT 21
314 #define AU1000_IRDA_TX_INT 22 /* au1000 */
315 #define AU1000_IRDA_RX_INT 23 /* au1000 */
316 #define AU1000_USB_DEV_REQ_INT 24
317 #define AU1000_USB_DEV_SUS_INT 25
318 #define AU1000_USB_HOST_INT 26
319 #define AU1000_ACSYNC_INT 27
320 #define AU1000_MAC0_DMA_INT 28
321 #define AU1000_MAC1_DMA_INT 29
322 #define AU1000_I2S_UO_INT 30 /* au1000 */
323 #define AU1000_AC97C_INT 31
324 #define AU1000_GPIO_0 32
325 #define AU1000_GPIO_1 33
326 #define AU1000_GPIO_2 34
327 #define AU1000_GPIO_3 35
328 #define AU1000_GPIO_4 36
329 #define AU1000_GPIO_5 37
330 #define AU1000_GPIO_6 38
331 #define AU1000_GPIO_7 39
332 #define AU1000_GPIO_8 40
333 #define AU1000_GPIO_9 41
334 #define AU1000_GPIO_10 42
335 #define AU1000_GPIO_11 43
336 #define AU1000_GPIO_12 44
337 #define AU1000_GPIO_13 45
338 #define AU1000_GPIO_14 46
339 #define AU1000_GPIO_15 47
340 #define AU1000_GPIO_16 48
341 #define AU1000_GPIO_17 49
342 #define AU1000_GPIO_18 50
343 #define AU1000_GPIO_19 51
344 #define AU1000_GPIO_20 52
345 #define AU1000_GPIO_21 53
346 #define AU1000_GPIO_22 54
347 #define AU1000_GPIO_23 55
348 #define AU1000_GPIO_24 56
349 #define AU1000_GPIO_25 57
350 #define AU1000_GPIO_26 58
351 #define AU1000_GPIO_27 59
352 #define AU1000_GPIO_28 60
353 #define AU1000_GPIO_29 61
354 #define AU1000_GPIO_30 62
355 #define AU1000_GPIO_31 63
356
357 #define UART0_ADDR 0xB1100000
358 #define UART1_ADDR 0xB1200000
359 #define UART2_ADDR 0xB1300000
360 #define UART3_ADDR 0xB1400000
361
362 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
363 #define USB_HOST_CONFIG 0xB017fffc
364
365 #define AU1000_ETH0_BASE 0xB0500000
366 #define AU1000_ETH1_BASE 0xB0510000
367 #define AU1000_MAC0_ENABLE 0xB0520000
368 #define AU1000_MAC1_ENABLE 0xB0520004
369 #define NUM_ETH_INTERFACES 2
370 #endif // CONFIG_SOC_AU1000
371
372 /* Au1500 */
373 #ifdef CONFIG_SOC_AU1500
374 #define AU1500_UART0_INT 0
375 #define AU1000_PCI_INTA 1 /* au1500 */
376 #define AU1000_PCI_INTB 2 /* au1500 */
377 #define AU1500_UART3_INT 3
378 #define AU1000_PCI_INTC 4 /* au1500 */
379 #define AU1000_PCI_INTD 5 /* au1500 */
380 #define AU1000_DMA_INT_BASE 6
381 #define AU1000_TOY_INT 14
382 #define AU1000_TOY_MATCH0_INT 15
383 #define AU1000_TOY_MATCH1_INT 16
384 #define AU1000_TOY_MATCH2_INT 17
385 #define AU1000_RTC_INT 18
386 #define AU1000_RTC_MATCH0_INT 19
387 #define AU1000_RTC_MATCH1_INT 20
388 #define AU1000_RTC_MATCH2_INT 21
389 #define AU1500_PCI_ERR_INT 22
390 #define AU1000_USB_DEV_REQ_INT 24
391 #define AU1000_USB_DEV_SUS_INT 25
392 #define AU1000_USB_HOST_INT 26
393 #define AU1000_ACSYNC_INT 27
394 #define AU1500_MAC0_DMA_INT 28
395 #define AU1500_MAC1_DMA_INT 29
396 #define AU1000_AC97C_INT 31
397 #define AU1000_GPIO_0 32
398 #define AU1000_GPIO_1 33
399 #define AU1000_GPIO_2 34
400 #define AU1000_GPIO_3 35
401 #define AU1000_GPIO_4 36
402 #define AU1000_GPIO_5 37
403 #define AU1000_GPIO_6 38
404 #define AU1000_GPIO_7 39
405 #define AU1000_GPIO_8 40
406 #define AU1000_GPIO_9 41
407 #define AU1000_GPIO_10 42
408 #define AU1000_GPIO_11 43
409 #define AU1000_GPIO_12 44
410 #define AU1000_GPIO_13 45
411 #define AU1000_GPIO_14 46
412 #define AU1000_GPIO_15 47
413 #define AU1500_GPIO_200 48
414 #define AU1500_GPIO_201 49
415 #define AU1500_GPIO_202 50
416 #define AU1500_GPIO_203 51
417 #define AU1500_GPIO_20 52
418 #define AU1500_GPIO_204 53
419 #define AU1500_GPIO_205 54
420 #define AU1500_GPIO_23 55
421 #define AU1500_GPIO_24 56
422 #define AU1500_GPIO_25 57
423 #define AU1500_GPIO_26 58
424 #define AU1500_GPIO_27 59
425 #define AU1500_GPIO_28 60
426 #define AU1500_GPIO_206 61
427 #define AU1500_GPIO_207 62
428 #define AU1500_GPIO_208_215 63
429
430 #define UART0_ADDR 0xB1100000
431 #define UART3_ADDR 0xB1400000
432
433 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
434 #define USB_HOST_CONFIG 0xB017fffc
435
436 #define AU1500_ETH0_BASE 0xB1500000
437 #define AU1500_ETH1_BASE 0xB1510000
438 #define AU1500_MAC0_ENABLE 0xB1520000
439 #define AU1500_MAC1_ENABLE 0xB1520004
440 #define NUM_ETH_INTERFACES 2
441 #endif // CONFIG_SOC_AU1500
442
443 /* Au1100 */
444 #ifdef CONFIG_SOC_AU1100
445 #define AU1100_UART0_INT 0
446 #define AU1100_UART1_INT 1
447 #define AU1100_SD_INT 2
448 #define AU1100_UART3_INT 3
449 #define AU1000_SSI0_INT 4
450 #define AU1000_SSI1_INT 5
451 #define AU1000_DMA_INT_BASE 6
452 #define AU1000_TOY_INT 14
453 #define AU1000_TOY_MATCH0_INT 15
454 #define AU1000_TOY_MATCH1_INT 16
455 #define AU1000_TOY_MATCH2_INT 17
456 #define AU1000_RTC_INT 18
457 #define AU1000_RTC_MATCH0_INT 19
458 #define AU1000_RTC_MATCH1_INT 20
459 #define AU1000_RTC_MATCH2_INT 21
460 #define AU1000_IRDA_TX_INT 22
461 #define AU1000_IRDA_RX_INT 23
462 #define AU1000_USB_DEV_REQ_INT 24
463 #define AU1000_USB_DEV_SUS_INT 25
464 #define AU1000_USB_HOST_INT 26
465 #define AU1000_ACSYNC_INT 27
466 #define AU1100_MAC0_DMA_INT 28
467 #define AU1100_GPIO_208_215 29
468 #define AU1100_LCD_INT 30
469 #define AU1000_AC97C_INT 31
470 #define AU1000_GPIO_0 32
471 #define AU1000_GPIO_1 33
472 #define AU1000_GPIO_2 34
473 #define AU1000_GPIO_3 35
474 #define AU1000_GPIO_4 36
475 #define AU1000_GPIO_5 37
476 #define AU1000_GPIO_6 38
477 #define AU1000_GPIO_7 39
478 #define AU1000_GPIO_8 40
479 #define AU1000_GPIO_9 41
480 #define AU1000_GPIO_10 42
481 #define AU1000_GPIO_11 43
482 #define AU1000_GPIO_12 44
483 #define AU1000_GPIO_13 45
484 #define AU1000_GPIO_14 46
485 #define AU1000_GPIO_15 47
486
487 #define UART0_ADDR 0xB1100000
488 #define UART1_ADDR 0xB1200000
489 #define UART3_ADDR 0xB1400000
490
491 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
492 #define USB_HOST_CONFIG 0xB017fffc
493
494 #define AU1100_ETH0_BASE 0xB0500000
495 #define AU1100_MAC0_ENABLE 0xB0520000
496 #define NUM_ETH_INTERFACES 1
497 #endif // CONFIG_SOC_AU1100
498
499 #ifdef CONFIG_SOC_AU1550
500 #define AU1550_UART0_INT 0
501 #define AU1550_PCI_INTA 1
502 #define AU1550_PCI_INTB 2
503 #define AU1550_DDMA_INT 3
504 #define AU1550_CRYPTO_INT 4
505 #define AU1550_PCI_INTC 5
506 #define AU1550_PCI_INTD 6
507 #define AU1550_PCI_RST_INT 7
508 #define AU1550_UART1_INT 8
509 #define AU1550_UART3_INT 9
510 #define AU1550_PSC0_INT 10
511 #define AU1550_PSC1_INT 11
512 #define AU1550_PSC2_INT 12
513 #define AU1550_PSC3_INT 13
514 #define AU1550_TOY_INT 14
515 #define AU1550_TOY_MATCH0_INT 15
516 #define AU1550_TOY_MATCH1_INT 16
517 #define AU1550_TOY_MATCH2_INT 17
518 #define AU1550_RTC_INT 18
519 #define AU1550_RTC_MATCH0_INT 19
520 #define AU1550_RTC_MATCH1_INT 20
521 #define AU1550_RTC_MATCH2_INT 21
522 #define AU1550_NAND_INT 23
523 #define AU1550_USB_DEV_REQ_INT 24
524 #define AU1550_USB_DEV_SUS_INT 25
525 #define AU1550_USB_HOST_INT 26
526 #define AU1000_USB_DEV_REQ_INT AU1550_USB_DEV_REQ_INT
527 #define AU1000_USB_DEV_SUS_INT AU1550_USB_DEV_SUS_INT
528 #define AU1000_USB_HOST_INT AU1550_USB_HOST_INT
529 #define AU1550_MAC0_DMA_INT 27
530 #define AU1550_MAC1_DMA_INT 28
531 #define AU1000_GPIO_0 32
532 #define AU1000_GPIO_1 33
533 #define AU1000_GPIO_2 34
534 #define AU1000_GPIO_3 35
535 #define AU1000_GPIO_4 36
536 #define AU1000_GPIO_5 37
537 #define AU1000_GPIO_6 38
538 #define AU1000_GPIO_7 39
539 #define AU1000_GPIO_8 40
540 #define AU1000_GPIO_9 41
541 #define AU1000_GPIO_10 42
542 #define AU1000_GPIO_11 43
543 #define AU1000_GPIO_12 44
544 #define AU1000_GPIO_13 45
545 #define AU1000_GPIO_14 46
546 #define AU1000_GPIO_15 47
547 #define AU1550_GPIO_200 48
548 #define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205
549 #define AU1500_GPIO_16 50
550 #define AU1500_GPIO_17 51
551 #define AU1500_GPIO_20 52
552 #define AU1500_GPIO_21 53
553 #define AU1500_GPIO_22 54
554 #define AU1500_GPIO_23 55
555 #define AU1500_GPIO_24 56
556 #define AU1500_GPIO_25 57
557 #define AU1500_GPIO_26 58
558 #define AU1500_GPIO_27 59
559 #define AU1500_GPIO_28 60
560 #define AU1500_GPIO_206 61
561 #define AU1500_GPIO_207 62
562 #define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218
563
564 #define UART0_ADDR 0xB1100000
565 #define UART1_ADDR 0xB1200000
566 #define UART3_ADDR 0xB1400000
567
568 #define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
569 #define USB_HOST_CONFIG 0xB4027ffc
570
571 #define AU1550_ETH0_BASE 0xB0500000
572 #define AU1550_ETH1_BASE 0xB0510000
573 #define AU1550_MAC0_ENABLE 0xB0520000
574 #define AU1550_MAC1_ENABLE 0xB0520004
575 #define NUM_ETH_INTERFACES 2
576 #endif // CONFIG_SOC_AU1550
577
578 #ifdef CONFIG_SOC_AU1200
579 #define AU1200_UART0_INT 0
580 #define AU1200_SWT_INT 1
581 #define AU1200_SD_INT 2
582 #define AU1200_DDMA_INT 3
583 #define AU1200_MAE_BE_INT 4
584 #define AU1200_GPIO_200 5
585 #define AU1200_GPIO_201 6
586 #define AU1200_GPIO_202 7
587 #define AU1200_UART1_INT 8
588 #define AU1200_MAE_FE_INT 9
589 #define AU1200_PSC0_INT 10
590 #define AU1200_PSC1_INT 11
591 #define AU1200_AES_INT 12
592 #define AU1200_CAMERA_INT 13
593 #define AU1200_TOY_INT 14
594 #define AU1200_TOY_MATCH0_INT 15
595 #define AU1200_TOY_MATCH1_INT 16
596 #define AU1200_TOY_MATCH2_INT 17
597 #define AU1200_RTC_INT 18
598 #define AU1200_RTC_MATCH0_INT 19
599 #define AU1200_RTC_MATCH1_INT 20
600 #define AU1200_RTC_MATCH2_INT 21
601 #define AU1200_NAND_INT 23
602 #define AU1200_GPIO_204 24
603 #define AU1200_GPIO_205 25
604 #define AU1200_GPIO_206 26
605 #define AU1200_GPIO_207 27
606 #define AU1200_GPIO_208_215 28 // Logical OR of 208:215
607 #define AU1200_USB_INT 29
608 #define AU1200_LCD_INT 30
609 #define AU1200_MAE_BOTH_INT 31
610 #define AU1000_GPIO_0 32
611 #define AU1000_GPIO_1 33
612 #define AU1000_GPIO_2 34
613 #define AU1000_GPIO_3 35
614 #define AU1000_GPIO_4 36
615 #define AU1000_GPIO_5 37
616 #define AU1000_GPIO_6 38
617 #define AU1000_GPIO_7 39
618 #define AU1000_GPIO_8 40
619 #define AU1000_GPIO_9 41
620 #define AU1000_GPIO_10 42
621 #define AU1000_GPIO_11 43
622 #define AU1000_GPIO_12 44
623 #define AU1000_GPIO_13 45
624 #define AU1000_GPIO_14 46
625 #define AU1000_GPIO_15 47
626 #define AU1000_GPIO_16 48
627 #define AU1000_GPIO_17 49
628 #define AU1000_GPIO_18 50
629 #define AU1000_GPIO_19 51
630 #define AU1000_GPIO_20 52
631 #define AU1000_GPIO_21 53
632 #define AU1000_GPIO_22 54
633 #define AU1000_GPIO_23 55
634 #define AU1000_GPIO_24 56
635 #define AU1000_GPIO_25 57
636 #define AU1000_GPIO_26 58
637 #define AU1000_GPIO_27 59
638 #define AU1000_GPIO_28 60
639 #define AU1000_GPIO_29 61
640 #define AU1000_GPIO_30 62
641 #define AU1000_GPIO_31 63
642
643 #define UART0_ADDR 0xB1100000
644 #define UART1_ADDR 0xB1200000
645
646 #define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
647 #define USB_HOST_CONFIG 0xB4027ffc
648
649 // these are here for prototyping on au1550 (do not exist on au1200)
650 #define AU1200_ETH0_BASE 0xB0500000
651 #define AU1200_ETH1_BASE 0xB0510000
652 #define AU1200_MAC0_ENABLE 0xB0520000
653 #define AU1200_MAC1_ENABLE 0xB0520004
654 #define NUM_ETH_INTERFACES 2
655 #endif // CONFIG_SOC_AU1200
656
657 #define AU1000_LAST_INTC0_INT 31
658 #define AU1000_MAX_INTR 63
659
660
661 /* Programmable Counters 0 and 1 */
662 #define SYS_BASE 0xB1900000
663 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
664 #define SYS_CNTRL_E1S (1<<23)
665 #define SYS_CNTRL_T1S (1<<20)
666 #define SYS_CNTRL_M21 (1<<19)
667 #define SYS_CNTRL_M11 (1<<18)
668 #define SYS_CNTRL_M01 (1<<17)
669 #define SYS_CNTRL_C1S (1<<16)
670 #define SYS_CNTRL_BP (1<<14)
671 #define SYS_CNTRL_EN1 (1<<13)
672 #define SYS_CNTRL_BT1 (1<<12)
673 #define SYS_CNTRL_EN0 (1<<11)
674 #define SYS_CNTRL_BT0 (1<<10)
675 #define SYS_CNTRL_E0 (1<<8)
676 #define SYS_CNTRL_E0S (1<<7)
677 #define SYS_CNTRL_32S (1<<5)
678 #define SYS_CNTRL_T0S (1<<4)
679 #define SYS_CNTRL_M20 (1<<3)
680 #define SYS_CNTRL_M10 (1<<2)
681 #define SYS_CNTRL_M00 (1<<1)
682 #define SYS_CNTRL_C0S (1<<0)
683
684 /* Programmable Counter 0 Registers */
685 #define SYS_TOYTRIM (SYS_BASE + 0)
686 #define SYS_TOYWRITE (SYS_BASE + 4)
687 #define SYS_TOYMATCH0 (SYS_BASE + 8)
688 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
689 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
690 #define SYS_TOYREAD (SYS_BASE + 0x40)
691
692 /* Programmable Counter 1 Registers */
693 #define SYS_RTCTRIM (SYS_BASE + 0x44)
694 #define SYS_RTCWRITE (SYS_BASE + 0x48)
695 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
696 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
697 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
698 #define SYS_RTCREAD (SYS_BASE + 0x58)
699
700 /* I2S Controller */
701 #define I2S_DATA 0xB1000000
702 #define I2S_DATA_MASK (0xffffff)
703 #define I2S_CONFIG 0xB1000004
704 #define I2S_CONFIG_XU (1<<25)
705 #define I2S_CONFIG_XO (1<<24)
706 #define I2S_CONFIG_RU (1<<23)
707 #define I2S_CONFIG_RO (1<<22)
708 #define I2S_CONFIG_TR (1<<21)
709 #define I2S_CONFIG_TE (1<<20)
710 #define I2S_CONFIG_TF (1<<19)
711 #define I2S_CONFIG_RR (1<<18)
712 #define I2S_CONFIG_RE (1<<17)
713 #define I2S_CONFIG_RF (1<<16)
714 #define I2S_CONFIG_PD (1<<11)
715 #define I2S_CONFIG_LB (1<<10)
716 #define I2S_CONFIG_IC (1<<9)
717 #define I2S_CONFIG_FM_BIT 7
718 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
719 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
720 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
721 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
722 #define I2S_CONFIG_TN (1<<6)
723 #define I2S_CONFIG_RN (1<<5)
724 #define I2S_CONFIG_SZ_BIT 0
725 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
726
727 #define I2S_CONTROL 0xB1000008
728 #define I2S_CONTROL_D (1<<1)
729 #define I2S_CONTROL_CE (1<<0)
730
731 /* USB Host Controller */
732 #define USB_OHCI_LEN 0x00100000
733
734 /* USB Device Controller */
735 #define USBD_EP0RD 0xB0200000
736 #define USBD_EP0WR 0xB0200004
737 #define USBD_EP2WR 0xB0200008
738 #define USBD_EP3WR 0xB020000C
739 #define USBD_EP4RD 0xB0200010
740 #define USBD_EP5RD 0xB0200014
741 #define USBD_INTEN 0xB0200018
742 #define USBD_INTSTAT 0xB020001C
743 #define USBDEV_INT_SOF (1<<12)
744 #define USBDEV_INT_HF_BIT 6
745 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
746 #define USBDEV_INT_CMPLT_BIT 0
747 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
748 #define USBD_CONFIG 0xB0200020
749 #define USBD_EP0CS 0xB0200024
750 #define USBD_EP2CS 0xB0200028
751 #define USBD_EP3CS 0xB020002C
752 #define USBD_EP4CS 0xB0200030
753 #define USBD_EP5CS 0xB0200034
754 #define USBDEV_CS_SU (1<<14)
755 #define USBDEV_CS_NAK (1<<13)
756 #define USBDEV_CS_ACK (1<<12)
757 #define USBDEV_CS_BUSY (1<<11)
758 #define USBDEV_CS_TSIZE_BIT 1
759 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
760 #define USBDEV_CS_STALL (1<<0)
761 #define USBD_EP0RDSTAT 0xB0200040
762 #define USBD_EP0WRSTAT 0xB0200044
763 #define USBD_EP2WRSTAT 0xB0200048
764 #define USBD_EP3WRSTAT 0xB020004C
765 #define USBD_EP4RDSTAT 0xB0200050
766 #define USBD_EP5RDSTAT 0xB0200054
767 #define USBDEV_FSTAT_FLUSH (1<<6)
768 #define USBDEV_FSTAT_UF (1<<5)
769 #define USBDEV_FSTAT_OF (1<<4)
770 #define USBDEV_FSTAT_FCNT_BIT 0
771 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
772 #define USBD_ENABLE 0xB0200058
773 #define USBDEV_ENABLE (1<<1)
774 #define USBDEV_CE (1<<0)
775
776 /* Ethernet Controllers */
777
778 /* 4 byte offsets from AU1000_ETH_BASE */
779 #define MAC_CONTROL 0x0
780 #define MAC_RX_ENABLE (1<<2)
781 #define MAC_TX_ENABLE (1<<3)
782 #define MAC_DEF_CHECK (1<<5)
783 #define MAC_SET_BL(X) (((X)&0x3)<<6)
784 #define MAC_AUTO_PAD (1<<8)
785 #define MAC_DISABLE_RETRY (1<<10)
786 #define MAC_DISABLE_BCAST (1<<11)
787 #define MAC_LATE_COL (1<<12)
788 #define MAC_HASH_MODE (1<<13)
789 #define MAC_HASH_ONLY (1<<15)
790 #define MAC_PASS_ALL (1<<16)
791 #define MAC_INVERSE_FILTER (1<<17)
792 #define MAC_PROMISCUOUS (1<<18)
793 #define MAC_PASS_ALL_MULTI (1<<19)
794 #define MAC_FULL_DUPLEX (1<<20)
795 #define MAC_NORMAL_MODE 0
796 #define MAC_INT_LOOPBACK (1<<21)
797 #define MAC_EXT_LOOPBACK (1<<22)
798 #define MAC_DISABLE_RX_OWN (1<<23)
799 #define MAC_BIG_ENDIAN (1<<30)
800 #define MAC_RX_ALL (1<<31)
801 #define MAC_ADDRESS_HIGH 0x4
802 #define MAC_ADDRESS_LOW 0x8
803 #define MAC_MCAST_HIGH 0xC
804 #define MAC_MCAST_LOW 0x10
805 #define MAC_MII_CNTRL 0x14
806 #define MAC_MII_BUSY (1<<0)
807 #define MAC_MII_READ 0
808 #define MAC_MII_WRITE (1<<1)
809 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
810 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
811 #define MAC_MII_DATA 0x18
812 #define MAC_FLOW_CNTRL 0x1C
813 #define MAC_FLOW_CNTRL_BUSY (1<<0)
814 #define MAC_FLOW_CNTRL_ENABLE (1<<1)
815 #define MAC_PASS_CONTROL (1<<2)
816 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
817 #define MAC_VLAN1_TAG 0x20
818 #define MAC_VLAN2_TAG 0x24
819
820 /* Ethernet Controller Enable */
821
822 #define MAC_EN_CLOCK_ENABLE (1<<0)
823 #define MAC_EN_RESET0 (1<<1)
824 #define MAC_EN_TOSS (0<<2)
825 #define MAC_EN_CACHEABLE (1<<3)
826 #define MAC_EN_RESET1 (1<<4)
827 #define MAC_EN_RESET2 (1<<5)
828 #define MAC_DMA_RESET (1<<6)
829
830 /* Ethernet Controller DMA Channels */
831
832 #define MAC0_TX_DMA_ADDR 0xB4004000
833 #define MAC1_TX_DMA_ADDR 0xB4004200
834 /* offsets from MAC_TX_RING_ADDR address */
835 #define MAC_TX_BUFF0_STATUS 0x0
836 #define TX_FRAME_ABORTED (1<<0)
837 #define TX_JAB_TIMEOUT (1<<1)
838 #define TX_NO_CARRIER (1<<2)
839 #define TX_LOSS_CARRIER (1<<3)
840 #define TX_EXC_DEF (1<<4)
841 #define TX_LATE_COLL_ABORT (1<<5)
842 #define TX_EXC_COLL (1<<6)
843 #define TX_UNDERRUN (1<<7)
844 #define TX_DEFERRED (1<<8)
845 #define TX_LATE_COLL (1<<9)
846 #define TX_COLL_CNT_MASK (0xF<<10)
847 #define TX_PKT_RETRY (1<<31)
848 #define MAC_TX_BUFF0_ADDR 0x4
849 #define TX_DMA_ENABLE (1<<0)
850 #define TX_T_DONE (1<<1)
851 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
852 #define MAC_TX_BUFF0_LEN 0x8
853 #define MAC_TX_BUFF1_STATUS 0x10
854 #define MAC_TX_BUFF1_ADDR 0x14
855 #define MAC_TX_BUFF1_LEN 0x18
856 #define MAC_TX_BUFF2_STATUS 0x20
857 #define MAC_TX_BUFF2_ADDR 0x24
858 #define MAC_TX_BUFF2_LEN 0x28
859 #define MAC_TX_BUFF3_STATUS 0x30
860 #define MAC_TX_BUFF3_ADDR 0x34
861 #define MAC_TX_BUFF3_LEN 0x38
862
863 #define MAC0_RX_DMA_ADDR 0xB4004100
864 #define MAC1_RX_DMA_ADDR 0xB4004300
865 /* offsets from MAC_RX_RING_ADDR */
866 #define MAC_RX_BUFF0_STATUS 0x0
867 #define RX_FRAME_LEN_MASK 0x3fff
868 #define RX_WDOG_TIMER (1<<14)
869 #define RX_RUNT (1<<15)
870 #define RX_OVERLEN (1<<16)
871 #define RX_COLL (1<<17)
872 #define RX_ETHER (1<<18)
873 #define RX_MII_ERROR (1<<19)
874 #define RX_DRIBBLING (1<<20)
875 #define RX_CRC_ERROR (1<<21)
876 #define RX_VLAN1 (1<<22)
877 #define RX_VLAN2 (1<<23)
878 #define RX_LEN_ERROR (1<<24)
879 #define RX_CNTRL_FRAME (1<<25)
880 #define RX_U_CNTRL_FRAME (1<<26)
881 #define RX_MCAST_FRAME (1<<27)
882 #define RX_BCAST_FRAME (1<<28)
883 #define RX_FILTER_FAIL (1<<29)
884 #define RX_PACKET_FILTER (1<<30)
885 #define RX_MISSED_FRAME (1<<31)
886
887 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
888 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
889 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
890 #define MAC_RX_BUFF0_ADDR 0x4
891 #define RX_DMA_ENABLE (1<<0)
892 #define RX_T_DONE (1<<1)
893 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
894 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
895 #define MAC_RX_BUFF1_STATUS 0x10
896 #define MAC_RX_BUFF1_ADDR 0x14
897 #define MAC_RX_BUFF2_STATUS 0x20
898 #define MAC_RX_BUFF2_ADDR 0x24
899 #define MAC_RX_BUFF3_STATUS 0x30
900 #define MAC_RX_BUFF3_ADDR 0x34
901
902
903 /* UARTS 0-3 */
904 #define UART_BASE UART0_ADDR
905 #define UART_DEBUG_BASE UART3_ADDR
906
907 #define UART_RX 0 /* Receive buffer */
908 #define UART_TX 4 /* Transmit buffer */
909 #define UART_IER 8 /* Interrupt Enable Register */
910 #define UART_IIR 0xC /* Interrupt ID Register */
911 #define UART_FCR 0x10 /* FIFO Control Register */
912 #define UART_LCR 0x14 /* Line Control Register */
913 #define UART_MCR 0x18 /* Modem Control Register */
914 #define UART_LSR 0x1C /* Line Status Register */
915 #define UART_MSR 0x20 /* Modem Status Register */
916 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
917 #define UART_MOD_CNTRL 0x100 /* Module Control */
918
919 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
920 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
921 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
922 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
923 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
924 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
925 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
926 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
927 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
928 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
929 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
930 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
931 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
932
933 /*
934 * These are the definitions for the Line Control Register
935 */
936 #define UART_LCR_SBC 0x40 /* Set break control */
937 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
938 #define UART_LCR_EPAR 0x10 /* Even parity select */
939 #define UART_LCR_PARITY 0x08 /* Parity Enable */
940 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
941 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
942 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
943 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
944 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
945
946 /*
947 * These are the definitions for the Line Status Register
948 */
949 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
950 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
951 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
952 #define UART_LSR_FE 0x08 /* Frame error indicator */
953 #define UART_LSR_PE 0x04 /* Parity error indicator */
954 #define UART_LSR_OE 0x02 /* Overrun error indicator */
955 #define UART_LSR_DR 0x01 /* Receiver data ready */
956
957 /*
958 * These are the definitions for the Interrupt Identification Register
959 */
960 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
961 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
962 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
963 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
964 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
965 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
966
967 /*
968 * These are the definitions for the Interrupt Enable Register
969 */
970 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
971 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
972 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
973 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
974
975 /*
976 * These are the definitions for the Modem Control Register
977 */
978 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
979 #define UART_MCR_OUT2 0x08 /* Out2 complement */
980 #define UART_MCR_OUT1 0x04 /* Out1 complement */
981 #define UART_MCR_RTS 0x02 /* RTS complement */
982 #define UART_MCR_DTR 0x01 /* DTR complement */
983
984 /*
985 * These are the definitions for the Modem Status Register
986 */
987 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
988 #define UART_MSR_RI 0x40 /* Ring Indicator */
989 #define UART_MSR_DSR 0x20 /* Data Set Ready */
990 #define UART_MSR_CTS 0x10 /* Clear to Send */
991 #define UART_MSR_DDCD 0x08 /* Delta DCD */
992 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
993 #define UART_MSR_DDSR 0x02 /* Delta DSR */
994 #define UART_MSR_DCTS 0x01 /* Delta CTS */
995 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
996
997
998
999 /* SSIO */
1000 #define SSI0_STATUS 0xB1600000
1001 #define SSI_STATUS_BF (1<<4)
1002 #define SSI_STATUS_OF (1<<3)
1003 #define SSI_STATUS_UF (1<<2)
1004 #define SSI_STATUS_D (1<<1)
1005 #define SSI_STATUS_B (1<<0)
1006 #define SSI0_INT 0xB1600004
1007 #define SSI_INT_OI (1<<3)
1008 #define SSI_INT_UI (1<<2)
1009 #define SSI_INT_DI (1<<1)
1010 #define SSI0_INT_ENABLE 0xB1600008
1011 #define SSI_INTE_OIE (1<<3)
1012 #define SSI_INTE_UIE (1<<2)
1013 #define SSI_INTE_DIE (1<<1)
1014 #define SSI0_CONFIG 0xB1600020
1015 #define SSI_CONFIG_AO (1<<24)
1016 #define SSI_CONFIG_DO (1<<23)
1017 #define SSI_CONFIG_ALEN_BIT 20
1018 #define SSI_CONFIG_ALEN_MASK (0x7<<20)
1019 #define SSI_CONFIG_DLEN_BIT 16
1020 #define SSI_CONFIG_DLEN_MASK (0x7<<16)
1021 #define SSI_CONFIG_DD (1<<11)
1022 #define SSI_CONFIG_AD (1<<10)
1023 #define SSI_CONFIG_BM_BIT 8
1024 #define SSI_CONFIG_BM_MASK (0x3<<8)
1025 #define SSI_CONFIG_CE (1<<7)
1026 #define SSI_CONFIG_DP (1<<6)
1027 #define SSI_CONFIG_DL (1<<5)
1028 #define SSI_CONFIG_EP (1<<4)
1029 #define SSI0_ADATA 0xB1600024
1030 #define SSI_AD_D (1<<24)
1031 #define SSI_AD_ADDR_BIT 16
1032 #define SSI_AD_ADDR_MASK (0xff<<16)
1033 #define SSI_AD_DATA_BIT 0
1034 #define SSI_AD_DATA_MASK (0xfff<<0)
1035 #define SSI0_CLKDIV 0xB1600028
1036 #define SSI0_CONTROL 0xB1600100
1037 #define SSI_CONTROL_CD (1<<1)
1038 #define SSI_CONTROL_E (1<<0)
1039
1040 /* SSI1 */
1041 #define SSI1_STATUS 0xB1680000
1042 #define SSI1_INT 0xB1680004
1043 #define SSI1_INT_ENABLE 0xB1680008
1044 #define SSI1_CONFIG 0xB1680020
1045 #define SSI1_ADATA 0xB1680024
1046 #define SSI1_CLKDIV 0xB1680028
1047 #define SSI1_ENABLE 0xB1680100
1048
1049 /*
1050 * Register content definitions
1051 */
1052 #define SSI_STATUS_BF (1<<4)
1053 #define SSI_STATUS_OF (1<<3)
1054 #define SSI_STATUS_UF (1<<2)
1055 #define SSI_STATUS_D (1<<1)
1056 #define SSI_STATUS_B (1<<0)
1057
1058 /* SSI_INT */
1059 #define SSI_INT_OI (1<<3)
1060 #define SSI_INT_UI (1<<2)
1061 #define SSI_INT_DI (1<<1)
1062
1063 /* SSI_INTEN */
1064 #define SSI_INTEN_OIE (1<<3)
1065 #define SSI_INTEN_UIE (1<<2)
1066 #define SSI_INTEN_DIE (1<<1)
1067
1068 #define SSI_CONFIG_AO (1<<24)
1069 #define SSI_CONFIG_DO (1<<23)
1070 #define SSI_CONFIG_ALEN (7<<20)
1071 #define SSI_CONFIG_DLEN (15<<16)
1072 #define SSI_CONFIG_DD (1<<11)
1073 #define SSI_CONFIG_AD (1<<10)
1074 #define SSI_CONFIG_BM (3<<8)
1075 #define SSI_CONFIG_CE (1<<7)
1076 #define SSI_CONFIG_DP (1<<6)
1077 #define SSI_CONFIG_DL (1<<5)
1078 #define SSI_CONFIG_EP (1<<4)
1079 #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
1080 #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
1081 #define SSI_CONFIG_BM_HI (0<<8)
1082 #define SSI_CONFIG_BM_LO (1<<8)
1083 #define SSI_CONFIG_BM_CY (2<<8)
1084
1085 #define SSI_ADATA_D (1<<24)
1086 #define SSI_ADATA_ADDR (0xFF<<16)
1087 #define SSI_ADATA_DATA (0x0FFF)
1088 #define SSI_ADATA_ADDR_N(N) (N<<16)
1089
1090 #define SSI_ENABLE_CD (1<<1)
1091 #define SSI_ENABLE_E (1<<0)
1092
1093
1094 /* IrDA Controller */
1095 #define IRDA_BASE 0xB0300000
1096 #define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
1097 #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
1098 #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
1099 #define IR_RING_SIZE (IRDA_BASE+0x0C)
1100 #define IR_RING_PROMPT (IRDA_BASE+0x10)
1101 #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
1102 #define IR_INT_CLEAR (IRDA_BASE+0x18)
1103 #define IR_CONFIG_1 (IRDA_BASE+0x20)
1104 #define IR_RX_INVERT_LED (1<<0)
1105 #define IR_TX_INVERT_LED (1<<1)
1106 #define IR_ST (1<<2)
1107 #define IR_SF (1<<3)
1108 #define IR_SIR (1<<4)
1109 #define IR_MIR (1<<5)
1110 #define IR_FIR (1<<6)
1111 #define IR_16CRC (1<<7)
1112 #define IR_TD (1<<8)
1113 #define IR_RX_ALL (1<<9)
1114 #define IR_DMA_ENABLE (1<<10)
1115 #define IR_RX_ENABLE (1<<11)
1116 #define IR_TX_ENABLE (1<<12)
1117 #define IR_LOOPBACK (1<<14)
1118 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1119 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1120 #define IR_SIR_FLAGS (IRDA_BASE+0x24)
1121 #define IR_ENABLE (IRDA_BASE+0x28)
1122 #define IR_RX_STATUS (1<<9)
1123 #define IR_TX_STATUS (1<<10)
1124 #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
1125 #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
1126 #define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
1127 #define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
1128 #define IR_CONFIG_2 (IRDA_BASE+0x3C)
1129 #define IR_MODE_INV (1<<0)
1130 #define IR_ONE_PIN (1<<1)
1131 #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
1132
1133 /* GPIO */
1134 #define SYS_PINFUNC 0xB190002C
1135 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */
1136 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
1137 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
1138 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
1139 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
1140 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
1141 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
1142 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
1143 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
1144 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
1145 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
1146 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
1147 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
1148 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
1149 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
1150 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
1151
1152 /* Au1100 Only */
1153 #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
1154 #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
1155 #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
1156 #define SYS_PF_EX0 (1<<9) /* gpio2/clock */
1157
1158 /* Au1550 Only. Redefines lots of pins */
1159 #define SYS_PF_PSC2_MASK (7 << 17)
1160 #define SYS_PF_PSC2_AC97 (0)
1161 #define SYS_PF_PSC2_SPI (0)
1162 #define SYS_PF_PSC2_I2S (1 << 17)
1163 #define SYS_PF_PSC2_SMBUS (3 << 17)
1164 #define SYS_PF_PSC2_GPIO (7 << 17)
1165 #define SYS_PF_PSC3_MASK (7 << 20)
1166 #define SYS_PF_PSC3_AC97 (0)
1167 #define SYS_PF_PSC3_SPI (0)
1168 #define SYS_PF_PSC3_I2S (1 << 20)
1169 #define SYS_PF_PSC3_SMBUS (3 << 20)
1170 #define SYS_PF_PSC3_GPIO (7 << 20)
1171 #define SYS_PF_PSC1_S1 (1 << 1)
1172 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1173
1174 #define SYS_TRIOUTRD 0xB1900100
1175 #define SYS_TRIOUTCLR 0xB1900100
1176 #define SYS_OUTPUTRD 0xB1900108
1177 #define SYS_OUTPUTSET 0xB1900108
1178 #define SYS_OUTPUTCLR 0xB190010C
1179 #define SYS_PINSTATERD 0xB1900110
1180 #define SYS_PININPUTEN 0xB1900110
1181
1182 /* GPIO2, Au1500, Au1550 only */
1183 #define GPIO2_BASE 0xB1700000
1184 #define GPIO2_DIR (GPIO2_BASE + 0)
1185 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1186 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1187 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1188 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1189
1190 /* Power Management */
1191 #define SYS_SCRATCH0 0xB1900018
1192 #define SYS_SCRATCH1 0xB190001C
1193 #define SYS_WAKEMSK 0xB1900034
1194 #define SYS_ENDIAN 0xB1900038
1195 #define SYS_POWERCTRL 0xB190003C
1196 #define SYS_WAKESRC 0xB190005C
1197 #define SYS_SLPPWR 0xB1900078
1198 #define SYS_SLEEP 0xB190007C
1199
1200 /* Clock Controller */
1201 #define SYS_FREQCTRL0 0xB1900020
1202 #define SYS_FC_FRDIV2_BIT 22
1203 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1204 #define SYS_FC_FE2 (1<<21)
1205 #define SYS_FC_FS2 (1<<20)
1206 #define SYS_FC_FRDIV1_BIT 12
1207 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1208 #define SYS_FC_FE1 (1<<11)
1209 #define SYS_FC_FS1 (1<<10)
1210 #define SYS_FC_FRDIV0_BIT 2
1211 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1212 #define SYS_FC_FE0 (1<<1)
1213 #define SYS_FC_FS0 (1<<0)
1214 #define SYS_FREQCTRL1 0xB1900024
1215 #define SYS_FC_FRDIV5_BIT 22
1216 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1217 #define SYS_FC_FE5 (1<<21)
1218 #define SYS_FC_FS5 (1<<20)
1219 #define SYS_FC_FRDIV4_BIT 12
1220 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1221 #define SYS_FC_FE4 (1<<11)
1222 #define SYS_FC_FS4 (1<<10)
1223 #define SYS_FC_FRDIV3_BIT 2
1224 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1225 #define SYS_FC_FE3 (1<<1)
1226 #define SYS_FC_FS3 (1<<0)
1227 #define SYS_CLKSRC 0xB1900028
1228 #define SYS_CS_ME1_BIT 27
1229 #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
1230 #define SYS_CS_DE1 (1<<26)
1231 #define SYS_CS_CE1 (1<<25)
1232 #define SYS_CS_ME0_BIT 22
1233 #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
1234 #define SYS_CS_DE0 (1<<21)
1235 #define SYS_CS_CE0 (1<<20)
1236 #define SYS_CS_MI2_BIT 17
1237 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
1238 #define SYS_CS_DI2 (1<<16)
1239 #define SYS_CS_CI2 (1<<15)
1240 #define SYS_CS_MUH_BIT 12
1241 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
1242 #define SYS_CS_DUH (1<<11)
1243 #define SYS_CS_CUH (1<<10)
1244 #define SYS_CS_MUD_BIT 7
1245 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
1246 #define SYS_CS_DUD (1<<6)
1247 #define SYS_CS_CUD (1<<5)
1248 #define SYS_CS_MIR_BIT 2
1249 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
1250 #define SYS_CS_DIR (1<<1)
1251 #define SYS_CS_CIR (1<<0)
1252
1253 #define SYS_CS_MUX_AUX 0x1
1254 #define SYS_CS_MUX_FQ0 0x2
1255 #define SYS_CS_MUX_FQ1 0x3
1256 #define SYS_CS_MUX_FQ2 0x4
1257 #define SYS_CS_MUX_FQ3 0x5
1258 #define SYS_CS_MUX_FQ4 0x6
1259 #define SYS_CS_MUX_FQ5 0x7
1260 #define SYS_CPUPLL 0xB1900060
1261 #define SYS_AUXPLL 0xB1900064
1262
1263 /* AC97 Controller */
1264 #define AC97C_CONFIG 0xB0000000
1265 #define AC97C_RECV_SLOTS_BIT 13
1266 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1267 #define AC97C_XMIT_SLOTS_BIT 3
1268 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1269 #define AC97C_SG (1<<2)
1270 #define AC97C_SYNC (1<<1)
1271 #define AC97C_RESET (1<<0)
1272 #define AC97C_STATUS 0xB0000004
1273 #define AC97C_XU (1<<11)
1274 #define AC97C_XO (1<<10)
1275 #define AC97C_RU (1<<9)
1276 #define AC97C_RO (1<<8)
1277 #define AC97C_READY (1<<7)
1278 #define AC97C_CP (1<<6)
1279 #define AC97C_TR (1<<5)
1280 #define AC97C_TE (1<<4)
1281 #define AC97C_TF (1<<3)
1282 #define AC97C_RR (1<<2)
1283 #define AC97C_RE (1<<1)
1284 #define AC97C_RF (1<<0)
1285 #define AC97C_DATA 0xB0000008
1286 #define AC97C_CMD 0xB000000C
1287 #define AC97C_WD_BIT 16
1288 #define AC97C_READ (1<<7)
1289 #define AC97C_INDEX_MASK 0x7f
1290 #define AC97C_CNTRL 0xB0000010
1291 #define AC97C_RS (1<<1)
1292 #define AC97C_CE (1<<0)
1293
1294
1295 /* Secure Digital (SD) Controller */
1296 #define SD0_XMIT_FIFO 0xB0600000
1297 #define SD0_RECV_FIFO 0xB0600004
1298 #define SD1_XMIT_FIFO 0xB0680000
1299 #define SD1_RECV_FIFO 0xB0680004
1300
1301
1302 #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1303 /* Au1500 PCI Controller */
1304 #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
1305 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1306 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1307 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
1308 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1309 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1310 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1311 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1312 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1313 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1314 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1315 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1316 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1317 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1318 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1319 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1320
1321 #define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr
1322
1323 /* All of our structures, like pci resource, have 32 bit members.
1324 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1325 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
1326 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1327 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
1328 * addresses. For PCI IO, it's simpler because we get to do the ioremap
1329 * ourselves and then adjust the device's resources.
1330 */
1331 #define Au1500_EXT_CFG 0x600000000
1332 #define Au1500_EXT_CFG_TYPE1 0x680000000
1333 #define Au1500_PCI_IO_START 0x500000000
1334 #define Au1500_PCI_IO_END 0x5000FFFFF
1335 #define Au1500_PCI_MEM_START 0x440000000
1336 #define Au1500_PCI_MEM_END 0x44FFFFFFF
1337
1338 #define PCI_IO_START (Au1500_PCI_IO_START + 0x300)
1339 #define PCI_IO_END (Au1500_PCI_IO_END)
1340 #define PCI_MEM_START (Au1500_PCI_MEM_START)
1341 #define PCI_MEM_END (Au1500_PCI_MEM_END)
1342 #define PCI_FIRST_DEVFN (0<<3)
1343 #define PCI_LAST_DEVFN (19<<3)
1344
1345 #define IOPORT_RESOURCE_START 0x00000000
1346 #define IOPORT_RESOURCE_END 0xffffffff
1347 #define IOMEM_RESOURCE_START 0x10000000
1348 #define IOMEM_RESOURCE_END 0xffffffff
1349
1350 /*
1351 * Borrowed from the PPC arch:
1352 * The following macro is used to lookup irqs in a standard table
1353 * format for those PPC systems that do not already have PCI
1354 * interrupts properly routed.
1355 */
1356 /* FIXME - double check this from asm-ppc/pci-bridge.h */
1357 #define PCI_IRQ_TABLE_LOOKUP \
1358 ({ long _ctl_ = -1; \
1359 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
1360 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
1361 _ctl_; })
1362
1363
1364 #else /* Au1000 and Au1100 */
1365
1366 /* don't allow any legacy ports probing */
1367 #define IOPORT_RESOURCE_START 0x10000000;
1368 #define IOPORT_RESOURCE_END 0xffffffff
1369 #define IOMEM_RESOURCE_START 0x10000000
1370 #define IOMEM_RESOURCE_END 0xffffffff
1371
1372 #ifdef CONFIG_MIPS_PB1000
1373 #define PCI_IO_START 0x10000000
1374 #define PCI_IO_END 0x1000ffff
1375 #define PCI_MEM_START 0x18000000
1376 #define PCI_MEM_END 0x18ffffff
1377 #define PCI_FIRST_DEVFN 0
1378 #define PCI_LAST_DEVFN 1
1379 #else
1380 /* no PCI bus controller */
1381 #define PCI_IO_START 0
1382 #define PCI_IO_END 0
1383 #define PCI_MEM_START 0
1384 #define PCI_MEM_END 0
1385 #define PCI_FIRST_DEVFN 0
1386 #define PCI_LAST_DEVFN 0
1387 #endif
1388
1389 #endif
1390
1391 /* Processor information base on prid.
1392 * Copied from PowerPC.
1393 */
1394 struct cpu_spec {
1395 /* CPU is matched via (PRID & prid_mask) == prid_value */
1396 unsigned int prid_mask;
1397 unsigned int prid_value;
1398
1399 char *cpu_name;
1400 unsigned char cpu_od; /* Set Config[OD] */
1401 unsigned char cpu_bclk; /* Enable BCLK switching */
1402 };
1403
1404 extern struct cpu_spec cpu_specs[];
1405 extern struct cpu_spec *cur_cpu_spec[];
1406 #endif
1407