1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/firmware.h>
11 #include <linux/iopoll.h>
12 #include <linux/workqueue.h>
13 #include <net/mac80211.h>
14
15 struct rtw89_dev;
16 struct rtw89_pci_info;
17
18 extern const struct ieee80211_ops rtw89_ops;
19
20 #define MASKBYTE0 0xff
21 #define MASKBYTE1 0xff00
22 #define MASKBYTE2 0xff0000
23 #define MASKBYTE3 0xff000000
24 #define MASKBYTE4 0xff00000000ULL
25 #define MASKHWORD 0xffff0000
26 #define MASKLWORD 0x0000ffff
27 #define MASKDWORD 0xffffffff
28 #define RFREG_MASK 0xfffff
29 #define INV_RF_DATA 0xffffffff
30
31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
32 #define CFO_TRACK_MAX_USER 64
33 #define MAX_RSSI 110
34 #define RSSI_FACTOR 1
35 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
36
37 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
38 #define RTW89_HTC_VARIANT_HE 3
39 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
40 #define RTW89_HTC_VARIANT_HE_CID_OM 1
41 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
42 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
43
44 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
45 enum htc_om_channel_width {
46 HTC_OM_CHANNEL_WIDTH_20 = 0,
47 HTC_OM_CHANNEL_WIDTH_40 = 1,
48 HTC_OM_CHANNEL_WIDTH_80 = 2,
49 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
50 };
51 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
52 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
53 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
54 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
55 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
56 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
57
58 enum rtw89_subband {
59 RTW89_CH_2G = 0,
60 RTW89_CH_5G_BAND_1 = 1,
61 /* RTW89_CH_5G_BAND_2 = 2, unused */
62 RTW89_CH_5G_BAND_3 = 3,
63 RTW89_CH_5G_BAND_4 = 4,
64
65 RTW89_CH_6G_BAND_IDX0, /* Low */
66 RTW89_CH_6G_BAND_IDX1, /* Low */
67 RTW89_CH_6G_BAND_IDX2, /* Mid */
68 RTW89_CH_6G_BAND_IDX3, /* Mid */
69 RTW89_CH_6G_BAND_IDX4, /* High */
70 RTW89_CH_6G_BAND_IDX5, /* High */
71 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
72 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
73
74 RTW89_SUBBAND_NR,
75 };
76
77 enum rtw89_gain_offset {
78 RTW89_GAIN_OFFSET_2G_CCK,
79 RTW89_GAIN_OFFSET_2G_OFDM,
80 RTW89_GAIN_OFFSET_5G_LOW,
81 RTW89_GAIN_OFFSET_5G_MID,
82 RTW89_GAIN_OFFSET_5G_HIGH,
83
84 RTW89_GAIN_OFFSET_NR,
85 };
86
87 enum rtw89_hci_type {
88 RTW89_HCI_TYPE_PCIE,
89 RTW89_HCI_TYPE_USB,
90 RTW89_HCI_TYPE_SDIO,
91 };
92
93 enum rtw89_core_chip_id {
94 RTL8852A,
95 RTL8852B,
96 RTL8852C,
97 };
98
99 enum rtw89_cv {
100 CHIP_CAV,
101 CHIP_CBV,
102 CHIP_CCV,
103 CHIP_CDV,
104 CHIP_CEV,
105 CHIP_CFV,
106 CHIP_CV_MAX,
107 CHIP_CV_INVALID = CHIP_CV_MAX,
108 };
109
110 enum rtw89_core_tx_type {
111 RTW89_CORE_TX_TYPE_DATA,
112 RTW89_CORE_TX_TYPE_MGMT,
113 RTW89_CORE_TX_TYPE_FWCMD,
114 };
115
116 enum rtw89_core_rx_type {
117 RTW89_CORE_RX_TYPE_WIFI = 0,
118 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
119 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
120 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
121 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
122 RTW89_CORE_RX_TYPE_SS2FW = 5,
123 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
124 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
125 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
126 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
127 RTW89_CORE_RX_TYPE_C2H = 10,
128 RTW89_CORE_RX_TYPE_CSI = 11,
129 RTW89_CORE_RX_TYPE_CQI = 12,
130 RTW89_CORE_RX_TYPE_H2C = 13,
131 RTW89_CORE_RX_TYPE_FWDL = 14,
132 };
133
134 enum rtw89_txq_flags {
135 RTW89_TXQ_F_AMPDU = 0,
136 RTW89_TXQ_F_BLOCK_BA = 1,
137 };
138
139 enum rtw89_net_type {
140 RTW89_NET_TYPE_NO_LINK = 0,
141 RTW89_NET_TYPE_AD_HOC = 1,
142 RTW89_NET_TYPE_INFRA = 2,
143 RTW89_NET_TYPE_AP_MODE = 3,
144 };
145
146 enum rtw89_wifi_role {
147 RTW89_WIFI_ROLE_NONE,
148 RTW89_WIFI_ROLE_STATION,
149 RTW89_WIFI_ROLE_AP,
150 RTW89_WIFI_ROLE_AP_VLAN,
151 RTW89_WIFI_ROLE_ADHOC,
152 RTW89_WIFI_ROLE_ADHOC_MASTER,
153 RTW89_WIFI_ROLE_MESH_POINT,
154 RTW89_WIFI_ROLE_MONITOR,
155 RTW89_WIFI_ROLE_P2P_DEVICE,
156 RTW89_WIFI_ROLE_P2P_CLIENT,
157 RTW89_WIFI_ROLE_P2P_GO,
158 RTW89_WIFI_ROLE_NAN,
159 RTW89_WIFI_ROLE_MLME_MAX
160 };
161
162 enum rtw89_upd_mode {
163 RTW89_ROLE_CREATE,
164 RTW89_ROLE_REMOVE,
165 RTW89_ROLE_TYPE_CHANGE,
166 RTW89_ROLE_INFO_CHANGE,
167 RTW89_ROLE_CON_DISCONN
168 };
169
170 enum rtw89_self_role {
171 RTW89_SELF_ROLE_CLIENT,
172 RTW89_SELF_ROLE_AP,
173 RTW89_SELF_ROLE_AP_CLIENT
174 };
175
176 enum rtw89_msk_sO_el {
177 RTW89_NO_MSK,
178 RTW89_SMA,
179 RTW89_TMA,
180 RTW89_BSSID
181 };
182
183 enum rtw89_sch_tx_sel {
184 RTW89_SCH_TX_SEL_ALL,
185 RTW89_SCH_TX_SEL_HIQ,
186 RTW89_SCH_TX_SEL_MG0,
187 RTW89_SCH_TX_SEL_MACID,
188 };
189
190 /* RTW89_ADDR_CAM_SEC_NONE : not enabled
191 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
192 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
193 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
194 */
195 enum rtw89_add_cam_sec_mode {
196 RTW89_ADDR_CAM_SEC_NONE = 0,
197 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
198 RTW89_ADDR_CAM_SEC_NORMAL = 2,
199 RTW89_ADDR_CAM_SEC_4GROUP = 3,
200 };
201
202 enum rtw89_sec_key_type {
203 RTW89_SEC_KEY_TYPE_NONE = 0,
204 RTW89_SEC_KEY_TYPE_WEP40 = 1,
205 RTW89_SEC_KEY_TYPE_WEP104 = 2,
206 RTW89_SEC_KEY_TYPE_TKIP = 3,
207 RTW89_SEC_KEY_TYPE_WAPI = 4,
208 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
209 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
210 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
211 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
212 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
213 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
214 };
215
216 enum rtw89_port {
217 RTW89_PORT_0 = 0,
218 RTW89_PORT_1 = 1,
219 RTW89_PORT_2 = 2,
220 RTW89_PORT_3 = 3,
221 RTW89_PORT_4 = 4,
222 RTW89_PORT_NUM
223 };
224
225 enum rtw89_band {
226 RTW89_BAND_2G = 0,
227 RTW89_BAND_5G = 1,
228 RTW89_BAND_6G = 2,
229 RTW89_BAND_MAX,
230 };
231
232 enum rtw89_hw_rate {
233 RTW89_HW_RATE_CCK1 = 0x0,
234 RTW89_HW_RATE_CCK2 = 0x1,
235 RTW89_HW_RATE_CCK5_5 = 0x2,
236 RTW89_HW_RATE_CCK11 = 0x3,
237 RTW89_HW_RATE_OFDM6 = 0x4,
238 RTW89_HW_RATE_OFDM9 = 0x5,
239 RTW89_HW_RATE_OFDM12 = 0x6,
240 RTW89_HW_RATE_OFDM18 = 0x7,
241 RTW89_HW_RATE_OFDM24 = 0x8,
242 RTW89_HW_RATE_OFDM36 = 0x9,
243 RTW89_HW_RATE_OFDM48 = 0xA,
244 RTW89_HW_RATE_OFDM54 = 0xB,
245 RTW89_HW_RATE_MCS0 = 0x80,
246 RTW89_HW_RATE_MCS1 = 0x81,
247 RTW89_HW_RATE_MCS2 = 0x82,
248 RTW89_HW_RATE_MCS3 = 0x83,
249 RTW89_HW_RATE_MCS4 = 0x84,
250 RTW89_HW_RATE_MCS5 = 0x85,
251 RTW89_HW_RATE_MCS6 = 0x86,
252 RTW89_HW_RATE_MCS7 = 0x87,
253 RTW89_HW_RATE_MCS8 = 0x88,
254 RTW89_HW_RATE_MCS9 = 0x89,
255 RTW89_HW_RATE_MCS10 = 0x8A,
256 RTW89_HW_RATE_MCS11 = 0x8B,
257 RTW89_HW_RATE_MCS12 = 0x8C,
258 RTW89_HW_RATE_MCS13 = 0x8D,
259 RTW89_HW_RATE_MCS14 = 0x8E,
260 RTW89_HW_RATE_MCS15 = 0x8F,
261 RTW89_HW_RATE_MCS16 = 0x90,
262 RTW89_HW_RATE_MCS17 = 0x91,
263 RTW89_HW_RATE_MCS18 = 0x92,
264 RTW89_HW_RATE_MCS19 = 0x93,
265 RTW89_HW_RATE_MCS20 = 0x94,
266 RTW89_HW_RATE_MCS21 = 0x95,
267 RTW89_HW_RATE_MCS22 = 0x96,
268 RTW89_HW_RATE_MCS23 = 0x97,
269 RTW89_HW_RATE_MCS24 = 0x98,
270 RTW89_HW_RATE_MCS25 = 0x99,
271 RTW89_HW_RATE_MCS26 = 0x9A,
272 RTW89_HW_RATE_MCS27 = 0x9B,
273 RTW89_HW_RATE_MCS28 = 0x9C,
274 RTW89_HW_RATE_MCS29 = 0x9D,
275 RTW89_HW_RATE_MCS30 = 0x9E,
276 RTW89_HW_RATE_MCS31 = 0x9F,
277 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
278 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
279 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
280 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
281 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
282 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
283 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
284 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
285 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
286 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
287 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
288 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
289 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
290 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
291 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
292 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
293 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
294 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
295 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
296 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
297 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
298 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
299 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
300 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
301 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
302 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
303 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
304 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
305 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
306 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
307 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
308 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
309 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
310 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
311 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
312 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
313 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
314 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
315 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
316 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
317 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
318 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
319 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
320 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
321 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
322 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
323 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
324 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
325 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
326 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
327 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
328 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
329 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
330 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
331 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
332 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
333 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
334 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
335 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
336 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
337 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
338 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
339 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
340 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
341 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
342 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
343 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
344 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
345 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
346 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
347 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
348 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
349 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
350 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
351 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
352 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
353 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
354 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
355 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
356 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
357 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
358 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
359 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
360 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
361 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
362 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
363 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
364 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
365 RTW89_HW_RATE_NR,
366
367 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
368 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
369 };
370
371 /* 2G channels,
372 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
373 */
374 #define RTW89_2G_CH_NUM 14
375
376 /* 5G channels,
377 * 36, 38, 40, 42, 44, 46, 48, 50,
378 * 52, 54, 56, 58, 60, 62, 64,
379 * 100, 102, 104, 106, 108, 110, 112, 114,
380 * 116, 118, 120, 122, 124, 126, 128, 130,
381 * 132, 134, 136, 138, 140, 142, 144,
382 * 149, 151, 153, 155, 157, 159, 161, 163,
383 * 165, 167, 169, 171, 173, 175, 177
384 */
385 #define RTW89_5G_CH_NUM 53
386
387 /* 6G channels,
388 * 1, 3, 5, 7, 9, 11, 13, 15,
389 * 17, 19, 21, 23, 25, 27, 29, 33,
390 * 35, 37, 39, 41, 43, 45, 47, 49,
391 * 51, 53, 55, 57, 59, 61, 65, 67,
392 * 69, 71, 73, 75, 77, 79, 81, 83,
393 * 85, 87, 89, 91, 93, 97, 99, 101,
394 * 103, 105, 107, 109, 111, 113, 115, 117,
395 * 119, 121, 123, 125, 129, 131, 133, 135,
396 * 137, 139, 141, 143, 145, 147, 149, 151,
397 * 153, 155, 157, 161, 163, 165, 167, 169,
398 * 171, 173, 175, 177, 179, 181, 183, 185,
399 * 187, 189, 193, 195, 197, 199, 201, 203,
400 * 205, 207, 209, 211, 213, 215, 217, 219,
401 * 221, 225, 227, 229, 231, 233, 235, 237,
402 * 239, 241, 243, 245, 247, 249, 251, 253,
403 */
404 #define RTW89_6G_CH_NUM 120
405
406 enum rtw89_rate_section {
407 RTW89_RS_CCK,
408 RTW89_RS_OFDM,
409 RTW89_RS_MCS, /* for HT/VHT/HE */
410 RTW89_RS_HEDCM,
411 RTW89_RS_OFFSET,
412 RTW89_RS_MAX,
413 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
414 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
415 };
416
417 enum rtw89_rate_max {
418 RTW89_RATE_CCK_MAX = 4,
419 RTW89_RATE_OFDM_MAX = 8,
420 RTW89_RATE_MCS_MAX = 12,
421 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */
422 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
423 };
424
425 enum rtw89_nss {
426 RTW89_NSS_1 = 0,
427 RTW89_NSS_2 = 1,
428 /* HE DCM only support 1ss and 2ss */
429 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1,
430 RTW89_NSS_3 = 2,
431 RTW89_NSS_4 = 3,
432 RTW89_NSS_MAX,
433 };
434
435 enum rtw89_ntx {
436 RTW89_1TX = 0,
437 RTW89_2TX = 1,
438 RTW89_NTX_NUM,
439 };
440
441 enum rtw89_beamforming_type {
442 RTW89_NONBF = 0,
443 RTW89_BF = 1,
444 RTW89_BF_NUM,
445 };
446
447 enum rtw89_regulation_type {
448 RTW89_WW = 0,
449 RTW89_ETSI = 1,
450 RTW89_FCC = 2,
451 RTW89_MKK = 3,
452 RTW89_NA = 4,
453 RTW89_IC = 5,
454 RTW89_KCC = 6,
455 RTW89_ACMA = 7,
456 RTW89_NCC = 8,
457 RTW89_MEXICO = 9,
458 RTW89_CHILE = 10,
459 RTW89_UKRAINE = 11,
460 RTW89_CN = 12,
461 RTW89_QATAR = 13,
462 RTW89_UK = 14,
463 RTW89_REGD_NUM,
464 };
465
466 struct rtw89_txpwr_byrate {
467 s8 cck[RTW89_RATE_CCK_MAX];
468 s8 ofdm[RTW89_RATE_OFDM_MAX];
469 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX];
470 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX];
471 s8 offset[RTW89_RATE_OFFSET_MAX];
472 };
473
474 enum rtw89_bandwidth_section_num {
475 RTW89_BW20_SEC_NUM = 8,
476 RTW89_BW40_SEC_NUM = 4,
477 RTW89_BW80_SEC_NUM = 2,
478 };
479
480 struct rtw89_txpwr_limit {
481 s8 cck_20m[RTW89_BF_NUM];
482 s8 cck_40m[RTW89_BF_NUM];
483 s8 ofdm[RTW89_BF_NUM];
484 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM];
485 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM];
486 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM];
487 s8 mcs_160m[RTW89_BF_NUM];
488 s8 mcs_40m_0p5[RTW89_BF_NUM];
489 s8 mcs_40m_2p5[RTW89_BF_NUM];
490 };
491
492 #define RTW89_RU_SEC_NUM 8
493
494 struct rtw89_txpwr_limit_ru {
495 s8 ru26[RTW89_RU_SEC_NUM];
496 s8 ru52[RTW89_RU_SEC_NUM];
497 s8 ru106[RTW89_RU_SEC_NUM];
498 };
499
500 struct rtw89_rate_desc {
501 enum rtw89_nss nss;
502 enum rtw89_rate_section rs;
503 u8 idx;
504 };
505
506 #define PHY_STS_HDR_LEN 8
507 #define RF_PATH_MAX 4
508 #define RTW89_MAX_PPDU_CNT 8
509 struct rtw89_rx_phy_ppdu {
510 u8 *buf;
511 u32 len;
512 u8 rssi_avg;
513 s8 rssi[RF_PATH_MAX];
514 u8 mac_id;
515 u8 chan_idx;
516 u8 ie;
517 u16 rate;
518 bool to_self;
519 bool valid;
520 };
521
522 enum rtw89_mac_idx {
523 RTW89_MAC_0 = 0,
524 RTW89_MAC_1 = 1,
525 };
526
527 enum rtw89_phy_idx {
528 RTW89_PHY_0 = 0,
529 RTW89_PHY_1 = 1,
530 RTW89_PHY_MAX
531 };
532
533 enum rtw89_rf_path {
534 RF_PATH_A = 0,
535 RF_PATH_B = 1,
536 RF_PATH_C = 2,
537 RF_PATH_D = 3,
538 RF_PATH_AB,
539 RF_PATH_AC,
540 RF_PATH_AD,
541 RF_PATH_BC,
542 RF_PATH_BD,
543 RF_PATH_CD,
544 RF_PATH_ABC,
545 RF_PATH_ABD,
546 RF_PATH_ACD,
547 RF_PATH_BCD,
548 RF_PATH_ABCD,
549 };
550
551 enum rtw89_rf_path_bit {
552 RF_A = BIT(0),
553 RF_B = BIT(1),
554 RF_C = BIT(2),
555 RF_D = BIT(3),
556
557 RF_AB = (RF_A | RF_B),
558 RF_AC = (RF_A | RF_C),
559 RF_AD = (RF_A | RF_D),
560 RF_BC = (RF_B | RF_C),
561 RF_BD = (RF_B | RF_D),
562 RF_CD = (RF_C | RF_D),
563
564 RF_ABC = (RF_A | RF_B | RF_C),
565 RF_ABD = (RF_A | RF_B | RF_D),
566 RF_ACD = (RF_A | RF_C | RF_D),
567 RF_BCD = (RF_B | RF_C | RF_D),
568
569 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
570 };
571
572 enum rtw89_bandwidth {
573 RTW89_CHANNEL_WIDTH_20 = 0,
574 RTW89_CHANNEL_WIDTH_40 = 1,
575 RTW89_CHANNEL_WIDTH_80 = 2,
576 RTW89_CHANNEL_WIDTH_160 = 3,
577 RTW89_CHANNEL_WIDTH_80_80 = 4,
578 RTW89_CHANNEL_WIDTH_5 = 5,
579 RTW89_CHANNEL_WIDTH_10 = 6,
580 };
581
582 enum rtw89_ps_mode {
583 RTW89_PS_MODE_NONE = 0,
584 RTW89_PS_MODE_RFOFF = 1,
585 RTW89_PS_MODE_CLK_GATED = 2,
586 RTW89_PS_MODE_PWR_GATED = 3,
587 };
588
589 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
590 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
591 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
592 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
593
594 enum rtw89_ru_bandwidth {
595 RTW89_RU26 = 0,
596 RTW89_RU52 = 1,
597 RTW89_RU106 = 2,
598 RTW89_RU_NUM,
599 };
600
601 enum rtw89_sc_offset {
602 RTW89_SC_DONT_CARE = 0,
603 RTW89_SC_20_UPPER = 1,
604 RTW89_SC_20_LOWER = 2,
605 RTW89_SC_20_UPMOST = 3,
606 RTW89_SC_20_LOWEST = 4,
607 RTW89_SC_20_UP2X = 5,
608 RTW89_SC_20_LOW2X = 6,
609 RTW89_SC_20_UP3X = 7,
610 RTW89_SC_20_LOW3X = 8,
611 RTW89_SC_40_UPPER = 9,
612 RTW89_SC_40_LOWER = 10,
613 };
614
615 struct rtw89_channel_params {
616 u8 center_chan;
617 u32 center_freq;
618 u8 primary_chan;
619 u8 bandwidth;
620 u8 pri_ch_idx;
621 u8 band_type;
622 u8 subband_type;
623 };
624
625 struct rtw89_channel_help_params {
626 u32 tx_en;
627 };
628
629 struct rtw89_port_reg {
630 u32 port_cfg;
631 u32 tbtt_prohib;
632 u32 bcn_area;
633 u32 bcn_early;
634 u32 tbtt_early;
635 u32 tbtt_agg;
636 u32 bcn_space;
637 u32 bcn_forcetx;
638 u32 bcn_err_cnt;
639 u32 bcn_err_flag;
640 u32 dtim_ctrl;
641 u32 tbtt_shift;
642 u32 bcn_cnt_tmr;
643 u32 tsftr_l;
644 u32 tsftr_h;
645 };
646
647 struct rtw89_txwd_body {
648 __le32 dword0;
649 __le32 dword1;
650 __le32 dword2;
651 __le32 dword3;
652 __le32 dword4;
653 __le32 dword5;
654 } __packed;
655
656 struct rtw89_txwd_body_v1 {
657 __le32 dword0;
658 __le32 dword1;
659 __le32 dword2;
660 __le32 dword3;
661 __le32 dword4;
662 __le32 dword5;
663 __le32 dword6;
664 __le32 dword7;
665 } __packed;
666
667 struct rtw89_txwd_info {
668 __le32 dword0;
669 __le32 dword1;
670 __le32 dword2;
671 __le32 dword3;
672 __le32 dword4;
673 __le32 dword5;
674 } __packed;
675
676 struct rtw89_rx_desc_info {
677 u16 pkt_size;
678 u8 pkt_type;
679 u8 drv_info_size;
680 u8 shift;
681 u8 wl_hd_iv_len;
682 bool long_rxdesc;
683 bool bb_sel;
684 bool mac_info_valid;
685 u16 data_rate;
686 u8 gi_ltf;
687 u8 bw;
688 u32 free_run_cnt;
689 u8 user_id;
690 bool sr_en;
691 u8 ppdu_cnt;
692 u8 ppdu_type;
693 bool icv_err;
694 bool crc32_err;
695 bool hw_dec;
696 bool sw_dec;
697 bool addr1_match;
698 u8 frag;
699 u16 seq;
700 u8 frame_type;
701 u8 rx_pl_id;
702 bool addr_cam_valid;
703 u8 addr_cam_id;
704 u8 sec_cam_id;
705 u8 mac_id;
706 u16 offset;
707 bool ready;
708 };
709
710 struct rtw89_rxdesc_short {
711 __le32 dword0;
712 __le32 dword1;
713 __le32 dword2;
714 __le32 dword3;
715 } __packed;
716
717 struct rtw89_rxdesc_long {
718 __le32 dword0;
719 __le32 dword1;
720 __le32 dword2;
721 __le32 dword3;
722 __le32 dword4;
723 __le32 dword5;
724 __le32 dword6;
725 __le32 dword7;
726 } __packed;
727
728 struct rtw89_tx_desc_info {
729 u16 pkt_size;
730 u8 wp_offset;
731 u8 mac_id;
732 u8 qsel;
733 u8 ch_dma;
734 u8 hdr_llc_len;
735 bool is_bmc;
736 bool en_wd_info;
737 bool wd_page;
738 bool use_rate;
739 bool dis_data_fb;
740 bool tid_indicate;
741 bool agg_en;
742 bool bk;
743 u8 ampdu_density;
744 u8 ampdu_num;
745 bool sec_en;
746 u8 addr_info_nr;
747 u8 sec_keyid;
748 u8 sec_type;
749 u8 sec_cam_idx;
750 u8 sec_seq[6];
751 u16 data_rate;
752 u16 data_retry_lowest_rate;
753 bool fw_dl;
754 u16 seq;
755 bool a_ctrl_bsr;
756 u8 hw_ssn_sel;
757 #define RTW89_MGMT_HW_SSN_SEL 1
758 u8 hw_seq_mode;
759 #define RTW89_MGMT_HW_SEQ_MODE 1
760 bool hiq;
761 u8 port;
762 };
763
764 struct rtw89_core_tx_request {
765 enum rtw89_core_tx_type tx_type;
766
767 struct sk_buff *skb;
768 struct ieee80211_vif *vif;
769 struct ieee80211_sta *sta;
770 struct rtw89_tx_desc_info desc_info;
771 };
772
773 struct rtw89_txq {
774 struct list_head list;
775 unsigned long flags;
776 int wait_cnt;
777 };
778
779 struct rtw89_mac_ax_gnt {
780 u8 gnt_bt_sw_en;
781 u8 gnt_bt;
782 u8 gnt_wl_sw_en;
783 u8 gnt_wl;
784 };
785
786 #define RTW89_MAC_AX_COEX_GNT_NR 2
787 struct rtw89_mac_ax_coex_gnt {
788 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
789 };
790
791 enum rtw89_btc_ncnt {
792 BTC_NCNT_POWER_ON = 0x0,
793 BTC_NCNT_POWER_OFF,
794 BTC_NCNT_INIT_COEX,
795 BTC_NCNT_SCAN_START,
796 BTC_NCNT_SCAN_FINISH,
797 BTC_NCNT_SPECIAL_PACKET,
798 BTC_NCNT_SWITCH_BAND,
799 BTC_NCNT_RFK_TIMEOUT,
800 BTC_NCNT_SHOW_COEX_INFO,
801 BTC_NCNT_ROLE_INFO,
802 BTC_NCNT_CONTROL,
803 BTC_NCNT_RADIO_STATE,
804 BTC_NCNT_CUSTOMERIZE,
805 BTC_NCNT_WL_RFK,
806 BTC_NCNT_WL_STA,
807 BTC_NCNT_FWINFO,
808 BTC_NCNT_TIMER,
809 BTC_NCNT_NUM
810 };
811
812 enum rtw89_btc_btinfo {
813 BTC_BTINFO_L0 = 0,
814 BTC_BTINFO_L1,
815 BTC_BTINFO_L2,
816 BTC_BTINFO_L3,
817 BTC_BTINFO_H0,
818 BTC_BTINFO_H1,
819 BTC_BTINFO_H2,
820 BTC_BTINFO_H3,
821 BTC_BTINFO_MAX
822 };
823
824 enum rtw89_btc_dcnt {
825 BTC_DCNT_RUN = 0x0,
826 BTC_DCNT_CX_RUNINFO,
827 BTC_DCNT_RPT,
828 BTC_DCNT_RPT_FREEZE,
829 BTC_DCNT_CYCLE,
830 BTC_DCNT_CYCLE_FREEZE,
831 BTC_DCNT_W1,
832 BTC_DCNT_W1_FREEZE,
833 BTC_DCNT_B1,
834 BTC_DCNT_B1_FREEZE,
835 BTC_DCNT_TDMA_NONSYNC,
836 BTC_DCNT_SLOT_NONSYNC,
837 BTC_DCNT_BTCNT_FREEZE,
838 BTC_DCNT_WL_SLOT_DRIFT,
839 BTC_DCNT_WL_STA_LAST,
840 BTC_DCNT_NUM,
841 };
842
843 enum rtw89_btc_wl_state_cnt {
844 BTC_WCNT_SCANAP = 0x0,
845 BTC_WCNT_DHCP,
846 BTC_WCNT_EAPOL,
847 BTC_WCNT_ARP,
848 BTC_WCNT_SCBDUPDATE,
849 BTC_WCNT_RFK_REQ,
850 BTC_WCNT_RFK_GO,
851 BTC_WCNT_RFK_REJECT,
852 BTC_WCNT_RFK_TIMEOUT,
853 BTC_WCNT_CH_UPDATE,
854 BTC_WCNT_NUM
855 };
856
857 enum rtw89_btc_bt_state_cnt {
858 BTC_BCNT_RETRY = 0x0,
859 BTC_BCNT_REINIT,
860 BTC_BCNT_REENABLE,
861 BTC_BCNT_SCBDREAD,
862 BTC_BCNT_RELINK,
863 BTC_BCNT_IGNOWL,
864 BTC_BCNT_INQPAG,
865 BTC_BCNT_INQ,
866 BTC_BCNT_PAGE,
867 BTC_BCNT_ROLESW,
868 BTC_BCNT_AFH,
869 BTC_BCNT_INFOUPDATE,
870 BTC_BCNT_INFOSAME,
871 BTC_BCNT_SCBDUPDATE,
872 BTC_BCNT_HIPRI_TX,
873 BTC_BCNT_HIPRI_RX,
874 BTC_BCNT_LOPRI_TX,
875 BTC_BCNT_LOPRI_RX,
876 BTC_BCNT_POLUT,
877 BTC_BCNT_RATECHG,
878 BTC_BCNT_NUM
879 };
880
881 enum rtw89_btc_bt_profile {
882 BTC_BT_NOPROFILE = 0,
883 BTC_BT_HFP = BIT(0),
884 BTC_BT_HID = BIT(1),
885 BTC_BT_A2DP = BIT(2),
886 BTC_BT_PAN = BIT(3),
887 BTC_PROFILE_MAX = 4,
888 };
889
890 struct rtw89_btc_ant_info {
891 u8 type; /* shared, dedicated */
892 u8 num;
893 u8 isolation;
894
895 u8 single_pos: 1;/* Single antenna at S0 or S1 */
896 u8 diversity: 1;
897 };
898
899 enum rtw89_tfc_dir {
900 RTW89_TFC_UL,
901 RTW89_TFC_DL,
902 };
903
904 struct rtw89_btc_wl_smap {
905 u32 busy: 1;
906 u32 scan: 1;
907 u32 connecting: 1;
908 u32 roaming: 1;
909 u32 _4way: 1;
910 u32 rf_off: 1;
911 u32 lps: 1;
912 u32 ips: 1;
913 u32 init_ok: 1;
914 u32 traffic_dir : 2;
915 u32 rf_off_pre: 1;
916 u32 lps_pre: 1;
917 };
918
919 enum rtw89_tfc_lv {
920 RTW89_TFC_IDLE,
921 RTW89_TFC_ULTRA_LOW,
922 RTW89_TFC_LOW,
923 RTW89_TFC_MID,
924 RTW89_TFC_HIGH,
925 };
926
927 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
928 DECLARE_EWMA(tp, 10, 2);
929
930 struct rtw89_traffic_stats {
931 /* units in bytes */
932 u64 tx_unicast;
933 u64 rx_unicast;
934 u32 tx_avg_len;
935 u32 rx_avg_len;
936
937 /* count for packets */
938 u64 tx_cnt;
939 u64 rx_cnt;
940
941 /* units in Mbps */
942 u32 tx_throughput;
943 u32 rx_throughput;
944 u32 tx_throughput_raw;
945 u32 rx_throughput_raw;
946 enum rtw89_tfc_lv tx_tfc_lv;
947 enum rtw89_tfc_lv rx_tfc_lv;
948 struct ewma_tp tx_ewma_tp;
949 struct ewma_tp rx_ewma_tp;
950
951 u16 tx_rate;
952 u16 rx_rate;
953 };
954
955 struct rtw89_btc_statistic {
956 u8 rssi; /* 0%~110% (dBm = rssi -110) */
957 struct rtw89_traffic_stats traffic;
958 };
959
960 #define BTC_WL_RSSI_THMAX 4
961
962 struct rtw89_btc_wl_link_info {
963 struct rtw89_btc_statistic stat;
964 enum rtw89_tfc_dir dir;
965 u8 rssi_state[BTC_WL_RSSI_THMAX];
966 u8 mac_addr[ETH_ALEN];
967 u8 busy;
968 u8 ch;
969 u8 bw;
970 u8 band;
971 u8 role;
972 u8 pid;
973 u8 phy;
974 u8 dtim_period;
975 u8 mode;
976
977 u8 mac_id;
978 u8 tx_retry;
979
980 u32 bcn_period;
981 u32 busy_t;
982 u32 tx_time;
983 u32 client_cnt;
984 u32 rx_rate_drop_cnt;
985
986 u32 active: 1;
987 u32 noa: 1;
988 u32 client_ps: 1;
989 u32 connected: 2;
990 };
991
992 union rtw89_btc_wl_state_map {
993 u32 val;
994 struct rtw89_btc_wl_smap map;
995 };
996
997 struct rtw89_btc_bt_hfp_desc {
998 u32 exist: 1;
999 u32 type: 2;
1000 u32 rsvd: 29;
1001 };
1002
1003 struct rtw89_btc_bt_hid_desc {
1004 u32 exist: 1;
1005 u32 slot_info: 2;
1006 u32 pair_cnt: 2;
1007 u32 type: 8;
1008 u32 rsvd: 19;
1009 };
1010
1011 struct rtw89_btc_bt_a2dp_desc {
1012 u8 exist: 1;
1013 u8 exist_last: 1;
1014 u8 play_latency: 1;
1015 u8 type: 3;
1016 u8 active: 1;
1017 u8 sink: 1;
1018
1019 u8 bitpool;
1020 u16 vendor_id;
1021 u32 device_name;
1022 u32 flush_time;
1023 };
1024
1025 struct rtw89_btc_bt_pan_desc {
1026 u32 exist: 1;
1027 u32 type: 1;
1028 u32 active: 1;
1029 u32 rsvd: 29;
1030 };
1031
1032 struct rtw89_btc_bt_rfk_info {
1033 u32 run: 1;
1034 u32 req: 1;
1035 u32 timeout: 1;
1036 u32 rsvd: 29;
1037 };
1038
1039 union rtw89_btc_bt_rfk_info_map {
1040 u32 val;
1041 struct rtw89_btc_bt_rfk_info map;
1042 };
1043
1044 struct rtw89_btc_bt_ver_info {
1045 u32 fw_coex; /* match with which coex_ver */
1046 u32 fw;
1047 };
1048
1049 struct rtw89_btc_bool_sta_chg {
1050 u32 now: 1;
1051 u32 last: 1;
1052 u32 remain: 1;
1053 u32 srvd: 29;
1054 };
1055
1056 struct rtw89_btc_u8_sta_chg {
1057 u8 now;
1058 u8 last;
1059 u8 remain;
1060 u8 rsvd;
1061 };
1062
1063 struct rtw89_btc_wl_scan_info {
1064 u8 band[RTW89_PHY_MAX];
1065 u8 phy_map;
1066 u8 rsvd;
1067 };
1068
1069 struct rtw89_btc_wl_dbcc_info {
1070 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1071 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */
1072 u8 real_band[RTW89_PHY_MAX];
1073 u8 role[RTW89_PHY_MAX]; /* role in each phy */
1074 };
1075
1076 struct rtw89_btc_wl_active_role {
1077 u8 connected: 1;
1078 u8 pid: 3;
1079 u8 phy: 1;
1080 u8 noa: 1;
1081 u8 band: 2;
1082
1083 u8 client_ps: 1;
1084 u8 bw: 7;
1085
1086 u8 role;
1087 u8 ch;
1088
1089 u16 tx_lvl;
1090 u16 rx_lvl;
1091 u16 tx_rate;
1092 u16 rx_rate;
1093 };
1094
1095 struct rtw89_btc_wl_role_info_bpos {
1096 u16 none: 1;
1097 u16 station: 1;
1098 u16 ap: 1;
1099 u16 vap: 1;
1100 u16 adhoc: 1;
1101 u16 adhoc_master: 1;
1102 u16 mesh: 1;
1103 u16 moniter: 1;
1104 u16 p2p_device: 1;
1105 u16 p2p_gc: 1;
1106 u16 p2p_go: 1;
1107 u16 nan: 1;
1108 };
1109
1110 union rtw89_btc_wl_role_info_map {
1111 u16 val;
1112 struct rtw89_btc_wl_role_info_bpos role;
1113 };
1114
1115 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1116 u8 connect_cnt;
1117 u8 link_mode;
1118 union rtw89_btc_wl_role_info_map role_map;
1119 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1120 };
1121
1122 struct rtw89_btc_wl_ver_info {
1123 u32 fw_coex; /* match with which coex_ver */
1124 u32 fw;
1125 u32 mac;
1126 u32 bb;
1127 u32 rf;
1128 };
1129
1130 struct rtw89_btc_wl_afh_info {
1131 u8 en;
1132 u8 ch;
1133 u8 bw;
1134 u8 rsvd;
1135 } __packed;
1136
1137 struct rtw89_btc_wl_rfk_info {
1138 u32 state: 2;
1139 u32 path_map: 4;
1140 u32 phy_map: 2;
1141 u32 band: 2;
1142 u32 type: 8;
1143 u32 rsvd: 14;
1144 };
1145
1146 struct rtw89_btc_bt_smap {
1147 u32 connect: 1;
1148 u32 ble_connect: 1;
1149 u32 acl_busy: 1;
1150 u32 sco_busy: 1;
1151 u32 mesh_busy: 1;
1152 u32 inq_pag: 1;
1153 };
1154
1155 union rtw89_btc_bt_state_map {
1156 u32 val;
1157 struct rtw89_btc_bt_smap map;
1158 };
1159
1160 #define BTC_BT_RSSI_THMAX 4
1161 #define BTC_BT_AFH_GROUP 12
1162
1163 struct rtw89_btc_bt_link_info {
1164 struct rtw89_btc_u8_sta_chg profile_cnt;
1165 struct rtw89_btc_bool_sta_chg multi_link;
1166 struct rtw89_btc_bool_sta_chg relink;
1167 struct rtw89_btc_bt_hfp_desc hfp_desc;
1168 struct rtw89_btc_bt_hid_desc hid_desc;
1169 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1170 struct rtw89_btc_bt_pan_desc pan_desc;
1171 union rtw89_btc_bt_state_map status;
1172
1173 u8 sut_pwr_level[BTC_PROFILE_MAX];
1174 u8 golden_rx_shift[BTC_PROFILE_MAX];
1175 u8 rssi_state[BTC_BT_RSSI_THMAX];
1176 u8 afh_map[BTC_BT_AFH_GROUP];
1177
1178 u32 role_sw: 1;
1179 u32 slave_role: 1;
1180 u32 afh_update: 1;
1181 u32 cqddr: 1;
1182 u32 rssi: 8;
1183 u32 tx_3m: 1;
1184 u32 rsvd: 19;
1185 };
1186
1187 struct rtw89_btc_3rdcx_info {
1188 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1189 u8 hw_coex;
1190 u16 rsvd;
1191 };
1192
1193 struct rtw89_btc_dm_emap {
1194 u32 init: 1;
1195 u32 pta_owner: 1;
1196 u32 wl_rfk_timeout: 1;
1197 u32 bt_rfk_timeout: 1;
1198
1199 u32 wl_fw_hang: 1;
1200 u32 offload_mismatch: 1;
1201 u32 cycle_hang: 1;
1202 u32 w1_hang: 1;
1203
1204 u32 b1_hang: 1;
1205 u32 tdma_no_sync: 1;
1206 u32 wl_slot_drift: 1;
1207 };
1208
1209 union rtw89_btc_dm_error_map {
1210 u32 val;
1211 struct rtw89_btc_dm_emap map;
1212 };
1213
1214 struct rtw89_btc_rf_para {
1215 u32 tx_pwr_freerun;
1216 u32 rx_gain_freerun;
1217 u32 tx_pwr_perpkt;
1218 u32 rx_gain_perpkt;
1219 };
1220
1221 struct rtw89_btc_wl_info {
1222 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1223 struct rtw89_btc_wl_rfk_info rfk_info;
1224 struct rtw89_btc_wl_ver_info ver_info;
1225 struct rtw89_btc_wl_afh_info afh_info;
1226 struct rtw89_btc_wl_role_info role_info;
1227 struct rtw89_btc_wl_scan_info scan_info;
1228 struct rtw89_btc_wl_dbcc_info dbcc_info;
1229 struct rtw89_btc_rf_para rf_para;
1230 union rtw89_btc_wl_state_map status;
1231
1232 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1233 u8 rssi_level;
1234
1235 u32 scbd;
1236 };
1237
1238 struct rtw89_btc_module {
1239 struct rtw89_btc_ant_info ant;
1240 u8 rfe_type;
1241 u8 cv;
1242
1243 u8 bt_solo: 1;
1244 u8 bt_pos: 1;
1245 u8 switch_type: 1;
1246
1247 u8 rsvd;
1248 };
1249
1250 #define RTW89_BTC_DM_MAXSTEP 30
1251 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1252
1253 struct rtw89_btc_dm_step {
1254 u16 step[RTW89_BTC_DM_MAXSTEP];
1255 u8 step_pos;
1256 bool step_ov;
1257 };
1258
1259 struct rtw89_btc_init_info {
1260 struct rtw89_btc_module module;
1261 u8 wl_guard_ch;
1262
1263 u8 wl_only: 1;
1264 u8 wl_init_ok: 1;
1265 u8 dbcc_en: 1;
1266 u8 cx_other: 1;
1267 u8 bt_only: 1;
1268
1269 u16 rsvd;
1270 };
1271
1272 struct rtw89_btc_wl_tx_limit_para {
1273 u16 enable;
1274 u32 tx_time; /* unit: us */
1275 u16 tx_retry;
1276 };
1277
1278 struct rtw89_btc_bt_scan_info {
1279 u16 win;
1280 u16 intvl;
1281 u32 enable: 1;
1282 u32 interlace: 1;
1283 u32 rsvd: 30;
1284 };
1285
1286 enum rtw89_btc_bt_scan_type {
1287 BTC_SCAN_INQ = 0,
1288 BTC_SCAN_PAGE,
1289 BTC_SCAN_BLE,
1290 BTC_SCAN_INIT,
1291 BTC_SCAN_TV,
1292 BTC_SCAN_ADV,
1293 BTC_SCAN_MAX1,
1294 };
1295
1296 struct rtw89_btc_bt_info {
1297 struct rtw89_btc_bt_link_info link_info;
1298 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1];
1299 struct rtw89_btc_bt_ver_info ver_info;
1300 struct rtw89_btc_bool_sta_chg enable;
1301 struct rtw89_btc_bool_sta_chg inq_pag;
1302 struct rtw89_btc_rf_para rf_para;
1303 union rtw89_btc_bt_rfk_info_map rfk_info;
1304
1305 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
1306
1307 u32 scbd;
1308 u32 feature;
1309
1310 u32 mbx_avl: 1;
1311 u32 whql_test: 1;
1312 u32 igno_wl: 1;
1313 u32 reinit: 1;
1314 u32 ble_scan_en: 1;
1315 u32 btg_type: 1;
1316 u32 inq: 1;
1317 u32 pag: 1;
1318 u32 run_patch_code: 1;
1319 u32 hi_lna_rx: 1;
1320 u32 rsvd: 22;
1321 };
1322
1323 struct rtw89_btc_cx {
1324 struct rtw89_btc_wl_info wl;
1325 struct rtw89_btc_bt_info bt;
1326 struct rtw89_btc_3rdcx_info other;
1327 u32 state_map;
1328 u32 cnt_bt[BTC_BCNT_NUM];
1329 u32 cnt_wl[BTC_WCNT_NUM];
1330 };
1331
1332 struct rtw89_btc_fbtc_tdma {
1333 u8 type;
1334 u8 rxflctrl;
1335 u8 txpause;
1336 u8 wtgle_n;
1337 u8 leak_n;
1338 u8 ext_ctrl;
1339 u8 rsvd0;
1340 u8 rsvd1;
1341 } __packed;
1342
1343 #define CXMREG_MAX 30
1344 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
1345 #define BTCRPT_VER 1
1346 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
1347
1348 enum rtw89_btc_bt_rfk_counter {
1349 BTC_BCNT_RFK_REQ = 0,
1350 BTC_BCNT_RFK_GO = 1,
1351 BTC_BCNT_RFK_REJECT = 2,
1352 BTC_BCNT_RFK_FAIL = 3,
1353 BTC_BCNT_RFK_TIMEOUT = 4,
1354 BTC_BCNT_RFK_MAX
1355 };
1356
1357 struct rtw89_btc_fbtc_rpt_ctrl {
1358 u16 fver;
1359 u16 rpt_cnt; /* tmr counters */
1360 u32 wl_fw_coex_ver; /* match which driver's coex version */
1361 u32 wl_fw_cx_offload;
1362 u32 wl_fw_ver;
1363 u32 rpt_enable;
1364 u32 rpt_para; /* ms */
1365 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
1366 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
1367 u32 mb_recv_cnt; /* fw recv mailbox counter */
1368 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
1369 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
1370 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
1371 u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX];
1372 u32 c2h_cnt; /* fw send c2h counter */
1373 u32 h2c_cnt; /* fw recv h2c counter */
1374 } __packed;
1375
1376 enum rtw89_fbtc_ext_ctrl_type {
1377 CXECTL_OFF = 0x0, /* tdma off */
1378 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
1379 CXECTL_EXT = 0x2,
1380 CXECTL_MAX
1381 };
1382
1383 union rtw89_btc_fbtc_rxflct {
1384 u8 val;
1385 u8 type: 3;
1386 u8 tgln_n: 5;
1387 };
1388
1389 enum rtw89_btc_cxst_state {
1390 CXST_OFF = 0x0,
1391 CXST_B2W = 0x1,
1392 CXST_W1 = 0x2,
1393 CXST_W2 = 0x3,
1394 CXST_W2B = 0x4,
1395 CXST_B1 = 0x5,
1396 CXST_B2 = 0x6,
1397 CXST_B3 = 0x7,
1398 CXST_B4 = 0x8,
1399 CXST_LK = 0x9,
1400 CXST_BLK = 0xa,
1401 CXST_E2G = 0xb,
1402 CXST_E5G = 0xc,
1403 CXST_EBT = 0xd,
1404 CXST_ENULL = 0xe,
1405 CXST_WLK = 0xf,
1406 CXST_W1FDD = 0x10,
1407 CXST_B1FDD = 0x11,
1408 CXST_MAX = 0x12,
1409 };
1410
1411 enum {
1412 CXBCN_ALL = 0x0,
1413 CXBCN_ALL_OK,
1414 CXBCN_BT_SLOT,
1415 CXBCN_BT_OK,
1416 CXBCN_MAX
1417 };
1418
1419 enum btc_slot_type {
1420 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
1421 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
1422 CXSTYPE_NUM,
1423 };
1424
1425 enum { /* TIME */
1426 CXT_BT = 0x0,
1427 CXT_WL = 0x1,
1428 CXT_MAX
1429 };
1430
1431 enum { /* TIME-A2DP */
1432 CXT_FLCTRL_OFF = 0x0,
1433 CXT_FLCTRL_ON = 0x1,
1434 CXT_FLCTRL_MAX
1435 };
1436
1437 enum { /* STEP TYPE */
1438 CXSTEP_NONE = 0x0,
1439 CXSTEP_EVNT = 0x1,
1440 CXSTEP_SLOT = 0x2,
1441 CXSTEP_MAX,
1442 };
1443
1444 #define FCXGPIODBG_VER 1
1445 #define BTC_DBG_MAX1 32
1446 struct rtw89_btc_fbtc_gpio_dbg {
1447 u8 fver;
1448 u8 rsvd;
1449 u16 rsvd2;
1450 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
1451 u32 pre_state; /* the debug signal is 1 or 0 */
1452 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
1453 } __packed;
1454
1455 #define FCXMREG_VER 1
1456 struct rtw89_btc_fbtc_mreg_val {
1457 u8 fver;
1458 u8 reg_num;
1459 __le16 rsvd;
1460 __le32 mreg_val[CXMREG_MAX];
1461 } __packed;
1462
1463 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
1464 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
1465 .offset = cpu_to_le32(__offset), }
1466
1467 struct rtw89_btc_fbtc_mreg {
1468 __le16 type;
1469 __le16 bytes;
1470 __le32 offset;
1471 } __packed;
1472
1473 struct rtw89_btc_fbtc_slot {
1474 __le16 dur;
1475 __le32 cxtbl;
1476 __le16 cxtype;
1477 } __packed;
1478
1479 #define FCXSLOTS_VER 1
1480 struct rtw89_btc_fbtc_slots {
1481 u8 fver;
1482 u8 tbl_num;
1483 __le16 rsvd;
1484 __le32 update_map;
1485 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
1486 } __packed;
1487
1488 #define FCXSTEP_VER 2
1489 struct rtw89_btc_fbtc_step {
1490 u8 type;
1491 u8 val;
1492 __le16 difft;
1493 } __packed;
1494
1495 struct rtw89_btc_fbtc_steps {
1496 u8 fver;
1497 u8 rsvd;
1498 __le16 cnt;
1499 __le16 pos_old;
1500 __le16 pos_new;
1501 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
1502 } __packed;
1503
1504 #define FCXCYSTA_VER 2
1505 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */
1506 u8 fver;
1507 u8 rsvd;
1508 __le16 cycles; /* total cycle number */
1509 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
1510 __le16 a2dpept; /* a2dp empty cnt */
1511 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
1512 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
1513 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
1514 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
1515 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
1516 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
1517 __le16 tavg_a2dpept; /* avg a2dp empty time */
1518 __le16 tmax_a2dpept; /* max a2dp empty time */
1519 __le16 tavg_lk; /* avg leak-slot time */
1520 __le16 tmax_lk; /* max leak-slot time */
1521 __le32 slot_cnt[CXST_MAX]; /* slot count */
1522 __le32 bcn_cnt[CXBCN_MAX];
1523 __le32 leakrx_cnt; /* the rximr occur at leak slot */
1524 __le32 collision_cnt; /* counter for event/timer occur at same time */
1525 __le32 skip_cnt;
1526 __le32 exception;
1527 __le32 except_cnt;
1528 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
1529 } __packed;
1530
1531 #define FCXNULLSTA_VER 1
1532 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */
1533 u8 fver;
1534 u8 rsvd;
1535 __le16 rsvd2;
1536 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
1537 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
1538 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
1539 } __packed;
1540
1541 #define FCX_BTVER_VER 1
1542 struct rtw89_btc_fbtc_btver {
1543 u8 fver;
1544 u8 rsvd;
1545 __le16 rsvd2;
1546 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
1547 __le32 fw_ver;
1548 __le32 feature;
1549 } __packed;
1550
1551 #define FCX_BTSCAN_VER 1
1552 struct rtw89_btc_fbtc_btscan {
1553 u8 fver;
1554 u8 rsvd;
1555 __le16 rsvd2;
1556 u8 scan[6];
1557 } __packed;
1558
1559 #define FCX_BTAFH_VER 1
1560 struct rtw89_btc_fbtc_btafh {
1561 u8 fver;
1562 u8 rsvd;
1563 __le16 rsvd2;
1564 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
1565 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
1566 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
1567 } __packed;
1568
1569 #define FCX_BTDEVINFO_VER 1
1570 struct rtw89_btc_fbtc_btdevinfo {
1571 u8 fver;
1572 u8 rsvd;
1573 __le16 vendor_id;
1574 __le32 dev_name; /* only 24 bits valid */
1575 __le32 flush_time;
1576 } __packed;
1577
1578 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
1579 struct rtw89_btc_rf_trx_para {
1580 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
1581 u32 wl_rx_gain; /* rx gain table index (TBD.) */
1582 u8 bt_tx_power; /* decrease Tx power (dB) */
1583 u8 bt_rx_gain; /* LNA constrain level */
1584 };
1585
1586 struct rtw89_btc_dm {
1587 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
1588 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX];
1589 struct rtw89_btc_fbtc_tdma tdma;
1590 struct rtw89_btc_fbtc_tdma tdma_now;
1591 struct rtw89_mac_ax_coex_gnt gnt;
1592 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */
1593 struct rtw89_btc_rf_trx_para rf_trx_para;
1594 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
1595 struct rtw89_btc_dm_step dm_step;
1596 union rtw89_btc_dm_error_map error;
1597 u32 cnt_dm[BTC_DCNT_NUM];
1598 u32 cnt_notify[BTC_NCNT_NUM];
1599
1600 u32 update_slot_map;
1601 u32 set_ant_path;
1602
1603 u32 wl_only: 1;
1604 u32 wl_fw_cx_offload: 1;
1605 u32 freerun: 1;
1606 u32 wl_ps_ctrl: 2;
1607 u32 wl_mimo_ps: 1;
1608 u32 leak_ap: 1;
1609 u32 noisy_level: 3;
1610 u32 coex_info_map: 8;
1611 u32 bt_only: 1;
1612 u32 wl_btg_rx: 1;
1613 u32 trx_para_level: 8;
1614 u32 wl_stb_chg: 1;
1615 u32 rsvd: 3;
1616
1617 u16 slot_dur[CXST_MAX];
1618
1619 u8 run_reason;
1620 u8 run_action;
1621 };
1622
1623 struct rtw89_btc_ctrl {
1624 u32 manual: 1;
1625 u32 igno_bt: 1;
1626 u32 always_freerun: 1;
1627 u32 trace_step: 16;
1628 u32 rsvd: 12;
1629 };
1630
1631 struct rtw89_btc_dbg {
1632 /* cmd "rb" */
1633 bool rb_done;
1634 u32 rb_val;
1635 };
1636
1637 #define FCXTDMA_VER 1
1638
1639 enum rtw89_btc_btf_fw_event {
1640 BTF_EVNT_RPT = 0,
1641 BTF_EVNT_BT_INFO = 1,
1642 BTF_EVNT_BT_SCBD = 2,
1643 BTF_EVNT_BT_REG = 3,
1644 BTF_EVNT_CX_RUNINFO = 4,
1645 BTF_EVNT_BT_PSD = 5,
1646 BTF_EVNT_BUF_OVERFLOW,
1647 BTF_EVNT_C2H_LOOPBACK,
1648 BTF_EVNT_MAX,
1649 };
1650
1651 enum btf_fw_event_report {
1652 BTC_RPT_TYPE_CTRL = 0x0,
1653 BTC_RPT_TYPE_TDMA,
1654 BTC_RPT_TYPE_SLOT,
1655 BTC_RPT_TYPE_CYSTA,
1656 BTC_RPT_TYPE_STEP,
1657 BTC_RPT_TYPE_NULLSTA,
1658 BTC_RPT_TYPE_MREG,
1659 BTC_RPT_TYPE_GPIO_DBG,
1660 BTC_RPT_TYPE_BT_VER,
1661 BTC_RPT_TYPE_BT_SCAN,
1662 BTC_RPT_TYPE_BT_AFH,
1663 BTC_RPT_TYPE_BT_DEVICE,
1664 BTC_RPT_TYPE_TEST,
1665 BTC_RPT_TYPE_MAX = 31
1666 };
1667
1668 enum rtw_btc_btf_reg_type {
1669 REG_MAC = 0x0,
1670 REG_BB = 0x1,
1671 REG_RF = 0x2,
1672 REG_BT_RF = 0x3,
1673 REG_BT_MODEM = 0x4,
1674 REG_BT_BLUEWIZE = 0x5,
1675 REG_BT_VENDOR = 0x6,
1676 REG_BT_LE = 0x7,
1677 REG_MAX_TYPE,
1678 };
1679
1680 struct rtw89_btc_rpt_cmn_info {
1681 u32 rx_cnt;
1682 u32 rx_len;
1683 u32 req_len; /* expected rsp len */
1684 u8 req_fver; /* expected rsp fver */
1685 u8 rsp_fver; /* fver from fw */
1686 u8 valid;
1687 } __packed;
1688
1689 struct rtw89_btc_report_ctrl_state {
1690 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1691 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw */
1692 };
1693
1694 struct rtw89_btc_rpt_fbtc_tdma {
1695 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1696 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */
1697 };
1698
1699 struct rtw89_btc_rpt_fbtc_slots {
1700 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1701 struct rtw89_btc_fbtc_slots finfo; /* info from fw */
1702 };
1703
1704 struct rtw89_btc_rpt_fbtc_cysta {
1705 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1706 struct rtw89_btc_fbtc_cysta finfo; /* info from fw */
1707 };
1708
1709 struct rtw89_btc_rpt_fbtc_step {
1710 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1711 struct rtw89_btc_fbtc_steps finfo; /* info from fw */
1712 };
1713
1714 struct rtw89_btc_rpt_fbtc_nullsta {
1715 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1716 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */
1717 };
1718
1719 struct rtw89_btc_rpt_fbtc_mreg {
1720 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1721 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
1722 };
1723
1724 struct rtw89_btc_rpt_fbtc_gpio_dbg {
1725 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1726 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
1727 };
1728
1729 struct rtw89_btc_rpt_fbtc_btver {
1730 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1731 struct rtw89_btc_fbtc_btver finfo; /* info from fw */
1732 };
1733
1734 struct rtw89_btc_rpt_fbtc_btscan {
1735 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1736 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */
1737 };
1738
1739 struct rtw89_btc_rpt_fbtc_btafh {
1740 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1741 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */
1742 };
1743
1744 struct rtw89_btc_rpt_fbtc_btdev {
1745 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1746 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
1747 };
1748
1749 enum rtw89_btc_btfre_type {
1750 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
1751 BTFRE_UNDEF_TYPE,
1752 BTFRE_EXCEPTION,
1753 BTFRE_MAX,
1754 };
1755
1756 struct rtw89_btc_btf_fwinfo {
1757 u32 cnt_c2h;
1758 u32 cnt_h2c;
1759 u32 cnt_h2c_fail;
1760 u32 event[BTF_EVNT_MAX];
1761
1762 u32 err[BTFRE_MAX];
1763 u32 len_mismch;
1764 u32 fver_mismch;
1765 u32 rpt_en_map;
1766
1767 struct rtw89_btc_report_ctrl_state rpt_ctrl;
1768 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
1769 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
1770 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
1771 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
1772 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
1773 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
1774 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
1775 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
1776 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
1777 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
1778 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
1779 };
1780
1781 #define RTW89_BTC_POLICY_MAXLEN 512
1782
1783 struct rtw89_btc {
1784 struct rtw89_btc_cx cx;
1785 struct rtw89_btc_dm dm;
1786 struct rtw89_btc_ctrl ctrl;
1787 struct rtw89_btc_module mdinfo;
1788 struct rtw89_btc_btf_fwinfo fwinfo;
1789 struct rtw89_btc_dbg dbg;
1790
1791 struct work_struct eapol_notify_work;
1792 struct work_struct arp_notify_work;
1793 struct work_struct dhcp_notify_work;
1794 struct work_struct icmp_notify_work;
1795
1796 u32 bt_req_len;
1797
1798 u8 policy[RTW89_BTC_POLICY_MAXLEN];
1799 u16 policy_len;
1800 u16 policy_type;
1801 bool bt_req_en;
1802 bool update_policy_force;
1803 bool lps;
1804 };
1805
1806 enum rtw89_ra_mode {
1807 RTW89_RA_MODE_CCK = BIT(0),
1808 RTW89_RA_MODE_OFDM = BIT(1),
1809 RTW89_RA_MODE_HT = BIT(2),
1810 RTW89_RA_MODE_VHT = BIT(3),
1811 RTW89_RA_MODE_HE = BIT(4),
1812 };
1813
1814 enum rtw89_ra_report_mode {
1815 RTW89_RA_RPT_MODE_LEGACY,
1816 RTW89_RA_RPT_MODE_HT,
1817 RTW89_RA_RPT_MODE_VHT,
1818 RTW89_RA_RPT_MODE_HE,
1819 };
1820
1821 enum rtw89_dig_noisy_level {
1822 RTW89_DIG_NOISY_LEVEL0 = -1,
1823 RTW89_DIG_NOISY_LEVEL1 = 0,
1824 RTW89_DIG_NOISY_LEVEL2 = 1,
1825 RTW89_DIG_NOISY_LEVEL3 = 2,
1826 RTW89_DIG_NOISY_LEVEL_MAX = 3,
1827 };
1828
1829 enum rtw89_gi_ltf {
1830 RTW89_GILTF_LGI_4XHE32 = 0,
1831 RTW89_GILTF_SGI_4XHE08 = 1,
1832 RTW89_GILTF_2XHE16 = 2,
1833 RTW89_GILTF_2XHE08 = 3,
1834 RTW89_GILTF_1XHE16 = 4,
1835 RTW89_GILTF_1XHE08 = 5,
1836 RTW89_GILTF_MAX
1837 };
1838
1839 enum rtw89_rx_frame_type {
1840 RTW89_RX_TYPE_MGNT = 0,
1841 RTW89_RX_TYPE_CTRL = 1,
1842 RTW89_RX_TYPE_DATA = 2,
1843 RTW89_RX_TYPE_RSVD = 3,
1844 };
1845
1846 struct rtw89_ra_info {
1847 u8 is_dis_ra:1;
1848 /* Bit0 : CCK
1849 * Bit1 : OFDM
1850 * Bit2 : HT
1851 * Bit3 : VHT
1852 * Bit4 : HE
1853 */
1854 u8 mode_ctrl:5;
1855 u8 bw_cap:2;
1856 u8 macid;
1857 u8 dcm_cap:1;
1858 u8 er_cap:1;
1859 u8 init_rate_lv:2;
1860 u8 upd_all:1;
1861 u8 en_sgi:1;
1862 u8 ldpc_cap:1;
1863 u8 stbc_cap:1;
1864 u8 ss_num:3;
1865 u8 giltf:3;
1866 u8 upd_bw_nss_mask:1;
1867 u8 upd_mask:1;
1868 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
1869 /* BFee CSI */
1870 u8 band_num;
1871 u8 ra_csi_rate_en:1;
1872 u8 fixed_csi_rate_en:1;
1873 u8 cr_tbl_sel:1;
1874 u8 rsvd2:5;
1875 u8 csi_mcs_ss_idx;
1876 u8 csi_mode:2;
1877 u8 csi_gi_ltf:3;
1878 u8 csi_bw:3;
1879 };
1880
1881 #define RTW89_PPDU_MAX_USR 4
1882 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
1883 #define RTW89_PPDU_MAC_INFO_SIZE 8
1884 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
1885
1886 #define RTW89_MAX_RX_AGG_NUM 64
1887 #define RTW89_MAX_TX_AGG_NUM 128
1888
1889 struct rtw89_ampdu_params {
1890 u16 agg_num;
1891 bool amsdu;
1892 };
1893
1894 struct rtw89_ra_report {
1895 struct rate_info txrate;
1896 u32 bit_rate;
1897 u16 hw_rate;
1898 };
1899
1900 DECLARE_EWMA(rssi, 10, 16);
1901
1902 #define RTW89_BA_CAM_NUM 2
1903
1904 struct rtw89_ba_cam_entry {
1905 u8 tid;
1906 };
1907
1908 #define RTW89_MAX_ADDR_CAM_NUM 128
1909 #define RTW89_MAX_BSSID_CAM_NUM 20
1910 #define RTW89_MAX_SEC_CAM_NUM 128
1911 #define RTW89_SEC_CAM_IN_ADDR_CAM 7
1912
1913 struct rtw89_addr_cam_entry {
1914 u8 addr_cam_idx;
1915 u8 offset;
1916 u8 len;
1917 u8 valid : 1;
1918 u8 addr_mask : 6;
1919 u8 wapi : 1;
1920 u8 mask_sel : 2;
1921 u8 bssid_cam_idx: 6;
1922
1923 u8 sec_ent_mode;
1924 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
1925 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
1926 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
1927 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];
1928 };
1929
1930 struct rtw89_bssid_cam_entry {
1931 u8 bssid[ETH_ALEN];
1932 u8 phy_idx;
1933 u8 bssid_cam_idx;
1934 u8 offset;
1935 u8 len;
1936 u8 valid : 1;
1937 u8 num;
1938 };
1939
1940 struct rtw89_sec_cam_entry {
1941 u8 sec_cam_idx;
1942 u8 offset;
1943 u8 len;
1944 u8 type : 4;
1945 u8 ext_key : 1;
1946 u8 spp_mode : 1;
1947 /* 256 bits */
1948 u8 key[32];
1949 };
1950
1951 struct rtw89_sta {
1952 u8 mac_id;
1953 bool disassoc;
1954 struct rtw89_vif *rtwvif;
1955 struct rtw89_ra_info ra;
1956 struct rtw89_ra_report ra_report;
1957 int max_agg_wait;
1958 u8 prev_rssi;
1959 struct ewma_rssi avg_rssi;
1960 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
1961 struct ieee80211_rx_status rx_status;
1962 u16 rx_hw_rate;
1963 __le32 htc_template;
1964 struct rtw89_addr_cam_entry addr_cam; /* AP mode only */
1965
1966 bool use_cfg_mask;
1967 struct cfg80211_bitrate_mask mask;
1968
1969 bool cctl_tx_time;
1970 u32 ampdu_max_time:4;
1971 bool cctl_tx_retry_limit;
1972 u32 data_tx_cnt_lmt:6;
1973
1974 DECLARE_BITMAP(ba_cam_map, RTW89_BA_CAM_NUM);
1975 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_BA_CAM_NUM];
1976 };
1977
1978 struct rtw89_efuse {
1979 bool valid;
1980 u8 xtal_cap;
1981 u8 addr[ETH_ALEN];
1982 u8 rfe_type;
1983 char country_code[2];
1984 };
1985
1986 struct rtw89_phy_rate_pattern {
1987 u64 ra_mask;
1988 u16 rate;
1989 u8 ra_mode;
1990 bool enable;
1991 };
1992
1993 struct rtw89_vif {
1994 struct list_head list;
1995 struct rtw89_dev *rtwdev;
1996 u8 mac_id;
1997 u8 port;
1998 u8 mac_addr[ETH_ALEN];
1999 u8 bssid[ETH_ALEN];
2000 u8 phy_idx;
2001 u8 mac_idx;
2002 u8 net_type;
2003 u8 wifi_role;
2004 u8 self_role;
2005 u8 wmm;
2006 u8 bcn_hit_cond;
2007 u8 hit_rule;
2008 bool trigger;
2009 bool lsig_txop;
2010 u8 tgt_ind;
2011 u8 frm_tgt_ind;
2012 bool wowlan_pattern;
2013 bool wowlan_uc;
2014 bool wowlan_magic;
2015 bool is_hesta;
2016 bool last_a_ctrl;
2017 struct work_struct update_beacon_work;
2018 struct rtw89_addr_cam_entry addr_cam;
2019 struct rtw89_bssid_cam_entry bssid_cam;
2020 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
2021 struct rtw89_traffic_stats stats;
2022 struct rtw89_phy_rate_pattern rate_pattern;
2023 struct cfg80211_scan_request *scan_req;
2024 struct ieee80211_scan_ies *scan_ies;
2025 };
2026
2027 enum rtw89_lv1_rcvy_step {
2028 RTW89_LV1_RCVY_STEP_1,
2029 RTW89_LV1_RCVY_STEP_2,
2030 };
2031
2032 struct rtw89_hci_ops {
2033 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
2034 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
2035 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
2036 void (*reset)(struct rtw89_dev *rtwdev);
2037 int (*start)(struct rtw89_dev *rtwdev);
2038 void (*stop)(struct rtw89_dev *rtwdev);
2039 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
2040 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
2041 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
2042
2043 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
2044 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
2045 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
2046 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
2047 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
2048 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
2049
2050 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
2051 int (*mac_post_init)(struct rtw89_dev *rtwdev);
2052 int (*deinit)(struct rtw89_dev *rtwdev);
2053
2054 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
2055 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
2056 void (*dump_err_status)(struct rtw89_dev *rtwdev);
2057 int (*napi_poll)(struct napi_struct *napi, int budget);
2058
2059 /* Deal with locks inside recovery_start and recovery_complete callbacks
2060 * by hci instance, and handle things which need to consider under SER.
2061 * e.g. turn on/off interrupts except for the one for halt notification.
2062 */
2063 void (*recovery_start)(struct rtw89_dev *rtwdev);
2064 void (*recovery_complete)(struct rtw89_dev *rtwdev);
2065 };
2066
2067 struct rtw89_hci_info {
2068 const struct rtw89_hci_ops *ops;
2069 enum rtw89_hci_type type;
2070 u32 rpwm_addr;
2071 u32 cpwm_addr;
2072 bool paused;
2073 };
2074
2075 struct rtw89_chip_ops {
2076 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
2077 void (*disable_bb_rf)(struct rtw89_dev *rtwdev);
2078 void (*bb_reset)(struct rtw89_dev *rtwdev,
2079 enum rtw89_phy_idx phy_idx);
2080 void (*bb_sethw)(struct rtw89_dev *rtwdev);
2081 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
2082 u32 addr, u32 mask);
2083 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
2084 u32 addr, u32 mask, u32 data);
2085 void (*set_channel)(struct rtw89_dev *rtwdev,
2086 struct rtw89_channel_params *param);
2087 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
2088 struct rtw89_channel_help_params *p);
2089 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map);
2090 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
2091 void (*fem_setup)(struct rtw89_dev *rtwdev);
2092 void (*rfk_init)(struct rtw89_dev *rtwdev);
2093 void (*rfk_channel)(struct rtw89_dev *rtwdev);
2094 void (*rfk_band_changed)(struct rtw89_dev *rtwdev);
2095 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
2096 void (*rfk_track)(struct rtw89_dev *rtwdev);
2097 void (*power_trim)(struct rtw89_dev *rtwdev);
2098 void (*set_txpwr)(struct rtw89_dev *rtwdev);
2099 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev);
2100 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
2101 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
2102 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg);
2103 void (*query_ppdu)(struct rtw89_dev *rtwdev,
2104 struct rtw89_rx_phy_ppdu *phy_ppdu,
2105 struct ieee80211_rx_status *status);
2106 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en);
2107 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
2108 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
2109 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
2110 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
2111 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
2112 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
2113 struct rtw89_tx_desc_info *desc_info,
2114 void *txdesc);
2115 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
2116 struct rtw89_tx_desc_info *desc_info,
2117 void *txdesc);
2118 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
2119 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
2120 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
2121 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
2122 u32 *tx_en, enum rtw89_sch_tx_sel sel);
2123 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
2124 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
2125 struct rtw89_vif *rtwvif,
2126 struct rtw89_sta *rtwsta);
2127
2128 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
2129 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
2130 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
2131 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
2132 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
2133 void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev);
2134 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
2135 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
2136 };
2137
2138 enum rtw89_dma_ch {
2139 RTW89_DMA_ACH0 = 0,
2140 RTW89_DMA_ACH1 = 1,
2141 RTW89_DMA_ACH2 = 2,
2142 RTW89_DMA_ACH3 = 3,
2143 RTW89_DMA_ACH4 = 4,
2144 RTW89_DMA_ACH5 = 5,
2145 RTW89_DMA_ACH6 = 6,
2146 RTW89_DMA_ACH7 = 7,
2147 RTW89_DMA_B0MG = 8,
2148 RTW89_DMA_B0HI = 9,
2149 RTW89_DMA_B1MG = 10,
2150 RTW89_DMA_B1HI = 11,
2151 RTW89_DMA_H2C = 12,
2152 RTW89_DMA_CH_NUM = 13
2153 };
2154
2155 enum rtw89_qta_mode {
2156 RTW89_QTA_SCC,
2157 RTW89_QTA_DLFW,
2158
2159 /* keep last */
2160 RTW89_QTA_INVALID,
2161 };
2162
2163 struct rtw89_hfc_ch_cfg {
2164 u16 min;
2165 u16 max;
2166 #define grp_0 0
2167 #define grp_1 1
2168 #define grp_num 2
2169 u8 grp;
2170 };
2171
2172 struct rtw89_hfc_ch_info {
2173 u16 aval;
2174 u16 used;
2175 };
2176
2177 struct rtw89_hfc_pub_cfg {
2178 u16 grp0;
2179 u16 grp1;
2180 u16 pub_max;
2181 u16 wp_thrd;
2182 };
2183
2184 struct rtw89_hfc_pub_info {
2185 u16 g0_used;
2186 u16 g1_used;
2187 u16 g0_aval;
2188 u16 g1_aval;
2189 u16 pub_aval;
2190 u16 wp_aval;
2191 };
2192
2193 struct rtw89_hfc_prec_cfg {
2194 u16 ch011_prec;
2195 u16 h2c_prec;
2196 u16 wp_ch07_prec;
2197 u16 wp_ch811_prec;
2198 u8 ch011_full_cond;
2199 u8 h2c_full_cond;
2200 u8 wp_ch07_full_cond;
2201 u8 wp_ch811_full_cond;
2202 };
2203
2204 struct rtw89_hfc_param {
2205 bool en;
2206 bool h2c_en;
2207 u8 mode;
2208 const struct rtw89_hfc_ch_cfg *ch_cfg;
2209 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
2210 struct rtw89_hfc_pub_cfg pub_cfg;
2211 struct rtw89_hfc_pub_info pub_info;
2212 struct rtw89_hfc_prec_cfg prec_cfg;
2213 };
2214
2215 struct rtw89_hfc_param_ini {
2216 const struct rtw89_hfc_ch_cfg *ch_cfg;
2217 const struct rtw89_hfc_pub_cfg *pub_cfg;
2218 const struct rtw89_hfc_prec_cfg *prec_cfg;
2219 u8 mode;
2220 };
2221
2222 struct rtw89_dle_size {
2223 u16 pge_size;
2224 u16 lnk_pge_num;
2225 u16 unlnk_pge_num;
2226 };
2227
2228 struct rtw89_wde_quota {
2229 u16 hif;
2230 u16 wcpu;
2231 u16 pkt_in;
2232 u16 cpu_io;
2233 };
2234
2235 struct rtw89_ple_quota {
2236 u16 cma0_tx;
2237 u16 cma1_tx;
2238 u16 c2h;
2239 u16 h2c;
2240 u16 wcpu;
2241 u16 mpdu_proc;
2242 u16 cma0_dma;
2243 u16 cma1_dma;
2244 u16 bb_rpt;
2245 u16 wd_rel;
2246 u16 cpu_io;
2247 u16 tx_rpt;
2248 };
2249
2250 struct rtw89_dle_mem {
2251 enum rtw89_qta_mode mode;
2252 const struct rtw89_dle_size *wde_size;
2253 const struct rtw89_dle_size *ple_size;
2254 const struct rtw89_wde_quota *wde_min_qt;
2255 const struct rtw89_wde_quota *wde_max_qt;
2256 const struct rtw89_ple_quota *ple_min_qt;
2257 const struct rtw89_ple_quota *ple_max_qt;
2258 };
2259
2260 struct rtw89_reg_def {
2261 u32 addr;
2262 u32 mask;
2263 };
2264
2265 struct rtw89_reg2_def {
2266 u32 addr;
2267 u32 data;
2268 };
2269
2270 struct rtw89_reg3_def {
2271 u32 addr;
2272 u32 mask;
2273 u32 data;
2274 };
2275
2276 struct rtw89_reg5_def {
2277 u8 flag; /* recognized by parsers */
2278 u8 path;
2279 u32 addr;
2280 u32 mask;
2281 u32 data;
2282 };
2283
2284 struct rtw89_phy_table {
2285 const struct rtw89_reg2_def *regs;
2286 u32 n_regs;
2287 enum rtw89_rf_path rf_path;
2288 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
2289 enum rtw89_rf_path rf_path, void *data);
2290 };
2291
2292 struct rtw89_txpwr_table {
2293 const void *data;
2294 u32 size;
2295 void (*load)(struct rtw89_dev *rtwdev,
2296 const struct rtw89_txpwr_table *tbl);
2297 };
2298
2299 struct rtw89_page_regs {
2300 u32 hci_fc_ctrl;
2301 u32 ch_page_ctrl;
2302 u32 ach_page_ctrl;
2303 u32 ach_page_info;
2304 u32 pub_page_info3;
2305 u32 pub_page_ctrl1;
2306 u32 pub_page_ctrl2;
2307 u32 pub_page_info1;
2308 u32 pub_page_info2;
2309 u32 wp_page_ctrl1;
2310 u32 wp_page_ctrl2;
2311 u32 wp_page_info1;
2312 };
2313
2314 struct rtw89_imr_info {
2315 u32 wdrls_imr_set;
2316 u32 wsec_imr_reg;
2317 u32 wsec_imr_set;
2318 u32 mpdu_tx_imr_set;
2319 u32 mpdu_rx_imr_set;
2320 u32 sta_sch_imr_set;
2321 u32 txpktctl_imr_b0_reg;
2322 u32 txpktctl_imr_b0_clr;
2323 u32 txpktctl_imr_b0_set;
2324 u32 txpktctl_imr_b1_reg;
2325 u32 txpktctl_imr_b1_clr;
2326 u32 txpktctl_imr_b1_set;
2327 u32 wde_imr_clr;
2328 u32 wde_imr_set;
2329 u32 ple_imr_clr;
2330 u32 ple_imr_set;
2331 u32 host_disp_imr_clr;
2332 u32 host_disp_imr_set;
2333 u32 cpu_disp_imr_clr;
2334 u32 cpu_disp_imr_set;
2335 u32 other_disp_imr_clr;
2336 u32 other_disp_imr_set;
2337 u32 bbrpt_chinfo_err_imr_reg;
2338 u32 bbrpt_err_imr_set;
2339 u32 bbrpt_dfs_err_imr_reg;
2340 u32 ptcl_imr_clr;
2341 u32 ptcl_imr_set;
2342 u32 cdma_imr_0_reg;
2343 u32 cdma_imr_0_clr;
2344 u32 cdma_imr_0_set;
2345 u32 cdma_imr_1_reg;
2346 u32 cdma_imr_1_clr;
2347 u32 cdma_imr_1_set;
2348 u32 phy_intf_imr_reg;
2349 u32 phy_intf_imr_clr;
2350 u32 phy_intf_imr_set;
2351 u32 rmac_imr_reg;
2352 u32 rmac_imr_clr;
2353 u32 rmac_imr_set;
2354 u32 tmac_imr_reg;
2355 u32 tmac_imr_clr;
2356 u32 tmac_imr_set;
2357 };
2358
2359 struct rtw89_chip_info {
2360 enum rtw89_core_chip_id chip_id;
2361 const struct rtw89_chip_ops *ops;
2362 const char *fw_name;
2363 u32 fifo_size;
2364 u16 max_amsdu_limit;
2365 bool dis_2g_40m_ul_ofdma;
2366 u32 rsvd_ple_ofst;
2367 const struct rtw89_hfc_param_ini *hfc_param_ini;
2368 const struct rtw89_dle_mem *dle_mem;
2369 u32 rf_base_addr[2];
2370 u8 support_bands;
2371 bool support_bw160;
2372 bool hw_sec_hdr;
2373 u8 rf_path_num;
2374 u8 tx_nss;
2375 u8 rx_nss;
2376 u8 acam_num;
2377 u8 bcam_num;
2378 u8 scam_num;
2379
2380 u8 sec_ctrl_efuse_size;
2381 u32 physical_efuse_size;
2382 u32 logical_efuse_size;
2383 u32 limit_efuse_size;
2384 u32 dav_phy_efuse_size;
2385 u32 dav_log_efuse_size;
2386 u32 phycap_addr;
2387 u32 phycap_size;
2388
2389 const struct rtw89_pwr_cfg * const *pwr_on_seq;
2390 const struct rtw89_pwr_cfg * const *pwr_off_seq;
2391 const struct rtw89_phy_table *bb_table;
2392 const struct rtw89_phy_table *bb_gain_table;
2393 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
2394 const struct rtw89_phy_table *nctl_table;
2395 const struct rtw89_txpwr_table *byr_table;
2396 const struct rtw89_phy_dig_gain_table *dig_table;
2397 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
2398 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
2399 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2400 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
2401 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
2402 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2403 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
2404 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
2405 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2406 [RTW89_REGD_NUM][RTW89_6G_CH_NUM];
2407 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2408 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
2409 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2410 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
2411 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2412 [RTW89_REGD_NUM][RTW89_6G_CH_NUM];
2413
2414 u8 txpwr_factor_rf;
2415 u8 txpwr_factor_mac;
2416
2417 u32 para_ver;
2418 u32 wlcx_desired;
2419 u8 btcx_desired;
2420 u8 scbd;
2421 u8 mailbox;
2422
2423 u8 afh_guard_ch;
2424 const u8 *wl_rssi_thres;
2425 const u8 *bt_rssi_thres;
2426 u8 rssi_tol;
2427
2428 u8 mon_reg_num;
2429 const struct rtw89_btc_fbtc_mreg *mon_reg;
2430 u8 rf_para_ulink_num;
2431 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
2432 u8 rf_para_dlink_num;
2433 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
2434 u8 ps_mode_supported;
2435 u8 low_power_hci_modes;
2436
2437 u32 h2c_cctl_func_id;
2438 u32 hci_func_en_addr;
2439 u32 h2c_desc_size;
2440 u32 txwd_body_size;
2441 u32 h2c_ctrl_reg;
2442 const u32 *h2c_regs;
2443 u32 c2h_ctrl_reg;
2444 const u32 *c2h_regs;
2445 const struct rtw89_page_regs *page_regs;
2446 const struct rtw89_reg_def *dcfo_comp;
2447 u8 dcfo_comp_sft;
2448 const struct rtw89_imr_info *imr_info;
2449 };
2450
2451 union rtw89_bus_info {
2452 const struct rtw89_pci_info *pci;
2453 };
2454
2455 struct rtw89_driver_info {
2456 const struct rtw89_chip_info *chip;
2457 union rtw89_bus_info bus;
2458 };
2459
2460 enum rtw89_hcifc_mode {
2461 RTW89_HCIFC_POH = 0,
2462 RTW89_HCIFC_STF = 1,
2463 RTW89_HCIFC_SDIO = 2,
2464
2465 /* keep last */
2466 RTW89_HCIFC_MODE_INVALID,
2467 };
2468
2469 struct rtw89_dle_info {
2470 enum rtw89_qta_mode qta_mode;
2471 u16 wde_pg_size;
2472 u16 ple_pg_size;
2473 u16 c0_rx_qta;
2474 u16 c1_rx_qta;
2475 };
2476
2477 enum rtw89_host_rpr_mode {
2478 RTW89_RPR_MODE_POH = 0,
2479 RTW89_RPR_MODE_STF
2480 };
2481
2482 struct rtw89_mac_info {
2483 struct rtw89_dle_info dle_info;
2484 struct rtw89_hfc_param hfc_param;
2485 enum rtw89_qta_mode qta_mode;
2486 u8 rpwm_seq_num;
2487 u8 cpwm_seq_num;
2488 };
2489
2490 enum rtw89_fw_type {
2491 RTW89_FW_NORMAL = 1,
2492 RTW89_FW_WOWLAN = 3,
2493 };
2494
2495 enum rtw89_fw_feature {
2496 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
2497 RTW89_FW_FEATURE_SCAN_OFFLOAD,
2498 RTW89_FW_FEATURE_TX_WAKE,
2499 RTW89_FW_FEATURE_CRASH_TRIGGER,
2500 };
2501
2502 struct rtw89_fw_suit {
2503 const u8 *data;
2504 u32 size;
2505 u8 major_ver;
2506 u8 minor_ver;
2507 u8 sub_ver;
2508 u8 sub_idex;
2509 u16 build_year;
2510 u16 build_mon;
2511 u16 build_date;
2512 u16 build_hour;
2513 u16 build_min;
2514 u8 cmd_ver;
2515 };
2516
2517 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \
2518 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
2519 #define RTW89_FW_SUIT_VER_CODE(s) \
2520 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
2521
2522 struct rtw89_fw_info {
2523 const struct firmware *firmware;
2524 struct rtw89_dev *rtwdev;
2525 struct completion completion;
2526 u8 h2c_seq;
2527 u8 rec_seq;
2528 struct rtw89_fw_suit normal;
2529 struct rtw89_fw_suit wowlan;
2530 bool fw_log_enable;
2531 u32 feature_map;
2532 };
2533
2534 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
2535 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
2536
2537 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
2538 ((_fw)->feature_map |= BIT(_fw_feature))
2539
2540 struct rtw89_cam_info {
2541 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
2542 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
2543 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
2544 };
2545
2546 enum rtw89_sar_sources {
2547 RTW89_SAR_SOURCE_NONE,
2548 RTW89_SAR_SOURCE_COMMON,
2549
2550 RTW89_SAR_SOURCE_NR,
2551 };
2552
2553 struct rtw89_sar_cfg_common {
2554 bool set[RTW89_SUBBAND_NR];
2555 s32 cfg[RTW89_SUBBAND_NR];
2556 };
2557
2558 struct rtw89_sar_info {
2559 /* used to decide how to acces SAR cfg union */
2560 enum rtw89_sar_sources src;
2561
2562 /* reserved for different knids of SAR cfg struct.
2563 * supposed that a single cfg struct cannot handle various SAR sources.
2564 */
2565 union {
2566 struct rtw89_sar_cfg_common cfg_common;
2567 };
2568 };
2569
2570 struct rtw89_hal {
2571 u32 rx_fltr;
2572 u8 cv;
2573 u8 current_channel;
2574 u32 current_freq;
2575 u8 prev_primary_channel;
2576 u8 current_primary_channel;
2577 enum rtw89_subband current_subband;
2578 u8 current_band_width;
2579 u8 prev_band_type;
2580 u8 current_band_type;
2581 u32 sw_amsdu_max_size;
2582 u32 antenna_tx;
2583 u32 antenna_rx;
2584 u8 tx_nss;
2585 u8 rx_nss;
2586 bool support_cckpd;
2587 bool support_igi;
2588 };
2589
2590 #define RTW89_MAX_MAC_ID_NUM 128
2591 #define RTW89_MAX_PKT_OFLD_NUM 255
2592
2593 enum rtw89_flags {
2594 RTW89_FLAG_POWERON,
2595 RTW89_FLAG_FW_RDY,
2596 RTW89_FLAG_RUNNING,
2597 RTW89_FLAG_BFEE_MON,
2598 RTW89_FLAG_BFEE_EN,
2599 RTW89_FLAG_NAPI_RUNNING,
2600 RTW89_FLAG_LEISURE_PS,
2601 RTW89_FLAG_LOW_POWER_MODE,
2602 RTW89_FLAG_INACTIVE_PS,
2603 RTW89_FLAG_RESTART_TRIGGER,
2604
2605 NUM_OF_RTW89_FLAGS,
2606 };
2607
2608 struct rtw89_pkt_stat {
2609 u16 beacon_nr;
2610 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
2611 };
2612
2613 DECLARE_EWMA(thermal, 4, 4);
2614
2615 struct rtw89_phy_stat {
2616 struct ewma_thermal avg_thermal[RF_PATH_MAX];
2617 struct rtw89_pkt_stat cur_pkt_stat;
2618 struct rtw89_pkt_stat last_pkt_stat;
2619 };
2620
2621 #define RTW89_DACK_PATH_NR 2
2622 #define RTW89_DACK_IDX_NR 2
2623 #define RTW89_DACK_MSBK_NR 16
2624 struct rtw89_dack_info {
2625 bool dack_done;
2626 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
2627 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2628 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2629 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2630 u32 dack_cnt;
2631 bool addck_timeout[RTW89_DACK_PATH_NR];
2632 bool dadck_timeout[RTW89_DACK_PATH_NR];
2633 bool msbk_timeout[RTW89_DACK_PATH_NR];
2634 };
2635
2636 #define RTW89_IQK_CHS_NR 2
2637 #define RTW89_IQK_PATH_NR 4
2638
2639 struct rtw89_mcc_info {
2640 u8 ch[RTW89_IQK_CHS_NR];
2641 u8 band[RTW89_IQK_CHS_NR];
2642 u8 table_idx;
2643 };
2644
2645 struct rtw89_lck_info {
2646 u8 thermal[RF_PATH_MAX];
2647 };
2648
2649 struct rtw89_iqk_info {
2650 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2651 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2652 bool lok_fail[RTW89_IQK_PATH_NR];
2653 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2654 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2655 u32 iqk_fail_cnt;
2656 bool is_iqk_init;
2657 u32 iqk_channel[RTW89_IQK_CHS_NR];
2658 u8 iqk_band[RTW89_IQK_PATH_NR];
2659 u8 iqk_ch[RTW89_IQK_PATH_NR];
2660 u8 iqk_bw[RTW89_IQK_PATH_NR];
2661 u8 kcount;
2662 u8 iqk_times;
2663 u8 version;
2664 u32 nb_txcfir[RTW89_IQK_PATH_NR];
2665 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
2666 u32 bp_txkresult[RTW89_IQK_PATH_NR];
2667 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
2668 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
2669 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
2670 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
2671 bool is_nbiqk;
2672 bool iqk_fft_en;
2673 bool iqk_xym_en;
2674 bool iqk_sram_en;
2675 bool iqk_cfir_en;
2676 u8 thermal[RTW89_IQK_PATH_NR];
2677 bool thermal_rek_en;
2678 u32 syn1to2;
2679 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2680 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
2681 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2682 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2683 };
2684
2685 #define RTW89_DPK_RF_PATH 2
2686 #define RTW89_DPK_AVG_THERMAL_NUM 8
2687 #define RTW89_DPK_BKUP_NUM 2
2688 struct rtw89_dpk_bkup_para {
2689 enum rtw89_band band;
2690 enum rtw89_bandwidth bw;
2691 u8 ch;
2692 bool path_ok;
2693 u8 mdpd_en;
2694 u8 txagc_dpk;
2695 u8 ther_dpk;
2696 u8 gs;
2697 u16 pwsf;
2698 };
2699
2700 struct rtw89_dpk_info {
2701 bool is_dpk_enable;
2702 bool is_dpk_reload_en;
2703 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
2704 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
2705 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
2706 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
2707 u8 cur_idx[RTW89_DPK_RF_PATH];
2708 u8 cur_k_set;
2709 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
2710 };
2711
2712 struct rtw89_fem_info {
2713 bool elna_2g;
2714 bool elna_5g;
2715 bool epa_2g;
2716 bool epa_5g;
2717 bool epa_6g;
2718 };
2719
2720 struct rtw89_phy_ch_info {
2721 u8 rssi_min;
2722 u16 rssi_min_macid;
2723 u8 pre_rssi_min;
2724 u8 rssi_max;
2725 u16 rssi_max_macid;
2726 u8 rxsc_160;
2727 u8 rxsc_80;
2728 u8 rxsc_40;
2729 u8 rxsc_20;
2730 u8 rxsc_l;
2731 u8 is_noisy;
2732 };
2733
2734 struct rtw89_agc_gaincode_set {
2735 u8 lna_idx;
2736 u8 tia_idx;
2737 u8 rxb_idx;
2738 };
2739
2740 #define IGI_RSSI_TH_NUM 5
2741 #define FA_TH_NUM 4
2742 #define LNA_GAIN_NUM 7
2743 #define TIA_GAIN_NUM 2
2744 struct rtw89_dig_info {
2745 struct rtw89_agc_gaincode_set cur_gaincode;
2746 bool force_gaincode_idx_en;
2747 struct rtw89_agc_gaincode_set force_gaincode;
2748 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
2749 u16 fa_th[FA_TH_NUM];
2750 u8 igi_rssi;
2751 u8 igi_fa_rssi;
2752 u8 fa_rssi_ofst;
2753 u8 dyn_igi_max;
2754 u8 dyn_igi_min;
2755 bool dyn_pd_th_en;
2756 u8 dyn_pd_th_max;
2757 u8 pd_low_th_ofst;
2758 u8 ib_pbk;
2759 s8 ib_pkpwr;
2760 s8 lna_gain_a[LNA_GAIN_NUM];
2761 s8 lna_gain_g[LNA_GAIN_NUM];
2762 s8 *lna_gain;
2763 s8 tia_gain_a[TIA_GAIN_NUM];
2764 s8 tia_gain_g[TIA_GAIN_NUM];
2765 s8 *tia_gain;
2766 bool is_linked_pre;
2767 bool bypass_dig;
2768 };
2769
2770 enum rtw89_multi_cfo_mode {
2771 RTW89_PKT_BASED_AVG_MODE = 0,
2772 RTW89_ENTRY_BASED_AVG_MODE = 1,
2773 RTW89_TP_BASED_AVG_MODE = 2,
2774 };
2775
2776 enum rtw89_phy_cfo_status {
2777 RTW89_PHY_DCFO_STATE_NORMAL = 0,
2778 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
2779 RTW89_PHY_DCFO_STATE_MAX
2780 };
2781
2782 struct rtw89_cfo_tracking_info {
2783 u16 cfo_timer_ms;
2784 bool cfo_trig_by_timer_en;
2785 enum rtw89_phy_cfo_status phy_cfo_status;
2786 u8 phy_cfo_trk_cnt;
2787 bool is_adjust;
2788 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
2789 bool apply_compensation;
2790 u8 crystal_cap;
2791 u8 crystal_cap_default;
2792 u8 def_x_cap;
2793 s8 x_cap_ofst;
2794 u32 sta_cfo_tolerance;
2795 s32 cfo_tail[CFO_TRACK_MAX_USER];
2796 u16 cfo_cnt[CFO_TRACK_MAX_USER];
2797 s32 cfo_avg_pre;
2798 s32 cfo_avg[CFO_TRACK_MAX_USER];
2799 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
2800 u32 packet_count;
2801 u32 packet_count_pre;
2802 s32 residual_cfo_acc;
2803 u8 phy_cfotrk_state;
2804 u8 phy_cfotrk_cnt;
2805 bool divergence_lock_en;
2806 u8 x_cap_lb;
2807 u8 x_cap_ub;
2808 u8 lock_cnt;
2809 };
2810
2811 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
2812 #define TSSI_TRIM_CH_GROUP_NUM 8
2813 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
2814
2815 #define TSSI_CCK_CH_GROUP_NUM 6
2816 #define TSSI_MCS_2G_CH_GROUP_NUM 5
2817 #define TSSI_MCS_5G_CH_GROUP_NUM 14
2818 #define TSSI_MCS_6G_CH_GROUP_NUM 32
2819 #define TSSI_MCS_CH_GROUP_NUM \
2820 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
2821
2822 struct rtw89_tssi_info {
2823 u8 thermal[RF_PATH_MAX];
2824 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
2825 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
2826 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
2827 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
2828 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
2829 s8 extra_ofst[RF_PATH_MAX];
2830 bool tssi_tracking_check[RF_PATH_MAX];
2831 u8 default_txagc_offset[RF_PATH_MAX];
2832 u32 base_thermal[RF_PATH_MAX];
2833 };
2834
2835 struct rtw89_power_trim_info {
2836 bool pg_thermal_trim;
2837 bool pg_pa_bias_trim;
2838 u8 thermal_trim[RF_PATH_MAX];
2839 u8 pa_bias_trim[RF_PATH_MAX];
2840 };
2841
2842 struct rtw89_regulatory {
2843 char alpha2[3];
2844 u8 txpwr_regd[RTW89_BAND_MAX];
2845 };
2846
2847 enum rtw89_ifs_clm_application {
2848 RTW89_IFS_CLM_INIT = 0,
2849 RTW89_IFS_CLM_BACKGROUND = 1,
2850 RTW89_IFS_CLM_ACS = 2,
2851 RTW89_IFS_CLM_DIG = 3,
2852 RTW89_IFS_CLM_TDMA_DIG = 4,
2853 RTW89_IFS_CLM_DBG = 5,
2854 RTW89_IFS_CLM_DBG_MANUAL = 6
2855 };
2856
2857 enum rtw89_env_racing_lv {
2858 RTW89_RAC_RELEASE = 0,
2859 RTW89_RAC_LV_1 = 1,
2860 RTW89_RAC_LV_2 = 2,
2861 RTW89_RAC_LV_3 = 3,
2862 RTW89_RAC_LV_4 = 4,
2863 RTW89_RAC_MAX_NUM = 5
2864 };
2865
2866 struct rtw89_ccx_para_info {
2867 enum rtw89_env_racing_lv rac_lv;
2868 u16 mntr_time;
2869 u8 nhm_manual_th_ofst;
2870 u8 nhm_manual_th0;
2871 enum rtw89_ifs_clm_application ifs_clm_app;
2872 u32 ifs_clm_manual_th_times;
2873 u32 ifs_clm_manual_th0;
2874 u8 fahm_manual_th_ofst;
2875 u8 fahm_manual_th0;
2876 u8 fahm_numer_opt;
2877 u8 fahm_denom_opt;
2878 };
2879
2880 enum rtw89_ccx_edcca_opt_sc_idx {
2881 RTW89_CCX_EDCCA_SEG0_P0 = 0,
2882 RTW89_CCX_EDCCA_SEG0_S1 = 1,
2883 RTW89_CCX_EDCCA_SEG0_S2 = 2,
2884 RTW89_CCX_EDCCA_SEG0_S3 = 3,
2885 RTW89_CCX_EDCCA_SEG1_P0 = 4,
2886 RTW89_CCX_EDCCA_SEG1_S1 = 5,
2887 RTW89_CCX_EDCCA_SEG1_S2 = 6,
2888 RTW89_CCX_EDCCA_SEG1_S3 = 7
2889 };
2890
2891 enum rtw89_ccx_edcca_opt_bw_idx {
2892 RTW89_CCX_EDCCA_BW20_0 = 0,
2893 RTW89_CCX_EDCCA_BW20_1 = 1,
2894 RTW89_CCX_EDCCA_BW20_2 = 2,
2895 RTW89_CCX_EDCCA_BW20_3 = 3,
2896 RTW89_CCX_EDCCA_BW20_4 = 4,
2897 RTW89_CCX_EDCCA_BW20_5 = 5,
2898 RTW89_CCX_EDCCA_BW20_6 = 6,
2899 RTW89_CCX_EDCCA_BW20_7 = 7
2900 };
2901
2902 #define RTW89_NHM_TH_NUM 11
2903 #define RTW89_FAHM_TH_NUM 11
2904 #define RTW89_NHM_RPT_NUM 12
2905 #define RTW89_FAHM_RPT_NUM 12
2906 #define RTW89_IFS_CLM_NUM 4
2907 struct rtw89_env_monitor_info {
2908 u32 ccx_trigger_time;
2909 u64 start_time;
2910 u8 ccx_rpt_stamp;
2911 u8 ccx_watchdog_result;
2912 bool ccx_ongoing;
2913 u8 ccx_rac_lv;
2914 bool ccx_manual_ctrl;
2915 u8 ccx_pre_rssi;
2916 u16 clm_mntr_time;
2917 u16 nhm_mntr_time;
2918 u16 ifs_clm_mntr_time;
2919 enum rtw89_ifs_clm_application ifs_clm_app;
2920 u16 fahm_mntr_time;
2921 u16 edcca_clm_mntr_time;
2922 u16 ccx_period;
2923 u8 ccx_unit_idx;
2924 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx;
2925 u8 nhm_th[RTW89_NHM_TH_NUM];
2926 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
2927 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
2928 u8 fahm_numer_opt;
2929 u8 fahm_denom_opt;
2930 u8 fahm_th[RTW89_FAHM_TH_NUM];
2931 u16 clm_result;
2932 u16 nhm_result[RTW89_NHM_RPT_NUM];
2933 u8 nhm_wgt[RTW89_NHM_RPT_NUM];
2934 u16 nhm_tx_cnt;
2935 u16 nhm_cca_cnt;
2936 u16 nhm_idle_cnt;
2937 u16 ifs_clm_tx;
2938 u16 ifs_clm_edcca_excl_cca;
2939 u16 ifs_clm_ofdmfa;
2940 u16 ifs_clm_ofdmcca_excl_fa;
2941 u16 ifs_clm_cckfa;
2942 u16 ifs_clm_cckcca_excl_fa;
2943 u16 ifs_clm_total_ifs;
2944 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
2945 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
2946 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
2947 u16 fahm_result[RTW89_FAHM_RPT_NUM];
2948 u16 fahm_denom_result;
2949 u16 edcca_clm_result;
2950 u8 clm_ratio;
2951 u8 nhm_rpt[RTW89_NHM_RPT_NUM];
2952 u8 nhm_tx_ratio;
2953 u8 nhm_cca_ratio;
2954 u8 nhm_idle_ratio;
2955 u8 nhm_ratio;
2956 u16 nhm_result_sum;
2957 u8 nhm_pwr;
2958 u8 ifs_clm_tx_ratio;
2959 u8 ifs_clm_edcca_excl_cca_ratio;
2960 u8 ifs_clm_cck_fa_ratio;
2961 u8 ifs_clm_ofdm_fa_ratio;
2962 u8 ifs_clm_cck_cca_excl_fa_ratio;
2963 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
2964 u16 ifs_clm_cck_fa_permil;
2965 u16 ifs_clm_ofdm_fa_permil;
2966 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
2967 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
2968 u8 fahm_rpt[RTW89_FAHM_RPT_NUM];
2969 u16 fahm_result_sum;
2970 u8 fahm_ratio;
2971 u8 fahm_denom_ratio;
2972 u8 fahm_pwr;
2973 u8 edcca_clm_ratio;
2974 };
2975
2976 enum rtw89_ser_rcvy_step {
2977 RTW89_SER_DRV_STOP_TX,
2978 RTW89_SER_DRV_STOP_RX,
2979 RTW89_SER_DRV_STOP_RUN,
2980 RTW89_SER_HAL_STOP_DMA,
2981 RTW89_NUM_OF_SER_FLAGS
2982 };
2983
2984 struct rtw89_ser {
2985 u8 state;
2986 u8 alarm_event;
2987
2988 struct work_struct ser_hdl_work;
2989 struct delayed_work ser_alarm_work;
2990 const struct state_ent *st_tbl;
2991 const struct event_ent *ev_tbl;
2992 struct list_head msg_q;
2993 spinlock_t msg_q_lock; /* lock when read/write ser msg */
2994 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
2995 };
2996
2997 enum rtw89_mac_ax_ps_mode {
2998 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
2999 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
3000 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
3001 RTW89_MAC_AX_PS_MODE_MAX = 3,
3002 };
3003
3004 enum rtw89_last_rpwm_mode {
3005 RTW89_LAST_RPWM_PS = 0x0,
3006 RTW89_LAST_RPWM_ACTIVE = 0x6,
3007 };
3008
3009 struct rtw89_lps_parm {
3010 u8 macid;
3011 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
3012 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
3013 };
3014
3015 struct rtw89_ppdu_sts_info {
3016 struct sk_buff_head rx_queue[RTW89_PHY_MAX];
3017 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
3018 };
3019
3020 struct rtw89_early_h2c {
3021 struct list_head list;
3022 u8 *h2c;
3023 u16 h2c_len;
3024 };
3025
3026 struct rtw89_hw_scan_info {
3027 struct ieee80211_vif *scanning_vif;
3028 struct list_head pkt_list[NUM_NL80211_BANDS];
3029 u8 op_pri_ch;
3030 u8 op_chan;
3031 u8 op_bw;
3032 u8 op_band;
3033 };
3034
3035 enum rtw89_phy_bb_gain_band {
3036 RTW89_BB_GAIN_BAND_2G = 0,
3037 RTW89_BB_GAIN_BAND_5G_L = 1,
3038 RTW89_BB_GAIN_BAND_5G_M = 2,
3039 RTW89_BB_GAIN_BAND_5G_H = 3,
3040 RTW89_BB_GAIN_BAND_6G_L = 4,
3041 RTW89_BB_GAIN_BAND_6G_M = 5,
3042 RTW89_BB_GAIN_BAND_6G_H = 6,
3043 RTW89_BB_GAIN_BAND_6G_UH = 7,
3044
3045 RTW89_BB_GAIN_BAND_NR,
3046 };
3047
3048 enum rtw89_phy_bb_rxsc_num {
3049 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
3050 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
3051 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
3052 };
3053
3054 struct rtw89_phy_bb_gain_info {
3055 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3056 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
3057 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3058 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3059 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3060 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
3061 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
3062 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3063 [RTW89_BB_RXSC_NUM_40];
3064 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3065 [RTW89_BB_RXSC_NUM_80];
3066 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3067 [RTW89_BB_RXSC_NUM_160];
3068 };
3069
3070 struct rtw89_phy_efuse_gain {
3071 bool offset_valid;
3072 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
3073 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
3074 };
3075
3076 struct rtw89_dev {
3077 struct ieee80211_hw *hw;
3078 struct device *dev;
3079
3080 bool dbcc_en;
3081 struct rtw89_hw_scan_info scan_info;
3082 const struct rtw89_chip_info *chip;
3083 const struct rtw89_pci_info *pci_info;
3084 struct rtw89_hal hal;
3085 struct rtw89_mac_info mac;
3086 struct rtw89_fw_info fw;
3087 struct rtw89_hci_info hci;
3088 struct rtw89_efuse efuse;
3089 struct rtw89_traffic_stats stats;
3090
3091 /* ensures exclusive access from mac80211 callbacks */
3092 struct mutex mutex;
3093 struct list_head rtwvifs_list;
3094 /* used to protect rf read write */
3095 struct mutex rf_mutex;
3096 struct workqueue_struct *txq_wq;
3097 struct work_struct txq_work;
3098 struct delayed_work txq_reinvoke_work;
3099 /* used to protect ba_list */
3100 spinlock_t ba_lock;
3101 /* txqs to setup ba session */
3102 struct list_head ba_list;
3103 struct work_struct ba_work;
3104 /* used to protect rpwm */
3105 spinlock_t rpwm_lock;
3106
3107 struct rtw89_cam_info cam_info;
3108
3109 struct sk_buff_head c2h_queue;
3110 struct work_struct c2h_work;
3111 struct work_struct ips_work;
3112
3113 struct list_head early_h2c_list;
3114
3115 struct rtw89_ser ser;
3116
3117 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
3118 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
3119 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
3120 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
3121
3122 struct rtw89_phy_stat phystat;
3123 struct rtw89_dack_info dack;
3124 struct rtw89_iqk_info iqk;
3125 struct rtw89_dpk_info dpk;
3126 struct rtw89_mcc_info mcc;
3127 struct rtw89_lck_info lck;
3128 bool is_tssi_mode[RF_PATH_MAX];
3129 bool is_bt_iqk_timeout;
3130
3131 struct rtw89_fem_info fem;
3132 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX];
3133 struct rtw89_tssi_info tssi;
3134 struct rtw89_power_trim_info pwr_trim;
3135
3136 struct rtw89_cfo_tracking_info cfo_tracking;
3137 struct rtw89_env_monitor_info env_monitor;
3138 struct rtw89_dig_info dig;
3139 struct rtw89_phy_ch_info ch_info;
3140 struct rtw89_phy_bb_gain_info bb_gain;
3141 struct rtw89_phy_efuse_gain efuse_gain;
3142
3143 struct delayed_work track_work;
3144 struct delayed_work coex_act1_work;
3145 struct delayed_work coex_bt_devinfo_work;
3146 struct delayed_work coex_rfk_chk_work;
3147 struct delayed_work cfo_track_work;
3148 struct rtw89_ppdu_sts_info ppdu_sts;
3149 u8 total_sta_assoc;
3150 bool scanning;
3151
3152 const struct rtw89_regulatory *regd;
3153 struct rtw89_sar_info sar;
3154
3155 struct rtw89_btc btc;
3156 enum rtw89_ps_mode ps_mode;
3157 bool lps_enabled;
3158
3159 /* napi structure */
3160 struct net_device netdev;
3161 struct napi_struct napi;
3162 int napi_budget_countdown;
3163
3164 /* HCI related data, keep last */
3165 u8 priv[] __aligned(sizeof(void *));
3166 };
3167
rtw89_hci_tx_write(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)3168 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
3169 struct rtw89_core_tx_request *tx_req)
3170 {
3171 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
3172 }
3173
rtw89_hci_reset(struct rtw89_dev * rtwdev)3174 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
3175 {
3176 rtwdev->hci.ops->reset(rtwdev);
3177 }
3178
rtw89_hci_start(struct rtw89_dev * rtwdev)3179 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
3180 {
3181 return rtwdev->hci.ops->start(rtwdev);
3182 }
3183
rtw89_hci_stop(struct rtw89_dev * rtwdev)3184 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
3185 {
3186 rtwdev->hci.ops->stop(rtwdev);
3187 }
3188
rtw89_hci_deinit(struct rtw89_dev * rtwdev)3189 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
3190 {
3191 return rtwdev->hci.ops->deinit(rtwdev);
3192 }
3193
rtw89_hci_pause(struct rtw89_dev * rtwdev,bool pause)3194 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
3195 {
3196 rtwdev->hci.ops->pause(rtwdev, pause);
3197 }
3198
rtw89_hci_switch_mode(struct rtw89_dev * rtwdev,bool low_power)3199 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
3200 {
3201 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
3202 }
3203
rtw89_hci_recalc_int_mit(struct rtw89_dev * rtwdev)3204 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
3205 {
3206 rtwdev->hci.ops->recalc_int_mit(rtwdev);
3207 }
3208
rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 txch)3209 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
3210 {
3211 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
3212 }
3213
rtw89_hci_tx_kick_off(struct rtw89_dev * rtwdev,u8 txch)3214 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
3215 {
3216 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
3217 }
3218
rtw89_hci_flush_queues(struct rtw89_dev * rtwdev,u32 queues,bool drop)3219 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
3220 bool drop)
3221 {
3222 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
3223 return;
3224
3225 if (rtwdev->hci.ops->flush_queues)
3226 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
3227 }
3228
rtw89_hci_recovery_start(struct rtw89_dev * rtwdev)3229 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
3230 {
3231 if (rtwdev->hci.ops->recovery_start)
3232 rtwdev->hci.ops->recovery_start(rtwdev);
3233 }
3234
rtw89_hci_recovery_complete(struct rtw89_dev * rtwdev)3235 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
3236 {
3237 if (rtwdev->hci.ops->recovery_complete)
3238 rtwdev->hci.ops->recovery_complete(rtwdev);
3239 }
3240
rtw89_read8(struct rtw89_dev * rtwdev,u32 addr)3241 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
3242 {
3243 return rtwdev->hci.ops->read8(rtwdev, addr);
3244 }
3245
rtw89_read16(struct rtw89_dev * rtwdev,u32 addr)3246 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
3247 {
3248 return rtwdev->hci.ops->read16(rtwdev, addr);
3249 }
3250
rtw89_read32(struct rtw89_dev * rtwdev,u32 addr)3251 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
3252 {
3253 return rtwdev->hci.ops->read32(rtwdev, addr);
3254 }
3255
rtw89_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)3256 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
3257 {
3258 rtwdev->hci.ops->write8(rtwdev, addr, data);
3259 }
3260
rtw89_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)3261 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
3262 {
3263 rtwdev->hci.ops->write16(rtwdev, addr, data);
3264 }
3265
rtw89_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)3266 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
3267 {
3268 rtwdev->hci.ops->write32(rtwdev, addr, data);
3269 }
3270
3271 static inline void
rtw89_write8_set(struct rtw89_dev * rtwdev,u32 addr,u8 bit)3272 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
3273 {
3274 u8 val;
3275
3276 val = rtw89_read8(rtwdev, addr);
3277 rtw89_write8(rtwdev, addr, val | bit);
3278 }
3279
3280 static inline void
rtw89_write16_set(struct rtw89_dev * rtwdev,u32 addr,u16 bit)3281 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
3282 {
3283 u16 val;
3284
3285 val = rtw89_read16(rtwdev, addr);
3286 rtw89_write16(rtwdev, addr, val | bit);
3287 }
3288
3289 static inline void
rtw89_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bit)3290 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
3291 {
3292 u32 val;
3293
3294 val = rtw89_read32(rtwdev, addr);
3295 rtw89_write32(rtwdev, addr, val | bit);
3296 }
3297
3298 static inline void
rtw89_write8_clr(struct rtw89_dev * rtwdev,u32 addr,u8 bit)3299 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
3300 {
3301 u8 val;
3302
3303 val = rtw89_read8(rtwdev, addr);
3304 rtw89_write8(rtwdev, addr, val & ~bit);
3305 }
3306
3307 static inline void
rtw89_write16_clr(struct rtw89_dev * rtwdev,u32 addr,u16 bit)3308 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
3309 {
3310 u16 val;
3311
3312 val = rtw89_read16(rtwdev, addr);
3313 rtw89_write16(rtwdev, addr, val & ~bit);
3314 }
3315
3316 static inline void
rtw89_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bit)3317 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
3318 {
3319 u32 val;
3320
3321 val = rtw89_read32(rtwdev, addr);
3322 rtw89_write32(rtwdev, addr, val & ~bit);
3323 }
3324
3325 static inline u32
rtw89_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)3326 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3327 {
3328 u32 shift = __ffs(mask);
3329 u32 orig;
3330 u32 ret;
3331
3332 orig = rtw89_read32(rtwdev, addr);
3333 ret = (orig & mask) >> shift;
3334
3335 return ret;
3336 }
3337
3338 static inline u16
rtw89_read16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)3339 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3340 {
3341 u32 shift = __ffs(mask);
3342 u32 orig;
3343 u32 ret;
3344
3345 orig = rtw89_read16(rtwdev, addr);
3346 ret = (orig & mask) >> shift;
3347
3348 return ret;
3349 }
3350
3351 static inline u8
rtw89_read8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)3352 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3353 {
3354 u32 shift = __ffs(mask);
3355 u32 orig;
3356 u32 ret;
3357
3358 orig = rtw89_read8(rtwdev, addr);
3359 ret = (orig & mask) >> shift;
3360
3361 return ret;
3362 }
3363
3364 static inline void
rtw89_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)3365 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
3366 {
3367 u32 shift = __ffs(mask);
3368 u32 orig;
3369 u32 set;
3370
3371 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
3372
3373 orig = rtw89_read32(rtwdev, addr);
3374 set = (orig & ~mask) | ((data << shift) & mask);
3375 rtw89_write32(rtwdev, addr, set);
3376 }
3377
3378 static inline void
rtw89_write16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u16 data)3379 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
3380 {
3381 u32 shift;
3382 u16 orig, set;
3383
3384 mask &= 0xffff;
3385 shift = __ffs(mask);
3386
3387 orig = rtw89_read16(rtwdev, addr);
3388 set = (orig & ~mask) | ((data << shift) & mask);
3389 rtw89_write16(rtwdev, addr, set);
3390 }
3391
3392 static inline void
rtw89_write8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u8 data)3393 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
3394 {
3395 u32 shift;
3396 u8 orig, set;
3397
3398 mask &= 0xff;
3399 shift = __ffs(mask);
3400
3401 orig = rtw89_read8(rtwdev, addr);
3402 set = (orig & ~mask) | ((data << shift) & mask);
3403 rtw89_write8(rtwdev, addr, set);
3404 }
3405
3406 static inline u32
rtw89_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)3407 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3408 u32 addr, u32 mask)
3409 {
3410 u32 val;
3411
3412 mutex_lock(&rtwdev->rf_mutex);
3413 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
3414 mutex_unlock(&rtwdev->rf_mutex);
3415
3416 return val;
3417 }
3418
3419 static inline void
rtw89_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)3420 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3421 u32 addr, u32 mask, u32 data)
3422 {
3423 mutex_lock(&rtwdev->rf_mutex);
3424 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
3425 mutex_unlock(&rtwdev->rf_mutex);
3426 }
3427
rtw89_txq_to_txq(struct rtw89_txq * rtwtxq)3428 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
3429 {
3430 void *p = rtwtxq;
3431
3432 return container_of(p, struct ieee80211_txq, drv_priv);
3433 }
3434
rtw89_core_txq_init(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq)3435 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
3436 struct ieee80211_txq *txq)
3437 {
3438 struct rtw89_txq *rtwtxq;
3439
3440 if (!txq)
3441 return;
3442
3443 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3444 INIT_LIST_HEAD(&rtwtxq->list);
3445 }
3446
rtwvif_to_vif(struct rtw89_vif * rtwvif)3447 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
3448 {
3449 void *p = rtwvif;
3450
3451 return container_of(p, struct ieee80211_vif, drv_priv);
3452 }
3453
rtwsta_to_sta(struct rtw89_sta * rtwsta)3454 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
3455 {
3456 void *p = rtwsta;
3457
3458 return container_of(p, struct ieee80211_sta, drv_priv);
3459 }
3460
rtwsta_to_sta_safe(struct rtw89_sta * rtwsta)3461 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
3462 {
3463 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
3464 }
3465
sta_to_rtwsta_safe(struct ieee80211_sta * sta)3466 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
3467 {
3468 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
3469 }
3470
rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)3471 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
3472 {
3473 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
3474 return RATE_INFO_BW_160;
3475 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
3476 return RATE_INFO_BW_80;
3477 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
3478 return RATE_INFO_BW_40;
3479 else
3480 return RATE_INFO_BW_20;
3481 }
3482
3483 static inline
rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)3484 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
3485 {
3486 switch (hw_band) {
3487 default:
3488 case RTW89_BAND_2G:
3489 return NL80211_BAND_2GHZ;
3490 case RTW89_BAND_5G:
3491 return NL80211_BAND_5GHZ;
3492 case RTW89_BAND_6G:
3493 return NL80211_BAND_6GHZ;
3494 }
3495 }
3496
3497 static inline
nl_to_rtw89_bandwidth(enum nl80211_chan_width width)3498 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
3499 {
3500 switch (width) {
3501 default:
3502 WARN(1, "Not support bandwidth %d\n", width);
3503 fallthrough;
3504 case NL80211_CHAN_WIDTH_20_NOHT:
3505 case NL80211_CHAN_WIDTH_20:
3506 return RTW89_CHANNEL_WIDTH_20;
3507 case NL80211_CHAN_WIDTH_40:
3508 return RTW89_CHANNEL_WIDTH_40;
3509 case NL80211_CHAN_WIDTH_80:
3510 return RTW89_CHANNEL_WIDTH_80;
3511 case NL80211_CHAN_WIDTH_160:
3512 return RTW89_CHANNEL_WIDTH_160;
3513 }
3514 }
3515
3516 static inline
rtw89_get_addr_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)3517 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
3518 struct rtw89_sta *rtwsta)
3519 {
3520 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE && rtwsta)
3521 return &rtwsta->addr_cam;
3522 return &rtwvif->addr_cam;
3523 }
3524
3525 static inline
rtw89_chip_set_channel_prepare(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p)3526 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
3527 struct rtw89_channel_help_params *p)
3528 {
3529 rtwdev->chip->ops->set_channel_help(rtwdev, true, p);
3530 }
3531
3532 static inline
rtw89_chip_set_channel_done(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p)3533 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
3534 struct rtw89_channel_help_params *p)
3535 {
3536 rtwdev->chip->ops->set_channel_help(rtwdev, false, p);
3537 }
3538
rtw89_chip_fem_setup(struct rtw89_dev * rtwdev)3539 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
3540 {
3541 const struct rtw89_chip_info *chip = rtwdev->chip;
3542
3543 if (chip->ops->fem_setup)
3544 chip->ops->fem_setup(rtwdev);
3545 }
3546
rtw89_chip_bb_sethw(struct rtw89_dev * rtwdev)3547 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
3548 {
3549 const struct rtw89_chip_info *chip = rtwdev->chip;
3550
3551 if (chip->ops->bb_sethw)
3552 chip->ops->bb_sethw(rtwdev);
3553 }
3554
rtw89_chip_rfk_init(struct rtw89_dev * rtwdev)3555 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
3556 {
3557 const struct rtw89_chip_info *chip = rtwdev->chip;
3558
3559 if (chip->ops->rfk_init)
3560 chip->ops->rfk_init(rtwdev);
3561 }
3562
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev)3563 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
3564 {
3565 const struct rtw89_chip_info *chip = rtwdev->chip;
3566
3567 if (chip->ops->rfk_channel)
3568 chip->ops->rfk_channel(rtwdev);
3569 }
3570
rtw89_chip_rfk_band_changed(struct rtw89_dev * rtwdev)3571 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev)
3572 {
3573 const struct rtw89_chip_info *chip = rtwdev->chip;
3574
3575 if (chip->ops->rfk_band_changed)
3576 chip->ops->rfk_band_changed(rtwdev);
3577 }
3578
rtw89_chip_rfk_scan(struct rtw89_dev * rtwdev,bool start)3579 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
3580 {
3581 const struct rtw89_chip_info *chip = rtwdev->chip;
3582
3583 if (chip->ops->rfk_scan)
3584 chip->ops->rfk_scan(rtwdev, start);
3585 }
3586
rtw89_chip_rfk_track(struct rtw89_dev * rtwdev)3587 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
3588 {
3589 const struct rtw89_chip_info *chip = rtwdev->chip;
3590
3591 if (chip->ops->rfk_track)
3592 chip->ops->rfk_track(rtwdev);
3593 }
3594
rtw89_chip_set_txpwr_ctrl(struct rtw89_dev * rtwdev)3595 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
3596 {
3597 const struct rtw89_chip_info *chip = rtwdev->chip;
3598
3599 if (chip->ops->set_txpwr_ctrl)
3600 chip->ops->set_txpwr_ctrl(rtwdev);
3601 }
3602
rtw89_chip_set_txpwr(struct rtw89_dev * rtwdev)3603 static inline void rtw89_chip_set_txpwr(struct rtw89_dev *rtwdev)
3604 {
3605 const struct rtw89_chip_info *chip = rtwdev->chip;
3606 u8 ch = rtwdev->hal.current_channel;
3607
3608 if (!ch)
3609 return;
3610
3611 if (chip->ops->set_txpwr)
3612 chip->ops->set_txpwr(rtwdev);
3613 }
3614
rtw89_chip_power_trim(struct rtw89_dev * rtwdev)3615 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
3616 {
3617 const struct rtw89_chip_info *chip = rtwdev->chip;
3618
3619 if (chip->ops->power_trim)
3620 chip->ops->power_trim(rtwdev);
3621 }
3622
rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)3623 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
3624 enum rtw89_phy_idx phy_idx)
3625 {
3626 const struct rtw89_chip_info *chip = rtwdev->chip;
3627
3628 if (chip->ops->init_txpwr_unit)
3629 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
3630 }
3631
rtw89_chip_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)3632 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
3633 enum rtw89_rf_path rf_path)
3634 {
3635 const struct rtw89_chip_info *chip = rtwdev->chip;
3636
3637 if (!chip->ops->get_thermal)
3638 return 0x10;
3639
3640 return chip->ops->get_thermal(rtwdev, rf_path);
3641 }
3642
rtw89_chip_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)3643 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
3644 struct rtw89_rx_phy_ppdu *phy_ppdu,
3645 struct ieee80211_rx_status *status)
3646 {
3647 const struct rtw89_chip_info *chip = rtwdev->chip;
3648
3649 if (chip->ops->query_ppdu)
3650 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
3651 }
3652
rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev * rtwdev,bool bt_en)3653 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev,
3654 bool bt_en)
3655 {
3656 const struct rtw89_chip_info *chip = rtwdev->chip;
3657
3658 if (chip->ops->bb_ctrl_btc_preagc)
3659 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en);
3660 }
3661
rtw89_chip_cfg_txrx_path(struct rtw89_dev * rtwdev)3662 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
3663 {
3664 const struct rtw89_chip_info *chip = rtwdev->chip;
3665
3666 if (chip->ops->cfg_txrx_path)
3667 chip->ops->cfg_txrx_path(rtwdev);
3668 }
3669
3670 static inline
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)3671 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
3672 struct ieee80211_vif *vif)
3673 {
3674 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3675 const struct rtw89_chip_info *chip = rtwdev->chip;
3676
3677 if (!vif->bss_conf.he_support || !vif->bss_conf.assoc)
3678 return;
3679
3680 if (chip->ops->set_txpwr_ul_tb_offset)
3681 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
3682 }
3683
rtw89_load_txpwr_table(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)3684 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
3685 const struct rtw89_txpwr_table *tbl)
3686 {
3687 tbl->load(rtwdev, tbl);
3688 }
3689
rtw89_regd_get(struct rtw89_dev * rtwdev,u8 band)3690 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
3691 {
3692 return rtwdev->regd->txpwr_regd[band];
3693 }
3694
rtw89_ctrl_btg(struct rtw89_dev * rtwdev,bool btg)3695 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
3696 {
3697 const struct rtw89_chip_info *chip = rtwdev->chip;
3698
3699 if (chip->ops->ctrl_btg)
3700 chip->ops->ctrl_btg(rtwdev, btg);
3701 }
3702
3703 static inline
rtw89_chip_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)3704 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
3705 struct rtw89_tx_desc_info *desc_info,
3706 void *txdesc)
3707 {
3708 const struct rtw89_chip_info *chip = rtwdev->chip;
3709
3710 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
3711 }
3712
3713 static inline
rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)3714 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
3715 struct rtw89_tx_desc_info *desc_info,
3716 void *txdesc)
3717 {
3718 const struct rtw89_chip_info *chip = rtwdev->chip;
3719
3720 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
3721 }
3722
3723 static inline
rtw89_chip_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)3724 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
3725 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
3726 {
3727 const struct rtw89_chip_info *chip = rtwdev->chip;
3728
3729 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
3730 }
3731
rtw89_chip_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)3732 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
3733 {
3734 const struct rtw89_chip_info *chip = rtwdev->chip;
3735
3736 chip->ops->cfg_ctrl_path(rtwdev, wl);
3737 }
3738
3739 static inline
rtw89_chip_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)3740 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
3741 u32 *tx_en, enum rtw89_sch_tx_sel sel)
3742 {
3743 const struct rtw89_chip_info *chip = rtwdev->chip;
3744
3745 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
3746 }
3747
3748 static inline
rtw89_chip_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)3749 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
3750 {
3751 const struct rtw89_chip_info *chip = rtwdev->chip;
3752
3753 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
3754 }
3755
3756 static inline
rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)3757 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
3758 struct rtw89_vif *rtwvif,
3759 struct rtw89_sta *rtwsta)
3760 {
3761 const struct rtw89_chip_info *chip = rtwdev->chip;
3762
3763 if (!chip->ops->h2c_dctl_sec_cam)
3764 return 0;
3765 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
3766 }
3767
get_hdr_bssid(struct ieee80211_hdr * hdr)3768 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
3769 {
3770 __le16 fc = hdr->frame_control;
3771
3772 if (ieee80211_has_tods(fc))
3773 return hdr->addr1;
3774 else if (ieee80211_has_fromds(fc))
3775 return hdr->addr2;
3776 else
3777 return hdr->addr3;
3778 }
3779
rtw89_sta_has_beamformer_cap(struct ieee80211_sta * sta)3780 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
3781 {
3782 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
3783 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
3784 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
3785 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
3786 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] &
3787 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
3788 return true;
3789 return false;
3790 }
3791
rtw89_fw_suit_get(struct rtw89_dev * rtwdev,enum rtw89_fw_type type)3792 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
3793 enum rtw89_fw_type type)
3794 {
3795 struct rtw89_fw_info *fw_info = &rtwdev->fw;
3796
3797 if (type == RTW89_FW_WOWLAN)
3798 return &fw_info->wowlan;
3799 return &fw_info->normal;
3800 }
3801
3802 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3803 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
3804 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
3805 struct sk_buff *skb, bool fwdl);
3806 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
3807 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
3808 struct rtw89_tx_desc_info *desc_info,
3809 void *txdesc);
3810 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
3811 struct rtw89_tx_desc_info *desc_info,
3812 void *txdesc);
3813 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
3814 struct rtw89_tx_desc_info *desc_info,
3815 void *txdesc);
3816 void rtw89_core_rx(struct rtw89_dev *rtwdev,
3817 struct rtw89_rx_desc_info *desc_info,
3818 struct sk_buff *skb);
3819 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
3820 struct rtw89_rx_desc_info *desc_info,
3821 u8 *data, u32 data_offset);
3822 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
3823 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
3824 void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
3825 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
3826 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
3827 struct ieee80211_vif *vif,
3828 struct ieee80211_sta *sta);
3829 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
3830 struct ieee80211_vif *vif,
3831 struct ieee80211_sta *sta);
3832 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
3833 struct ieee80211_vif *vif,
3834 struct ieee80211_sta *sta);
3835 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
3836 struct ieee80211_vif *vif,
3837 struct ieee80211_sta *sta);
3838 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
3839 struct ieee80211_vif *vif,
3840 struct ieee80211_sta *sta);
3841 int rtw89_core_init(struct rtw89_dev *rtwdev);
3842 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
3843 int rtw89_core_register(struct rtw89_dev *rtwdev);
3844 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
3845 void rtw89_set_channel(struct rtw89_dev *rtwdev);
3846 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
3847 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
3848 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
3849 int rtw89_core_acquire_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
3850 int rtw89_core_release_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
3851 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
3852 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
3853 u16 rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate);
3854 int rtw89_regd_init(struct rtw89_dev *rtwdev,
3855 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
3856 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
3857 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
3858 struct rtw89_traffic_stats *stats);
3859 int rtw89_core_start(struct rtw89_dev *rtwdev);
3860 void rtw89_core_stop(struct rtw89_dev *rtwdev);
3861 void rtw89_core_update_beacon_work(struct work_struct *work);
3862 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3863 const u8 *mac_addr, bool hw_scan);
3864 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
3865 struct ieee80211_vif *vif, bool hw_scan);
3866
3867 #endif
3868