1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_MAC_H__
6 #define __RTW89_MAC_H__
7
8 #include "core.h"
9 #include "reg.h"
10
11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
12 #define ADDR_CAM_ENT_SIZE 0x40
13 #define BSSID_CAM_ENT_SIZE 0x08
14 #define HFC_PAGE_UNIT 64
15 #define RPWM_TRY_CNT 3
16
17 enum rtw89_mac_hwmod_sel {
18 RTW89_DMAC_SEL = 0,
19 RTW89_CMAC_SEL = 1,
20
21 RTW89_MAC_INVALID,
22 };
23
24 enum rtw89_mac_fwd_target {
25 RTW89_FWD_DONT_CARE = 0,
26 RTW89_FWD_TO_HOST = 1,
27 RTW89_FWD_TO_WLAN_CPU = 2
28 };
29
30 enum rtw89_mac_wd_dma_intvl {
31 RTW89_MAC_WD_DMA_INTVL_0S,
32 RTW89_MAC_WD_DMA_INTVL_256NS,
33 RTW89_MAC_WD_DMA_INTVL_512NS,
34 RTW89_MAC_WD_DMA_INTVL_768NS,
35 RTW89_MAC_WD_DMA_INTVL_1US,
36 RTW89_MAC_WD_DMA_INTVL_1_5US,
37 RTW89_MAC_WD_DMA_INTVL_2US,
38 RTW89_MAC_WD_DMA_INTVL_4US,
39 RTW89_MAC_WD_DMA_INTVL_8US,
40 RTW89_MAC_WD_DMA_INTVL_16US,
41 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
42 };
43
44 enum rtw89_mac_multi_tag_num {
45 RTW89_MAC_TAG_NUM_1,
46 RTW89_MAC_TAG_NUM_2,
47 RTW89_MAC_TAG_NUM_3,
48 RTW89_MAC_TAG_NUM_4,
49 RTW89_MAC_TAG_NUM_5,
50 RTW89_MAC_TAG_NUM_6,
51 RTW89_MAC_TAG_NUM_7,
52 RTW89_MAC_TAG_NUM_8,
53 RTW89_MAC_TAG_NUM_DEF = 0xFE
54 };
55
56 enum rtw89_mac_lbc_tmr {
57 RTW89_MAC_LBC_TMR_8US = 0,
58 RTW89_MAC_LBC_TMR_16US,
59 RTW89_MAC_LBC_TMR_32US,
60 RTW89_MAC_LBC_TMR_64US,
61 RTW89_MAC_LBC_TMR_128US,
62 RTW89_MAC_LBC_TMR_256US,
63 RTW89_MAC_LBC_TMR_512US,
64 RTW89_MAC_LBC_TMR_1MS,
65 RTW89_MAC_LBC_TMR_2MS,
66 RTW89_MAC_LBC_TMR_4MS,
67 RTW89_MAC_LBC_TMR_8MS,
68 RTW89_MAC_LBC_TMR_DEF = 0xFE
69 };
70
71 enum rtw89_mac_cpuio_op_cmd_type {
72 CPUIO_OP_CMD_GET_1ST_PID = 0,
73 CPUIO_OP_CMD_GET_NEXT_PID = 1,
74 CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
75 CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
76 CPUIO_OP_CMD_DEQ = 8,
77 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
78 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
79 };
80
81 enum rtw89_mac_wde_dle_port_id {
82 WDE_DLE_PORT_ID_DISPATCH = 0,
83 WDE_DLE_PORT_ID_PKTIN = 1,
84 WDE_DLE_PORT_ID_CMAC0 = 3,
85 WDE_DLE_PORT_ID_CMAC1 = 4,
86 WDE_DLE_PORT_ID_CPU_IO = 6,
87 WDE_DLE_PORT_ID_WDRLS = 7,
88 WDE_DLE_PORT_ID_END = 8
89 };
90
91 enum rtw89_mac_wde_dle_queid_wdrls {
92 WDE_DLE_QUEID_TXOK = 0,
93 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
94 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
95 WDE_DLE_QUEID_DROP_MACID_DROP = 3,
96 WDE_DLE_QUEID_NO_REPORT = 4
97 };
98
99 enum rtw89_mac_ple_dle_port_id {
100 PLE_DLE_PORT_ID_DISPATCH = 0,
101 PLE_DLE_PORT_ID_MPDU = 1,
102 PLE_DLE_PORT_ID_SEC = 2,
103 PLE_DLE_PORT_ID_CMAC0 = 3,
104 PLE_DLE_PORT_ID_CMAC1 = 4,
105 PLE_DLE_PORT_ID_WDRLS = 5,
106 PLE_DLE_PORT_ID_CPU_IO = 6,
107 PLE_DLE_PORT_ID_PLRLS = 7,
108 PLE_DLE_PORT_ID_END = 8
109 };
110
111 enum rtw89_mac_ple_dle_queid_plrls {
112 PLE_DLE_QUEID_NO_REPORT = 0x0
113 };
114
115 enum rtw89_machdr_frame_type {
116 RTW89_MGNT = 0,
117 RTW89_CTRL = 1,
118 RTW89_DATA = 2,
119 };
120
121 enum rtw89_mac_dle_dfi_type {
122 DLE_DFI_TYPE_FREEPG = 0,
123 DLE_DFI_TYPE_QUOTA = 1,
124 DLE_DFI_TYPE_PAGELLT = 2,
125 DLE_DFI_TYPE_PKTINFO = 3,
126 DLE_DFI_TYPE_PREPKTLLT = 4,
127 DLE_DFI_TYPE_NXTPKTLLT = 5,
128 DLE_DFI_TYPE_QLNKTBL = 6,
129 DLE_DFI_TYPE_QEMPTY = 7,
130 };
131
132 enum rtw89_mac_dle_wde_quota_id {
133 WDE_QTAID_HOST_IF = 0,
134 WDE_QTAID_WLAN_CPU = 1,
135 WDE_QTAID_DATA_CPU = 2,
136 WDE_QTAID_PKTIN = 3,
137 WDE_QTAID_CPUIO = 4,
138 };
139
140 enum rtw89_mac_dle_ple_quota_id {
141 PLE_QTAID_B0_TXPL = 0,
142 PLE_QTAID_B1_TXPL = 1,
143 PLE_QTAID_C2H = 2,
144 PLE_QTAID_H2C = 3,
145 PLE_QTAID_WLAN_CPU = 4,
146 PLE_QTAID_MPDU = 5,
147 PLE_QTAID_CMAC0_RX = 6,
148 PLE_QTAID_CMAC1_RX = 7,
149 PLE_QTAID_CMAC1_BBRPT = 8,
150 PLE_QTAID_WDRLS = 9,
151 PLE_QTAID_CPUIO = 10,
152 };
153
154 enum rtw89_mac_dle_ctrl_type {
155 DLE_CTRL_TYPE_WDE = 0,
156 DLE_CTRL_TYPE_PLE = 1,
157 DLE_CTRL_TYPE_NUM = 2,
158 };
159
160 enum rtw89_mac_ax_l0_to_l1_event {
161 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
162 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
163 MAC_AX_L0_TO_L1_RLS_PKID = 2,
164 MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
165 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
166 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
167 MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
168 MAC_AX_L0_TO_L1_EVENT_MAX = 15,
169 };
170
171 enum rtw89_mac_dbg_port_sel {
172 /* CMAC 0 related */
173 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
174 RTW89_DBG_PORT_SEL_SCH_C0,
175 RTW89_DBG_PORT_SEL_TMAC_C0,
176 RTW89_DBG_PORT_SEL_RMAC_C0,
177 RTW89_DBG_PORT_SEL_RMACST_C0,
178 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
179 RTW89_DBG_PORT_SEL_TRXPTCL_C0,
180 RTW89_DBG_PORT_SEL_TX_INFOL_C0,
181 RTW89_DBG_PORT_SEL_TX_INFOH_C0,
182 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
183 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
184 /* CMAC 1 related */
185 RTW89_DBG_PORT_SEL_PTCL_C1,
186 RTW89_DBG_PORT_SEL_SCH_C1,
187 RTW89_DBG_PORT_SEL_TMAC_C1,
188 RTW89_DBG_PORT_SEL_RMAC_C1,
189 RTW89_DBG_PORT_SEL_RMACST_C1,
190 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
191 RTW89_DBG_PORT_SEL_TRXPTCL_C1,
192 RTW89_DBG_PORT_SEL_TX_INFOL_C1,
193 RTW89_DBG_PORT_SEL_TX_INFOH_C1,
194 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
195 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
196 /* DLE related */
197 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
198 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
199 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
200 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
201 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
202 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
203 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
204 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
205 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
206 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
207 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
208 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
209 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
210 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
211 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
212 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
213 RTW89_DBG_PORT_SEL_PKTINFO,
214 /* PCIE related */
215 RTW89_DBG_PORT_SEL_PCIE_TXDMA,
216 RTW89_DBG_PORT_SEL_PCIE_RXDMA,
217 RTW89_DBG_PORT_SEL_PCIE_CVT,
218 RTW89_DBG_PORT_SEL_PCIE_CXPL,
219 RTW89_DBG_PORT_SEL_PCIE_IO,
220 RTW89_DBG_PORT_SEL_PCIE_MISC,
221 RTW89_DBG_PORT_SEL_PCIE_MISC2,
222
223 /* keep last */
224 RTW89_DBG_PORT_SEL_LAST,
225 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
226 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
227 };
228
229 /* SRAM mem dump */
230 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
231
232 #define AXIDMA_BASE_ADDR 0x18006000
233 #define STA_SCHED_BASE_ADDR 0x18808000
234 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
235 #define SECURITY_CAM_BASE_ADDR 0x18814000
236 #define WOW_CAM_BASE_ADDR 0x18815000
237 #define CMAC_TBL_BASE_ADDR 0x18840000
238 #define ADDR_CAM_BASE_ADDR 0x18850000
239 #define BSSID_CAM_BASE_ADDR 0x18853000
240 #define BA_CAM_BASE_ADDR 0x18854000
241 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
242 #define SHARED_BUF_BASE_ADDR 0x18700000
243 #define DMAC_TBL_BASE_ADDR 0x18800000
244 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
245 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
246 #define TXD_FIFO_0_BASE_ADDR 0x18856200
247 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
248 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
249 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
250 #define CPU_LOCAL_BASE_ADDR 0x18003000
251
252 #define CCTL_INFO_SIZE 32
253
254 enum rtw89_mac_mem_sel {
255 RTW89_MAC_MEM_AXIDMA,
256 RTW89_MAC_MEM_SHARED_BUF,
257 RTW89_MAC_MEM_DMAC_TBL,
258 RTW89_MAC_MEM_SHCUT_MACHDR,
259 RTW89_MAC_MEM_STA_SCHED,
260 RTW89_MAC_MEM_RXPLD_FLTR_CAM,
261 RTW89_MAC_MEM_SECURITY_CAM,
262 RTW89_MAC_MEM_WOW_CAM,
263 RTW89_MAC_MEM_CMAC_TBL,
264 RTW89_MAC_MEM_ADDR_CAM,
265 RTW89_MAC_MEM_BA_CAM,
266 RTW89_MAC_MEM_BCN_IE_CAM0,
267 RTW89_MAC_MEM_BCN_IE_CAM1,
268 RTW89_MAC_MEM_TXD_FIFO_0,
269 RTW89_MAC_MEM_TXD_FIFO_1,
270 RTW89_MAC_MEM_TXDATA_FIFO_0,
271 RTW89_MAC_MEM_TXDATA_FIFO_1,
272 RTW89_MAC_MEM_CPU_LOCAL,
273 RTW89_MAC_MEM_BSSID_CAM,
274
275 /* keep last */
276 RTW89_MAC_MEM_NUM,
277 };
278
279 extern const u32 rtw89_mac_mem_base_addrs[];
280
281 enum rtw89_rpwm_req_pwr_state {
282 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
283 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
284 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
285 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
286 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
287 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
288 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
289 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
290 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
291 };
292
293 struct rtw89_pwr_cfg {
294 u16 addr;
295 u8 cv_msk;
296 u8 intf_msk;
297 u8 base:4;
298 u8 cmd:4;
299 u8 msk;
300 u8 val;
301 };
302
303 enum rtw89_mac_c2h_ofld_func {
304 RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
305 RTW89_MAC_C2H_FUNC_READ_RSP,
306 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
307 RTW89_MAC_C2H_FUNC_BCN_RESEND,
308 RTW89_MAC_C2H_FUNC_MACID_PAUSE,
309 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
310 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
311 RTW89_MAC_C2H_FUNC_OFLD_MAX,
312 };
313
314 enum rtw89_mac_c2h_info_func {
315 RTW89_MAC_C2H_FUNC_REC_ACK,
316 RTW89_MAC_C2H_FUNC_DONE_ACK,
317 RTW89_MAC_C2H_FUNC_C2H_LOG,
318 RTW89_MAC_C2H_FUNC_BCN_CNT,
319 RTW89_MAC_C2H_FUNC_INFO_MAX,
320 };
321
322 enum rtw89_mac_c2h_class {
323 RTW89_MAC_C2H_CLASS_INFO,
324 RTW89_MAC_C2H_CLASS_OFLD,
325 RTW89_MAC_C2H_CLASS_TWT,
326 RTW89_MAC_C2H_CLASS_WOW,
327 RTW89_MAC_C2H_CLASS_MCC,
328 RTW89_MAC_C2H_CLASS_FWDBG,
329 RTW89_MAC_C2H_CLASS_MAX,
330 };
331
332 struct rtw89_mac_ax_coex {
333 #define RTW89_MAC_AX_COEX_RTK_MODE 0
334 #define RTW89_MAC_AX_COEX_CSR_MODE 1
335 u8 pta_mode;
336 #define RTW89_MAC_AX_COEX_INNER 0
337 #define RTW89_MAC_AX_COEX_OUTPUT 1
338 #define RTW89_MAC_AX_COEX_INPUT 2
339 u8 direction;
340 };
341
342 struct rtw89_mac_ax_plt {
343 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
344 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
345 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
346 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
347 u8 band;
348 u8 tx;
349 u8 rx;
350 };
351
352 enum rtw89_mac_bf_rrsc_rate {
353 RTW89_MAC_BF_RRSC_6M = 0,
354 RTW89_MAC_BF_RRSC_9M = 1,
355 RTW89_MAC_BF_RRSC_12M,
356 RTW89_MAC_BF_RRSC_18M,
357 RTW89_MAC_BF_RRSC_24M,
358 RTW89_MAC_BF_RRSC_36M,
359 RTW89_MAC_BF_RRSC_48M,
360 RTW89_MAC_BF_RRSC_54M,
361 RTW89_MAC_BF_RRSC_HT_MSC0,
362 RTW89_MAC_BF_RRSC_HT_MSC1,
363 RTW89_MAC_BF_RRSC_HT_MSC2,
364 RTW89_MAC_BF_RRSC_HT_MSC3,
365 RTW89_MAC_BF_RRSC_HT_MSC4,
366 RTW89_MAC_BF_RRSC_HT_MSC5,
367 RTW89_MAC_BF_RRSC_HT_MSC6,
368 RTW89_MAC_BF_RRSC_HT_MSC7,
369 RTW89_MAC_BF_RRSC_VHT_MSC0,
370 RTW89_MAC_BF_RRSC_VHT_MSC1,
371 RTW89_MAC_BF_RRSC_VHT_MSC2,
372 RTW89_MAC_BF_RRSC_VHT_MSC3,
373 RTW89_MAC_BF_RRSC_VHT_MSC4,
374 RTW89_MAC_BF_RRSC_VHT_MSC5,
375 RTW89_MAC_BF_RRSC_VHT_MSC6,
376 RTW89_MAC_BF_RRSC_VHT_MSC7,
377 RTW89_MAC_BF_RRSC_HE_MSC0,
378 RTW89_MAC_BF_RRSC_HE_MSC1,
379 RTW89_MAC_BF_RRSC_HE_MSC2,
380 RTW89_MAC_BF_RRSC_HE_MSC3,
381 RTW89_MAC_BF_RRSC_HE_MSC4,
382 RTW89_MAC_BF_RRSC_HE_MSC5,
383 RTW89_MAC_BF_RRSC_HE_MSC6,
384 RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
385 RTW89_MAC_BF_RRSC_MAX = 32
386 };
387
388 #define RTW89_R32_EA 0xEAEAEAEA
389 #define RTW89_R32_DEAD 0xDEADBEEF
390 #define MAC_REG_POOL_COUNT 10
391 #define ACCESS_CMAC(_addr) \
392 ({typeof(_addr) __addr = (_addr); \
393 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
394
395 #define PTCL_IDLE_POLL_CNT 10000
396 #define SW_CVR_DUR_US 8
397 #define SW_CVR_CNT 8
398
399 #define DLE_BOUND_UNIT (8 * 1024)
400 #define DLE_WAIT_CNT 2000
401 #define TRXCFG_WAIT_CNT 2000
402
403 #define RTW89_WDE_PG_64 64
404 #define RTW89_WDE_PG_128 128
405 #define RTW89_WDE_PG_256 256
406
407 #define S_AX_WDE_PAGE_SEL_64 0
408 #define S_AX_WDE_PAGE_SEL_128 1
409 #define S_AX_WDE_PAGE_SEL_256 2
410
411 #define RTW89_PLE_PG_64 64
412 #define RTW89_PLE_PG_128 128
413 #define RTW89_PLE_PG_256 256
414
415 #define S_AX_PLE_PAGE_SEL_64 0
416 #define S_AX_PLE_PAGE_SEL_128 1
417 #define S_AX_PLE_PAGE_SEL_256 2
418
419 #define SDIO_LOCAL_BASE_ADDR 0x80000000
420
421 #define PWR_CMD_WRITE 0
422 #define PWR_CMD_POLL 1
423 #define PWR_CMD_DELAY 2
424 #define PWR_CMD_END 3
425
426 #define PWR_INTF_MSK_SDIO BIT(0)
427 #define PWR_INTF_MSK_USB BIT(1)
428 #define PWR_INTF_MSK_PCIE BIT(2)
429 #define PWR_INTF_MSK_ALL 0x7
430
431 #define PWR_BASE_MAC 0
432 #define PWR_BASE_USB 1
433 #define PWR_BASE_PCIE 2
434 #define PWR_BASE_SDIO 3
435
436 #define PWR_CV_MSK_A BIT(0)
437 #define PWR_CV_MSK_B BIT(1)
438 #define PWR_CV_MSK_C BIT(2)
439 #define PWR_CV_MSK_D BIT(3)
440 #define PWR_CV_MSK_E BIT(4)
441 #define PWR_CV_MSK_F BIT(5)
442 #define PWR_CV_MSK_G BIT(6)
443 #define PWR_CV_MSK_TEST BIT(7)
444 #define PWR_CV_MSK_ALL 0xFF
445
446 #define PWR_DELAY_US 0
447 #define PWR_DELAY_MS 1
448
449 /* STA scheduler */
450 #define SS_MACID_SH 8
451 #define SS_TX_LEN_MSK 0x1FFFFF
452 #define SS_CTRL1_R_TX_LEN 5
453 #define SS_CTRL1_R_NEXT_LINK 20
454 #define SS_LINK_SIZE 256
455
456 /* MAC debug port */
457 #define TMAC_DBG_SEL_C0 0xA5
458 #define RMAC_DBG_SEL_C0 0xA6
459 #define TRXPTCL_DBG_SEL_C0 0xA7
460 #define TMAC_DBG_SEL_C1 0xB5
461 #define RMAC_DBG_SEL_C1 0xB6
462 #define TRXPTCL_DBG_SEL_C1 0xB7
463 #define FW_PROG_CNTR_DBG_SEL 0xF2
464 #define PCIE_TXDMA_DBG_SEL 0x30
465 #define PCIE_RXDMA_DBG_SEL 0x31
466 #define PCIE_CVT_DBG_SEL 0x32
467 #define PCIE_CXPL_DBG_SEL 0x33
468 #define PCIE_IO_DBG_SEL 0x37
469 #define PCIE_MISC_DBG_SEL 0x38
470 #define PCIE_MISC2_DBG_SEL 0x00
471 #define MAC_DBG_SEL 1
472 #define RMAC_CMAC_DBG_SEL 1
473
474 /* TRXPTCL dbg port sel */
475 #define TRXPTRL_DBG_SEL_TMAC 0
476 #define TRXPTRL_DBG_SEL_RMAC 1
477
478 struct rtw89_cpuio_ctrl {
479 u16 pkt_num;
480 u16 start_pktid;
481 u16 end_pktid;
482 u8 cmd_type;
483 u8 macid;
484 u8 src_pid;
485 u8 src_qid;
486 u8 dst_pid;
487 u8 dst_qid;
488 u16 pktid;
489 };
490
491 struct rtw89_mac_dbg_port_info {
492 u32 sel_addr;
493 u8 sel_byte;
494 u32 sel_msk;
495 u32 srt;
496 u32 end;
497 u32 rd_addr;
498 u8 rd_byte;
499 u32 rd_msk;
500 };
501
502 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
503 #define QLNKTBL_ADDR_INFO_SEL_0 0
504 #define QLNKTBL_ADDR_INFO_SEL_1 1
505 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
506 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
507
508 struct rtw89_mac_dle_dfi_ctrl {
509 enum rtw89_mac_dle_ctrl_type type;
510 u32 target;
511 u32 addr;
512 u32 out_data;
513 };
514
515 struct rtw89_mac_dle_dfi_quota {
516 enum rtw89_mac_dle_ctrl_type dle_type;
517 u32 qtaid;
518 u16 rsv_pgnum;
519 u16 use_pgnum;
520 };
521
522 struct rtw89_mac_dle_dfi_qempty {
523 enum rtw89_mac_dle_ctrl_type dle_type;
524 u32 grpsel;
525 u32 qempty;
526 };
527
528 enum rtw89_mac_error_scenario {
529 RTW89_WCPU_CPU_EXCEPTION = 2,
530 RTW89_WCPU_ASSERTION = 3,
531 };
532
533 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28)
534
535 /* Define DBG and recovery enum */
536 enum mac_ax_err_info {
537 /* Get error info */
538
539 /* L0 */
540 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
541 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
542 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
543 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
544
545 /* L1 */
546 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
547 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
548 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
549 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
550 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
551
552 /* L2 */
553 /* address hole (master) */
554 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
555 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
556 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
557 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
558 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
559 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
560 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
561 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
562
563 /* AHB bridge timeout (master) */
564 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
565 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
566 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
567 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
568 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
569 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
570 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
571 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
572
573 /* APB_SA bridge timeout (master + slave) */
574 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
575 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
576 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
577 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
578 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
579 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
580 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
581 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
582 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
583 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
584 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
585 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
586 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
587 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
588 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
589 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
590 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
591 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
592 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
593 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
594 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
595 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
596 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
597 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
598 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
599 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
600 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
601 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
602 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
603 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
604 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
605 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
606 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
607 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
608 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
609 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
610 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
611 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
612 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
613 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
614 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
615 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
616 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
617 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
618 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
619 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
620 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
621 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
622 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
623 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
624 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
625 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
626 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
627 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
628 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
629 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
630 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
631 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
632 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
633 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
634 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
635 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
636 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
637 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
638 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
639 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
640 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
641 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
642 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
643 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
644 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
645 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
646 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
647 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
648 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
649 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
650 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
651 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
652 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
653 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
654 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
655 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
656 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
657 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
658 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
659 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
660 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
661
662 /* APB_BBRF bridge timeout (master) */
663 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
664 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
665 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
666 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
667 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
668 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
669 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
670 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
671 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
672 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
673 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
674 MAC_AX_ERR_ASSERTION = 0x4000,
675 MAC_AX_GET_ERR_MAX,
676 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
677
678 /* set error info */
679 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
680 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
681 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
682 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
683 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
684 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
685 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
686 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
687 MAC_AX_SET_ERR_MAX,
688 };
689
690 struct rtw89_mac_size_set {
691 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
692 const struct rtw89_dle_size wde_size0;
693 const struct rtw89_dle_size wde_size4;
694 const struct rtw89_dle_size wde_size6;
695 const struct rtw89_dle_size wde_size9;
696 const struct rtw89_dle_size wde_size18;
697 const struct rtw89_dle_size wde_size19;
698 const struct rtw89_dle_size ple_size0;
699 const struct rtw89_dle_size ple_size4;
700 const struct rtw89_dle_size ple_size6;
701 const struct rtw89_dle_size ple_size8;
702 const struct rtw89_dle_size ple_size18;
703 const struct rtw89_dle_size ple_size19;
704 const struct rtw89_wde_quota wde_qt0;
705 const struct rtw89_wde_quota wde_qt4;
706 const struct rtw89_wde_quota wde_qt6;
707 const struct rtw89_wde_quota wde_qt17;
708 const struct rtw89_wde_quota wde_qt18;
709 const struct rtw89_ple_quota ple_qt4;
710 const struct rtw89_ple_quota ple_qt5;
711 const struct rtw89_ple_quota ple_qt13;
712 const struct rtw89_ple_quota ple_qt18;
713 const struct rtw89_ple_quota ple_qt44;
714 const struct rtw89_ple_quota ple_qt45;
715 const struct rtw89_ple_quota ple_qt46;
716 const struct rtw89_ple_quota ple_qt47;
717 const struct rtw89_ple_quota ple_qt58;
718 };
719
720 extern const struct rtw89_mac_size_set rtw89_mac_size;
721
rtw89_mac_reg_by_idx(u32 reg_base,u8 band)722 static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band)
723 {
724 return band == 0 ? reg_base : (reg_base + 0x2000);
725 }
726
rtw89_mac_reg_by_port(u32 base,u8 port,u8 mac_idx)727 static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx)
728 {
729 return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx);
730 }
731
732 static inline u32
rtw89_read32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask)733 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
734 u32 base, u32 mask)
735 {
736 u32 reg;
737
738 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
739 return rtw89_read32_mask(rtwdev, reg, mask);
740 }
741
742 static inline void
rtw89_write32_port(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 data)743 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base,
744 u32 data)
745 {
746 u32 reg;
747
748 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
749 rtw89_write32(rtwdev, reg, data);
750 }
751
752 static inline void
rtw89_write32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u32 data)753 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
754 u32 base, u32 mask, u32 data)
755 {
756 u32 reg;
757
758 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
759 rtw89_write32_mask(rtwdev, reg, mask, data);
760 }
761
762 static inline void
rtw89_write16_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u16 data)763 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
764 u32 base, u32 mask, u16 data)
765 {
766 u32 reg;
767
768 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
769 rtw89_write16_mask(rtwdev, reg, mask, data);
770 }
771
772 static inline void
rtw89_write32_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)773 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
774 u32 base, u32 bit)
775 {
776 u32 reg;
777
778 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
779 rtw89_write32_clr(rtwdev, reg, bit);
780 }
781
782 static inline void
rtw89_write16_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u16 bit)783 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
784 u32 base, u16 bit)
785 {
786 u32 reg;
787
788 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
789 rtw89_write16_clr(rtwdev, reg, bit);
790 }
791
792 static inline void
rtw89_write32_port_set(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)793 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
794 u32 base, u32 bit)
795 {
796 u32 reg;
797
798 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
799 rtw89_write32_set(rtwdev, reg, bit);
800 }
801
802 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
803 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev);
804 int rtw89_mac_init(struct rtw89_dev *rtwdev);
805 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
806 enum rtw89_mac_hwmod_sel sel);
807 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
808 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
809 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
810 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
811 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
812 struct ieee80211_vif *vif);
813 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
814 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
815 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
816
rtw89_chip_enable_bb_rf(struct rtw89_dev * rtwdev)817 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
818 {
819 const struct rtw89_chip_info *chip = rtwdev->chip;
820
821 return chip->ops->enable_bb_rf(rtwdev);
822 }
823
rtw89_chip_disable_bb_rf(struct rtw89_dev * rtwdev)824 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
825 {
826 const struct rtw89_chip_info *chip = rtwdev->chip;
827
828 return chip->ops->disable_bb_rf(rtwdev);
829 }
830
831 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
832 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
833 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
834 u32 len, u8 class, u8 func);
835 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
836 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
837 u32 *tx_en, enum rtw89_sch_tx_sel sel);
838 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
839 u32 *tx_en, enum rtw89_sch_tx_sel sel);
840 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
841 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
842 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable);
843 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx);
844 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
845 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
846 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
847 const struct rtw89_mac_ax_coex *coex);
848 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
849 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
850 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
851 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
852 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
853 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band);
854 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
855 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
856 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
857 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
858 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
859 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,
860 enum rtw89_phy_idx phy_idx,
861 u32 reg_base, u32 *cr);
862 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
863 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);
864 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
865 struct ieee80211_sta *sta);
866 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
867 struct ieee80211_sta *sta);
868 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
869 struct ieee80211_bss_conf *conf);
870 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
871 struct ieee80211_sta *sta, bool disconnect);
872 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
873 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
874 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
875 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
876 struct rtw89_vif *rtwvif, bool en);
877 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause);
878
rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)879 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
880 {
881 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
882 return;
883
884 _rtw89_mac_bf_monitor_track(rtwdev);
885 }
886
rtw89_mac_txpwr_read32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * val)887 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
888 enum rtw89_phy_idx phy_idx,
889 u32 reg_base, u32 *val)
890 {
891 u32 cr;
892
893 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
894 return -EINVAL;
895
896 *val = rtw89_read32(rtwdev, cr);
897 return 0;
898 }
899
rtw89_mac_txpwr_write32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 val)900 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
901 enum rtw89_phy_idx phy_idx,
902 u32 reg_base, u32 val)
903 {
904 u32 cr;
905
906 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
907 return -EINVAL;
908
909 rtw89_write32(rtwdev, cr, val);
910 return 0;
911 }
912
rtw89_mac_txpwr_write32_mask(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 mask,u32 val)913 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
914 enum rtw89_phy_idx phy_idx,
915 u32 reg_base, u32 mask, u32 val)
916 {
917 u32 cr;
918
919 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
920 return -EINVAL;
921
922 rtw89_write32_mask(rtwdev, cr, mask, val);
923 return 0;
924 }
925
rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev * rtwdev,bool enable)926 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev,
927 bool enable)
928 {
929 const struct rtw89_chip_info *chip = rtwdev->chip;
930
931 if (enable)
932 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
933 B_AX_HCI_TXDMA_EN);
934 else
935 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
936 B_AX_HCI_TXDMA_EN);
937 }
938
rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev * rtwdev,bool enable)939 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev,
940 bool enable)
941 {
942 const struct rtw89_chip_info *chip = rtwdev->chip;
943
944 if (enable)
945 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
946 B_AX_HCI_RXDMA_EN);
947 else
948 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
949 B_AX_HCI_RXDMA_EN);
950 }
951
rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev * rtwdev,bool enable)952 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev,
953 bool enable)
954 {
955 const struct rtw89_chip_info *chip = rtwdev->chip;
956
957 if (enable)
958 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
959 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
960 else
961 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
962 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
963 }
964
965 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
966 bool resume, u32 tx_time);
967 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
968 u32 *tx_time);
969 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
970 struct rtw89_sta *rtwsta,
971 bool resume, u8 tx_retry);
972 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
973 struct rtw89_sta *rtwsta, u8 *tx_retry);
974
975 enum rtw89_mac_xtal_si_offset {
976 XTAL0 = 0x0,
977 XTAL3 = 0x3,
978 XTAL_SI_XTAL_SC_XI = 0x04,
979 #define XTAL_SC_XI_MASK GENMASK(7, 0)
980 XTAL_SI_XTAL_SC_XO = 0x05,
981 #define XTAL_SC_XO_MASK GENMASK(7, 0)
982 XTAL_SI_PWR_CUT = 0x10,
983 #define XTAL_SI_SMALL_PWR_CUT BIT(0)
984 #define XTAL_SI_BIG_PWR_CUT BIT(1)
985 XTAL_SI_XTAL_XMD_2 = 0x24,
986 #define XTAL_SI_LDO_LPS GENMASK(6, 4)
987 XTAL_SI_XTAL_XMD_4 = 0x26,
988 #define XTAL_SI_LPS_CAP GENMASK(3, 0)
989 XTAL_SI_CV = 0x41,
990 XTAL_SI_LOW_ADDR = 0x62,
991 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
992 XTAL_SI_CTRL = 0x63,
993 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6)
994 #define XTAL_SI_RDY BIT(5)
995 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
996 XTAL_SI_READ_VAL = 0x7A,
997 XTAL_SI_WL_RFC_S0 = 0x80,
998 #define XTAL_SI_RF00S_EN GENMASK(2, 0)
999 #define XTAL_SI_RF00 BIT(0)
1000 XTAL_SI_WL_RFC_S1 = 0x81,
1001 #define XTAL_SI_RF10S_EN GENMASK(2, 0)
1002 #define XTAL_SI_RF10 BIT(0)
1003 XTAL_SI_ANAPAR_WL = 0x90,
1004 #define XTAL_SI_SRAM2RFC BIT(7)
1005 #define XTAL_SI_GND_SHDN_WL BIT(6)
1006 #define XTAL_SI_SHDN_WL BIT(5)
1007 #define XTAL_SI_RFC2RF BIT(4)
1008 #define XTAL_SI_OFF_EI BIT(3)
1009 #define XTAL_SI_OFF_WEI BIT(2)
1010 #define XTAL_SI_PON_EI BIT(1)
1011 #define XTAL_SI_PON_WEI BIT(0)
1012 XTAL_SI_SRAM_CTRL = 0xA1,
1013 #define FULL_BIT_MASK GENMASK(7, 0)
1014 };
1015
1016 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
1017 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
1018 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1019 u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd);
1020 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev,
1021 struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
1022
1023 #endif
1024