1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * rt1011.h -- RT1011 ALSA SoC amplifier component driver header
4  *
5  * Copyright(c) 2019 Realtek Semiconductor Corp.
6  */
7 
8 #ifndef _RT1011_H_
9 #define _RT1011_H_
10 
11 #define RT1011_DEVICE_ID_NUM 0x1011
12 
13 #define RT1011_RESET				0x0000
14 #define RT1011_CLK_1				0x0002
15 #define RT1011_CLK_2				0x0004
16 #define RT1011_CLK_3				0x0006
17 #define RT1011_CLK_4				0x0008
18 #define RT1011_PLL_1				0x000a
19 #define RT1011_PLL_2				0x000c
20 #define RT1011_SRC_1				0x000e
21 #define RT1011_SRC_2				0x0010
22 #define RT1011_SRC_3				0x0012
23 #define RT1011_CLK_DET				0x0020
24 #define RT1011_SIL_DET				0x0022
25 #define RT1011_PRIV_INDEX			0x006a
26 #define RT1011_PRIV_DATA			0x006c
27 #define RT1011_CUSTOMER_ID			0x0076
28 #define RT1011_FM_VER				0x0078
29 #define RT1011_VERSION_ID			0x007a
30 #define RT1011_VENDOR_ID			0x007c
31 #define RT1011_DEVICE_ID			0x007d
32 #define RT1011_DUM_RW_0				0x00f0
33 #define RT1011_DUM_YUN				0x00f2
34 #define RT1011_DUM_RW_1				0x00f3
35 #define RT1011_DUM_RO				0x00f4
36 #define RT1011_MAN_I2C_DEV			0x0100
37 #define RT1011_DAC_SET_1			0x0102
38 #define RT1011_DAC_SET_2			0x0104
39 #define RT1011_DAC_SET_3			0x0106
40 #define RT1011_ADC_SET				0x0107
41 #define RT1011_ADC_SET_1			0x0108
42 #define RT1011_ADC_SET_2			0x010a
43 #define RT1011_ADC_SET_3			0x010c
44 #define RT1011_ADC_SET_4			0x010e
45 #define RT1011_ADC_SET_5			0x0110
46 #define RT1011_TDM_TOTAL_SET		0x0111
47 #define RT1011_TDM1_SET_TCON		0x0112
48 #define RT1011_TDM1_SET_1			0x0114
49 #define RT1011_TDM1_SET_2			0x0116
50 #define RT1011_TDM1_SET_3			0x0118
51 #define RT1011_TDM1_SET_4			0x011a
52 #define RT1011_TDM1_SET_5			0x011c
53 #define RT1011_TDM2_SET_1			0x011e
54 #define RT1011_TDM2_SET_2			0x0120
55 #define RT1011_TDM2_SET_3			0x0122
56 #define RT1011_TDM2_SET_4			0x0124
57 #define RT1011_TDM2_SET_5			0x0126
58 #define RT1011_PWM_CAL				0x0200
59 #define RT1011_MIXER_1				0x0300
60 #define RT1011_MIXER_2				0x0302
61 #define RT1011_ADRC_LIMIT			0x0310
62 #define RT1011_A_PRO				0x0311
63 #define RT1011_A_TIMING_1			0x0313
64 #define RT1011_A_TIMING_2			0x0314
65 #define RT1011_A_TEMP_SEN			0x0316
66 #define RT1011_SPK_VOL_DET_1		0x0319
67 #define RT1011_SPK_VOL_DET_2		0x031a
68 #define RT1011_SPK_VOL_TEST_OUT		0x031b
69 #define RT1011_VBAT_VOL_DET_1		0x031c
70 #define RT1011_VBAT_VOL_DET_2		0x031d
71 #define RT1011_VBAT_TEST_OUT_1		0x031e
72 #define RT1011_VBAT_TEST_OUT_2		0x031f
73 #define RT1011_VBAT_PROTECTION			0x0320
74 #define RT1011_VBAT_DET				0x0321
75 #define RT1011_POWER_1				0x0322
76 #define RT1011_POWER_2				0x0324
77 #define RT1011_POWER_3				0x0326
78 #define RT1011_POWER_4				0x0328
79 #define RT1011_POWER_5				0x0329
80 #define RT1011_POWER_6				0x032a
81 #define RT1011_POWER_7				0x032b
82 #define RT1011_POWER_8				0x032c
83 #define RT1011_POWER_9				0x032d
84 #define RT1011_CLASS_D_POS			0x032e
85 #define RT1011_BOOST_CON_1			0x0330
86 #define RT1011_BOOST_CON_2			0x0332
87 #define RT1011_ANALOG_CTRL			0x0334
88 #define RT1011_POWER_SEQ			0x0340
89 #define RT1011_SHORT_CIRCUIT_DET_1	0x0508
90 #define RT1011_SHORT_CIRCUIT_DET_2	0x050a
91 #define RT1011_SPK_TEMP_PROTECT_0		0x050c
92 #define RT1011_SPK_TEMP_PROTECT_1		0x050d
93 #define RT1011_SPK_TEMP_PROTECT_2		0x050e
94 #define RT1011_SPK_TEMP_PROTECT_3		0x050f
95 #define RT1011_SPK_TEMP_PROTECT_4		0x0510
96 #define RT1011_SPK_TEMP_PROTECT_5		0x0511
97 #define RT1011_SPK_TEMP_PROTECT_6		0x0512
98 #define RT1011_SPK_TEMP_PROTECT_7		0x0516
99 #define RT1011_SPK_TEMP_PROTECT_8		0x0517
100 #define RT1011_SPK_TEMP_PROTECT_9		0x0518
101 #define RT1011_SPK_PRO_DC_DET_1		0x0519
102 #define RT1011_SPK_PRO_DC_DET_2		0x051a
103 #define RT1011_SPK_PRO_DC_DET_3		0x051b
104 #define RT1011_SPK_PRO_DC_DET_4		0x051c
105 #define RT1011_SPK_PRO_DC_DET_5		0x051d
106 #define RT1011_SPK_PRO_DC_DET_6		0x051e
107 #define RT1011_SPK_PRO_DC_DET_7		0x051f
108 #define RT1011_SPK_PRO_DC_DET_8		0x0520
109 #define RT1011_SPL_1				0x0521
110 #define RT1011_SPL_2				0x0522
111 #define RT1011_SPL_3				0x0524
112 #define RT1011_SPL_4				0x0526
113 #define RT1011_THER_FOLD_BACK_1		0x0528
114 #define RT1011_THER_FOLD_BACK_2		0x052a
115 #define RT1011_EXCUR_PROTECT_1			0x0530
116 #define RT1011_EXCUR_PROTECT_2			0x0532
117 #define RT1011_EXCUR_PROTECT_3			0x0534
118 #define RT1011_EXCUR_PROTECT_4			0x0535
119 #define RT1011_BAT_GAIN_1			0x0536
120 #define RT1011_BAT_GAIN_2			0x0538
121 #define RT1011_BAT_GAIN_3			0x053a
122 #define RT1011_BAT_GAIN_4			0x053c
123 #define RT1011_BAT_GAIN_5			0x053d
124 #define RT1011_BAT_GAIN_6			0x053e
125 #define RT1011_BAT_GAIN_7			0x053f
126 #define RT1011_BAT_GAIN_8			0x0540
127 #define RT1011_BAT_GAIN_9			0x0541
128 #define RT1011_BAT_GAIN_10			0x0542
129 #define RT1011_BAT_GAIN_11			0x0543
130 #define RT1011_BAT_RT_THMAX_1		0x0544
131 #define RT1011_BAT_RT_THMAX_2		0x0545
132 #define RT1011_BAT_RT_THMAX_3		0x0546
133 #define RT1011_BAT_RT_THMAX_4		0x0547
134 #define RT1011_BAT_RT_THMAX_5		0x0548
135 #define RT1011_BAT_RT_THMAX_6		0x0549
136 #define RT1011_BAT_RT_THMAX_7		0x054a
137 #define RT1011_BAT_RT_THMAX_8		0x054b
138 #define RT1011_BAT_RT_THMAX_9		0x054c
139 #define RT1011_BAT_RT_THMAX_10		0x054d
140 #define RT1011_BAT_RT_THMAX_11		0x054e
141 #define RT1011_BAT_RT_THMAX_12		0x054f
142 #define RT1011_SPREAD_SPECTURM		0x0568
143 #define RT1011_PRO_GAIN_MODE		0x056a
144 #define RT1011_RT_DRC_CROSS			0x0600
145 #define RT1011_RT_DRC_HB_1			0x0611
146 #define RT1011_RT_DRC_HB_2			0x0612
147 #define RT1011_RT_DRC_HB_3			0x0613
148 #define RT1011_RT_DRC_HB_4			0x0614
149 #define RT1011_RT_DRC_HB_5			0x0615
150 #define RT1011_RT_DRC_HB_6			0x0616
151 #define RT1011_RT_DRC_HB_7			0x0617
152 #define RT1011_RT_DRC_HB_8			0x0618
153 #define RT1011_RT_DRC_BB_1			0x0621
154 #define RT1011_RT_DRC_BB_2			0x0622
155 #define RT1011_RT_DRC_BB_3			0x0623
156 #define RT1011_RT_DRC_BB_4			0x0624
157 #define RT1011_RT_DRC_BB_5			0x0625
158 #define RT1011_RT_DRC_BB_6			0x0626
159 #define RT1011_RT_DRC_BB_7			0x0627
160 #define RT1011_RT_DRC_BB_8			0x0628
161 #define RT1011_RT_DRC_POS_1			0x0631
162 #define RT1011_RT_DRC_POS_2			0x0632
163 #define RT1011_RT_DRC_POS_3			0x0633
164 #define RT1011_RT_DRC_POS_4			0x0634
165 #define RT1011_RT_DRC_POS_5			0x0635
166 #define RT1011_RT_DRC_POS_6			0x0636
167 #define RT1011_RT_DRC_POS_7			0x0637
168 #define RT1011_RT_DRC_POS_8			0x0638
169 #define RT1011_CROSS_BQ_SET_1		0x0702
170 #define RT1011_CROSS_BQ_SET_2		0x0704
171 #define RT1011_BQ_SET_0				0x0706
172 #define RT1011_BQ_SET_1				0x0708
173 #define RT1011_BQ_SET_2				0x070a
174 #define RT1011_BQ_PRE_GAIN_28_16	0x0710
175 #define RT1011_BQ_PRE_GAIN_15_0		0x0711
176 #define RT1011_BQ_POST_GAIN_28_16	0x0712
177 #define RT1011_BQ_POST_GAIN_15_0	0x0713
178 
179 #define RT1011_BQ_H0_28_16					0x0720
180 #define RT1011_BQ_A2_15_0						0x0729
181 #define RT1011_BQ_1_H0_28_16					0x0730
182 #define RT1011_BQ_1_A2_15_0					0x0739
183 #define RT1011_BQ_2_H0_28_16					0x0740
184 #define RT1011_BQ_2_A2_15_0					0x0749
185 #define RT1011_BQ_3_H0_28_16					0x0750
186 #define RT1011_BQ_3_A2_15_0					0x0759
187 #define RT1011_BQ_4_H0_28_16					0x0760
188 #define RT1011_BQ_4_A2_15_0					0x0769
189 #define RT1011_BQ_5_H0_28_16					0x0770
190 #define RT1011_BQ_5_A2_15_0					0x0779
191 #define RT1011_BQ_6_H0_28_16					0x0780
192 #define RT1011_BQ_6_A2_15_0					0x0789
193 #define RT1011_BQ_7_H0_28_16					0x0790
194 #define RT1011_BQ_7_A2_15_0					0x0799
195 #define RT1011_BQ_8_H0_28_16					0x07a0
196 #define RT1011_BQ_8_A2_15_0					0x07a9
197 #define RT1011_BQ_9_H0_28_16					0x07b0
198 #define RT1011_BQ_9_A2_15_0					0x07b9
199 #define RT1011_BQ_10_H0_28_16				0x07c0
200 #define RT1011_BQ_10_A2_15_0					0x07c9
201 #define RT1011_TEST_PAD_STATUS				0x1000
202 #define RT1011_SYSTEM_RESET_1				0x1007
203 #define RT1011_SYSTEM_RESET_2				0x1008
204 #define RT1011_SYSTEM_RESET_3				0x1009
205 #define RT1011_ADCDAT_OUT_SOURCE			0x100D
206 #define RT1011_PLL_INTERNAL_SET				0x1010
207 #define RT1011_TEST_OUT_1						0x1020
208 #define RT1011_TEST_OUT_3						0x1024
209 #define RT1011_DC_CALIB_CLASSD_1			0x1200
210 #define RT1011_DC_CALIB_CLASSD_2			0x1202
211 #define RT1011_DC_CALIB_CLASSD_3			0x1204
212 #define RT1011_DC_CALIB_CLASSD_5			0x1208
213 #define RT1011_DC_CALIB_CLASSD_6			0x120a
214 #define RT1011_DC_CALIB_CLASSD_7			0x120c
215 #define RT1011_DC_CALIB_CLASSD_8			0x120e
216 #define RT1011_DC_CALIB_CLASSD_10			0x1212
217 #define RT1011_CLASSD_INTERNAL_SET_1		0x1300
218 #define RT1011_CLASSD_INTERNAL_SET_3		0x1304
219 #define RT1011_CLASSD_INTERNAL_SET_8		0x130c
220 #define RT1011_VREF_LV_1						0x131a
221 #define RT1011_SMART_BOOST_TIMING_1		0x1322
222 #define RT1011_SMART_BOOST_TIMING_36		0x1349
223 #define RT1011_SINE_GEN_REG_1				0x1500
224 #define RT1011_SINE_GEN_REG_2				0x1502
225 #define RT1011_SINE_GEN_REG_3				0x1504
226 #define RT1011_STP_INITIAL_RS_TEMP			0x1510
227 #define RT1011_STP_CALIB_RS_TEMP			0x152a
228 #define RT1011_INIT_RECIPROCAL_REG_24_16				0x1538
229 #define RT1011_INIT_RECIPROCAL_REG_15_0				0x1539
230 #define RT1011_STP_INITIAL_RESISTANCE_TEMP				0x153c
231 #define RT1011_STP_ALPHA_RECIPROCAL_MSB				0x153e
232 #define RT1011_SPK_RESISTANCE_1				0x1544
233 #define RT1011_SPK_RESISTANCE_2				0x1546
234 #define RT1011_SPK_THERMAL					0x1548
235 #define RT1011_STP_OTP_TH						0x1552
236 #define RT1011_ALC_BK_GAIN_O					0x1554
237 #define RT1011_ALC_BK_GAIN_O_PRE			0x1556
238 #define RT1011_SPK_DC_O_23_16				0x155a
239 #define RT1011_SPK_DC_O_15_0					0x155c
240 #define RT1011_INIT_RECIPROCAL_SYN_24_16	0x1560
241 #define RT1011_INIT_RECIPROCAL_SYN_15_0	0x1562
242 #define RT1011_STP_BQ_1_A1_L_28_16			0x1570
243 #define RT1011_STP_BQ_1_H0_R_15_0			0x1583
244 #define RT1011_STP_BQ_2_A1_L_28_16			0x1590
245 #define RT1011_SPK_EXCURSION_23_16			0x15be
246 #define RT1011_SPK_EXCURSION_15_0			0x15bf
247 #define RT1011_SEP_MAIN_OUT_23_16			0x15c0
248 #define RT1011_SEP_MAIN_OUT_15_0			0x15c1
249 #define RT1011_SEP_RE_REG_15_0				0x15f9
250 #define RT1011_DRC_CF_PARAMS_1				0x1600
251 #define RT1011_DRC_CF_PARAMS_12				0x160b
252 #define RT1011_ALC_DRC_HB_INTERNAL_1		0x1611
253 #define RT1011_ALC_DRC_HB_INTERNAL_5		0x1615
254 #define RT1011_ALC_DRC_HB_INTERNAL_6		0x1616
255 #define RT1011_ALC_DRC_HB_INTERNAL_7		0x1617
256 #define RT1011_ALC_DRC_BB_INTERNAL_1		0x1621
257 #define RT1011_ALC_DRC_BB_INTERNAL_5		0x1625
258 #define RT1011_ALC_DRC_BB_INTERNAL_6		0x1626
259 #define RT1011_ALC_DRC_BB_INTERNAL_7		0x1627
260 #define RT1011_ALC_DRC_POS_INTERNAL_1		0x1631
261 #define RT1011_ALC_DRC_POS_INTERNAL_5		0x1635
262 #define RT1011_ALC_DRC_POS_INTERNAL_6		0x1636
263 #define RT1011_ALC_DRC_POS_INTERNAL_7		0x1637
264 #define RT1011_ALC_DRC_POS_INTERNAL_8		0x1638
265 #define RT1011_ALC_DRC_POS_INTERNAL_9		0x163a
266 #define RT1011_ALC_DRC_POS_INTERNAL_10	0x163c
267 #define RT1011_ALC_DRC_POS_INTERNAL_11	0x163e
268 #define RT1011_BQ_1_PARAMS_CHECK_5			0x1648
269 #define RT1011_BQ_2_PARAMS_CHECK_1			0x1650
270 #define RT1011_BQ_2_PARAMS_CHECK_5			0x1658
271 #define RT1011_BQ_3_PARAMS_CHECK_1			0x1660
272 #define RT1011_BQ_3_PARAMS_CHECK_5			0x1668
273 #define RT1011_BQ_4_PARAMS_CHECK_1			0x1670
274 #define RT1011_BQ_4_PARAMS_CHECK_5			0x1678
275 #define RT1011_BQ_5_PARAMS_CHECK_1			0x1680
276 #define RT1011_BQ_5_PARAMS_CHECK_5			0x1688
277 #define RT1011_BQ_6_PARAMS_CHECK_1			0x1690
278 #define RT1011_BQ_6_PARAMS_CHECK_5			0x1698
279 #define RT1011_BQ_7_PARAMS_CHECK_1			0x1700
280 #define RT1011_BQ_7_PARAMS_CHECK_5			0x1708
281 #define RT1011_BQ_8_PARAMS_CHECK_1			0x1710
282 #define RT1011_BQ_8_PARAMS_CHECK_5			0x1718
283 #define RT1011_BQ_9_PARAMS_CHECK_1			0x1720
284 #define RT1011_BQ_9_PARAMS_CHECK_5			0x1728
285 #define RT1011_BQ_10_PARAMS_CHECK_1		0x1730
286 #define RT1011_BQ_10_PARAMS_CHECK_5		0x1738
287 #define RT1011_IRQ_1							0x173a
288 #define RT1011_PART_NUMBER_EFUSE			0x173e
289 #define RT1011_EFUSE_CONTROL_1				0x17bb
290 #define RT1011_EFUSE_CONTROL_2				0x17bd
291 #define RT1011_EFUSE_MATCH_DONE				0x17cb
292 #define RT1011_EFUSE_ADC_OFFSET_18_16				0x17e5
293 #define RT1011_EFUSE_ADC_OFFSET_15_0				0x17e7
294 #define RT1011_EFUSE_DAC_OFFSET_G0_20_16				0x17e9
295 #define RT1011_EFUSE_DAC_OFFSET_G0_15_0				0x17eb
296 #define RT1011_EFUSE_DAC_OFFSET_G1_20_16				0x17ed
297 #define RT1011_EFUSE_DAC_OFFSET_G1_15_0				0x17ef
298 #define RT1011_EFUSE_READ_R0_3_15_0		0x1803
299 #define RT1011_MAX_REG				0x1803
300 #define RT1011_REG_DISP_LEN 23
301 
302 
303 /* CLOCK-2 (0x0004) */
304 #define RT1011_FS_SYS_PRE_MASK			(0x3 << 14)
305 #define RT1011_FS_SYS_PRE_SFT			14
306 #define RT1011_FS_SYS_PRE_MCLK			(0x0 << 14)
307 #define RT1011_FS_SYS_PRE_BCLK			(0x1 << 14)
308 #define RT1011_FS_SYS_PRE_PLL1			(0x2 << 14)
309 #define RT1011_FS_SYS_PRE_RCCLK			(0x3 << 14)
310 #define RT1011_PLL1_SRC_MASK			(0x1 << 13)
311 #define RT1011_PLL1_SRC_SFT			13
312 #define RT1011_PLL1_SRC_PLL2			(0x0 << 13)
313 #define RT1011_PLL1_SRC_BCLK			(0x1 << 13)
314 #define RT1011_PLL2_SRC_MASK			(0x1 << 12)
315 #define RT1011_PLL2_SRC_SFT			12
316 #define RT1011_PLL2_SRC_MCLK			(0x0 << 12)
317 #define RT1011_PLL2_SRC_RCCLK			(0x1 << 12)
318 #define RT1011_PLL2_SRC_DIV_MASK			(0x3 << 10)
319 #define RT1011_PLL2_SRC_DIV_SFT			10
320 #define RT1011_SRCIN_DIV_MASK			(0x3 << 8)
321 #define RT1011_SRCIN_DIV_SFT			8
322 #define RT1011_FS_SYS_DIV_MASK			(0x7 << 4)
323 #define RT1011_FS_SYS_DIV_SFT			4
324 
325 /* PLL-1 (0x000a) */
326 #define RT1011_PLL1_QM_MASK			(0xf << 12)
327 #define RT1011_PLL1_QM_SFT			12
328 #define RT1011_PLL1_BPM_MASK			(0x1 << 11)
329 #define RT1011_PLL1_BPM_SFT			11
330 #define RT1011_PLL1_BPM			(0x1 << 11)
331 #define RT1011_PLL1_QN_MASK			(0x1ff << 0)
332 #define RT1011_PLL1_QN_SFT			0
333 
334 /* PLL-2 (0x000c) */
335 #define RT1011_PLL2_BPK_MASK			(0x1 << 5)
336 #define RT1011_PLL2_BPK_SFT			5
337 #define RT1011_PLL2_BPK			(0x1 << 5)
338 #define RT1011_PLL2_QK_MASK			(0x1f << 0)
339 #define RT1011_PLL2_QK_SFT			0
340 
341 /* Clock Detect (0x0020) */
342 #define RT1011_EN_MCLK_DET_MASK			(0x1 << 15)
343 #define RT1011_EN_MCLK_DET_SFT			15
344 #define RT1011_EN_MCLK_DET			(0x1 << 15)
345 
346 /* DAC Setting-2 (0x0104) */
347 #define RT1011_EN_CKGEN_DAC_MASK			(0x1 << 13)
348 #define RT1011_EN_CKGEN_DAC_SFT			13
349 #define RT1011_EN_CKGEN_DAC			(0x1 << 13)
350 
351 /* DAC Setting-3 (0x0106) */
352 #define RT1011_DA_MUTE_EN_MASK			(0x1 << 15)
353 #define RT1011_DA_MUTE_EN_SFT			15
354 
355 /* ADC Setting-5 (0x0110) */
356 #define RT1011_AD_EN_CKGEN_ADC_MASK			(0x1 << 9)
357 #define RT1011_AD_EN_CKGEN_ADC_SFT			9
358 #define RT1011_AD_EN_CKGEN_ADC			(0x1 << 9)
359 
360 /* TDM Total Setting (0x0111) */
361 #define RT1011_I2S_TDM_MS_MASK			(0x1 << 14)
362 #define RT1011_I2S_TDM_MS_SFT			14
363 #define RT1011_I2S_TDM_MS_S			(0x0 << 14)
364 #define RT1011_I2S_TDM_MS_M			(0x1 << 14)
365 #define RT1011_I2S_TX_DL_MASK			(0x7 << 8)
366 #define RT1011_I2S_TX_DL_SFT			8
367 #define RT1011_I2S_TX_DL_16B			(0x0 << 8)
368 #define RT1011_I2S_TX_DL_20B			(0x1 << 8)
369 #define RT1011_I2S_TX_DL_24B			(0x2 << 8)
370 #define RT1011_I2S_TX_DL_32B			(0x3 << 8)
371 #define RT1011_I2S_TX_DL_8B			(0x4 << 8)
372 #define RT1011_I2S_RX_DL_MASK			(0x7 << 5)
373 #define RT1011_I2S_RX_DL_SFT			5
374 #define RT1011_I2S_RX_DL_16B			(0x0 << 5)
375 #define RT1011_I2S_RX_DL_20B			(0x1 << 5)
376 #define RT1011_I2S_RX_DL_24B			(0x2 << 5)
377 #define RT1011_I2S_RX_DL_32B			(0x3 << 5)
378 #define RT1011_I2S_RX_DL_8B			(0x4 << 5)
379 #define RT1011_ADCDAT1_PIN_CONFIG			(0x1 << 4)
380 #define RT1011_ADCDAT1_OUTPUT			(0x0 << 4)
381 #define RT1011_ADCDAT1_INPUT			(0x1 << 4)
382 #define RT1011_ADCDAT2_PIN_CONFIG			(0x1 << 3)
383 #define RT1011_ADCDAT2_OUTPUT			(0x0 << 3)
384 #define RT1011_ADCDAT2_INPUT			(0x1 << 3)
385 #define RT1011_I2S_TDM_DF_MASK			(0x7 << 0)
386 #define RT1011_I2S_TDM_DF_SFT			0
387 #define RT1011_I2S_TDM_DF_I2S			(0x0)
388 #define RT1011_I2S_TDM_DF_LEFT			(0x1)
389 #define RT1011_I2S_TDM_DF_PCM_A			(0x2)
390 #define RT1011_I2S_TDM_DF_PCM_B			(0x3)
391 #define RT1011_I2S_TDM_DF_PCM_A_N			(0x6)
392 #define RT1011_I2S_TDM_DF_PCM_B_N			(0x7)
393 
394 /* TDM_tcon Setting (0x0112) */
395 #define RT1011_TCON_DF_MASK			(0x7 << 13)
396 #define RT1011_TCON_DF_SFT			13
397 #define RT1011_TCON_DF_I2S			(0x0 << 13)
398 #define RT1011_TCON_DF_LEFT			(0x1 << 13)
399 #define RT1011_TCON_DF_PCM_A			(0x2 << 13)
400 #define RT1011_TCON_DF_PCM_B			(0x3 << 13)
401 #define RT1011_TCON_DF_PCM_A_N			(0x6 << 13)
402 #define RT1011_TCON_DF_PCM_B_N			(0x7 << 13)
403 #define RT1011_TCON_BCLK_SEL_MASK			(0x3 << 10)
404 #define RT1011_TCON_BCLK_SEL_SFT			10
405 #define RT1011_TCON_BCLK_SEL_32FS			(0x0 << 10)
406 #define RT1011_TCON_BCLK_SEL_64FS			(0x1 << 10)
407 #define RT1011_TCON_BCLK_SEL_128FS			(0x2 << 10)
408 #define RT1011_TCON_BCLK_SEL_256FS			(0x3 << 10)
409 #define RT1011_TCON_CH_LEN_MASK			(0x3 << 5)
410 #define RT1011_TCON_CH_LEN_SFT			5
411 #define RT1011_TCON_CH_LEN_16B			(0x0 << 5)
412 #define RT1011_TCON_CH_LEN_20B			(0x1 << 5)
413 #define RT1011_TCON_CH_LEN_24B			(0x2 << 5)
414 #define RT1011_TCON_CH_LEN_32B			(0x3 << 5)
415 #define RT1011_TCON_BCLK_MST_MASK			(0x1 << 4)
416 #define RT1011_TCON_BCLK_MST_SFT			4
417 #define RT1011_TCON_BCLK_MST_INV		(0x1 << 4)
418 
419 /* TDM1 Setting-1 (0x0114) */
420 #define RT1011_TDM_INV_BCLK_MASK			(0x1 << 15)
421 #define RT1011_TDM_INV_BCLK_SFT			15
422 #define RT1011_TDM_INV_BCLK		(0x1 << 15)
423 #define RT1011_I2S_CH_TX_MASK			(0x3 << 10)
424 #define RT1011_I2S_CH_TX_SFT			10
425 #define RT1011_I2S_TX_2CH			(0x0 << 10)
426 #define RT1011_I2S_TX_4CH			(0x1 << 10)
427 #define RT1011_I2S_TX_6CH			(0x2 << 10)
428 #define RT1011_I2S_TX_8CH			(0x3 << 10)
429 #define RT1011_I2S_CH_RX_MASK			(0x3 << 8)
430 #define RT1011_I2S_CH_RX_SFT			8
431 #define RT1011_I2S_RX_2CH			(0x0 << 8)
432 #define RT1011_I2S_RX_4CH			(0x1 << 8)
433 #define RT1011_I2S_RX_6CH			(0x2 << 8)
434 #define RT1011_I2S_RX_8CH			(0x3 << 8)
435 #define RT1011_I2S_LR_CH_SEL_MASK			(0x1 << 7)
436 #define RT1011_I2S_LR_CH_SEL_SFT			7
437 #define RT1011_I2S_LEFT_CH_SEL			(0x0 << 7)
438 #define RT1011_I2S_RIGHT_CH_SEL			(0x1 << 7)
439 #define RT1011_I2S_CH_TX_LEN_MASK			(0x7 << 4)
440 #define RT1011_I2S_CH_TX_LEN_SFT			4
441 #define RT1011_I2S_CH_TX_LEN_16B			(0x0 << 4)
442 #define RT1011_I2S_CH_TX_LEN_20B			(0x1 << 4)
443 #define RT1011_I2S_CH_TX_LEN_24B			(0x2 << 4)
444 #define RT1011_I2S_CH_TX_LEN_32B			(0x3 << 4)
445 #define RT1011_I2S_CH_TX_LEN_8B			(0x4 << 4)
446 #define RT1011_I2S_CH_RX_LEN_MASK			(0x7 << 0)
447 #define RT1011_I2S_CH_RX_LEN_SFT			0
448 #define RT1011_I2S_CH_RX_LEN_16B			(0x0 << 0)
449 #define RT1011_I2S_CH_RX_LEN_20B			(0x1 << 0)
450 #define RT1011_I2S_CH_RX_LEN_24B			(0x2 << 0)
451 #define RT1011_I2S_CH_RX_LEN_32B			(0x3 << 0)
452 #define RT1011_I2S_CH_RX_LEN_8B			(0x4 << 0)
453 
454 /* TDM1 Setting-2 (0x0116) */
455 #define RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK			(0x7 << 13)
456 #define RT1011_TDM_I2S_DOCK_ADCDAT_2CH			(0x1 << 13)
457 #define RT1011_TDM_I2S_DOCK_ADCDAT_4CH			(0x3 << 13)
458 #define RT1011_TDM_I2S_DOCK_ADCDAT_6CH			(0x5 << 13)
459 #define RT1011_TDM_I2S_DOCK_ADCDAT_8CH			(0x7 << 13)
460 #define RT1011_TDM_I2S_DOCK_EN_1_MASK			(0x1 << 3)
461 #define RT1011_TDM_I2S_DOCK_EN_1_SFT			3
462 #define RT1011_TDM_I2S_DOCK_EN_1		(0x1 << 3)
463 #define RT1011_TDM_ADCDAT1_DATA_LOCATION			(0x7 << 0)
464 
465 /* TDM1 Setting-3 (0x0118) */
466 #define RT1011_TDM_I2S_RX_ADC1_1_MASK			(0x3 << 6)
467 #define RT1011_TDM_I2S_RX_ADC2_1_MASK			(0x3 << 4)
468 #define RT1011_TDM_I2S_RX_ADC3_1_MASK			(0x3 << 2)
469 #define RT1011_TDM_I2S_RX_ADC4_1_MASK			(0x3 << 0)
470 #define RT1011_TDM_I2S_RX_ADC1_1_LL			(0x2 << 6)
471 #define RT1011_TDM_I2S_RX_ADC2_1_LL			(0x2 << 4)
472 #define RT1011_TDM_I2S_RX_ADC3_1_LL			(0x2 << 2)
473 #define RT1011_TDM_I2S_RX_ADC4_1_LL			(0x2 << 0)
474 
475 /* TDM1 Setting-4 (0x011a) */
476 #define RT1011_TDM_I2S_TX_L_DAC1_1_MASK			(0x7 << 12)
477 #define RT1011_TDM_I2S_TX_R_DAC1_1_MASK			(0x7 << 8)
478 #define RT1011_TDM_I2S_TX_L_DAC1_1_SFT 12
479 #define RT1011_TDM_I2S_TX_R_DAC1_1_SFT 8
480 
481 /* TDM2 Setting-2 (0x0120) */
482 #define RT1011_TDM_I2S_DOCK_ADCDAT_LEN_2_MASK			(0x7 << 13)
483 #define RT1011_TDM_I2S_DOCK_EN_2_MASK			(0x1 << 3)
484 #define RT1011_TDM_I2S_DOCK_EN_2_SFT			3
485 #define RT1011_TDM_I2S_DOCK_EN_2		(0x1 << 3)
486 
487 /* MIXER 1 (0x0300) */
488 #define RT1011_MIXER_MUTE_MIX_I_MASK			(0x1 << 15)
489 #define RT1011_MIXER_MUTE_MIX_I_SFT			15
490 #define RT1011_MIXER_MUTE_MIX_I		(0x1 << 15)
491 #define RT1011_MIXER_MUTE_SUM_I_MASK			(0x1 << 14)
492 #define RT1011_MIXER_MUTE_SUM_I_SFT			14
493 #define RT1011_MIXER_MUTE_SUM_I		(0x1 << 14)
494 #define RT1011_MIXER_MUTE_MIX_V_MASK			(0x1 << 7)
495 #define RT1011_MIXER_MUTE_MIX_V_SFT			7
496 #define RT1011_MIXER_MUTE_MIX_V		(0x1 << 7)
497 #define RT1011_MIXER_MUTE_SUM_V_MASK			(0x1 << 6)
498 #define RT1011_MIXER_MUTE_SUM_V_SFT			6
499 #define RT1011_MIXER_MUTE_SUM_V		(0x1 << 6)
500 
501 /* Analog Temperature Sensor (0x0316) */
502 #define RT1011_POW_TEMP_REG				(0x1 << 2)
503 #define RT1011_POW_TEMP_REG_BIT			2
504 
505 /* POWER-1 (0x0322) */
506 #define RT1011_POW_LDO2				(0x1 << 15)
507 #define RT1011_POW_LDO2_BIT			15
508 #define RT1011_POW_DAC				(0x1 << 14)
509 #define RT1011_POW_DAC_BIT			14
510 #define RT1011_POW_CLK12M				(0x1 << 13)
511 #define RT1011_POW_CLK12M_BIT		13
512 #define RT1011_POW_TEMP				(0x1 << 12)
513 #define RT1011_POW_TEMP_BIT			12
514 #define RT1011_POW_ISENSE_SPK				(0x1 << 7)
515 #define RT1011_POW_ISENSE_SPK_BIT			7
516 #define RT1011_POW_LPF_SPK				(0x1 << 6)
517 #define RT1011_POW_LPF_SPK_BIT			6
518 #define RT1011_POW_VSENSE_SPK				(0x1 << 5)
519 #define RT1011_POW_VSENSE_SPK_BIT			5
520 #define RT1011_POW_TWO_BATTERY_SPK				(0x1 << 4)
521 #define RT1011_POW_TWO_BATTERY_SPK_BIT			4
522 
523 /* POWER-2 (0x0324) */
524 #define RT1011_PLLEN				(0x1 << 2)
525 #define RT1011_PLLEN_BIT			2
526 #define RT1011_POW_BG				(0x1 << 1)
527 #define RT1011_POW_BG_BIT			1
528 #define RT1011_POW_BG_MBIAS_LV				(0x1 << 0)
529 #define RT1011_POW_BG_MBIAS_LV_BIT		0
530 
531 /* POWER-3 (0x0326) */
532 #define RT1011_POW_DET_SPKVDD			(0x1 << 15)
533 #define RT1011_POW_DET_SPKVDD_BIT		15
534 #define RT1011_POW_DET_VBAT				(0x1 << 14)
535 #define RT1011_POW_DET_VBAT_BIT			14
536 #define RT1011_POW_FC						(0x1 << 13)
537 #define RT1011_POW_FC_BIT					13
538 #define RT1011_POW_MBIAS_LV				(0x1 << 12)
539 #define RT1011_POW_MBIAS_LV_BIT			12
540 #define RT1011_POW_ADC_I					(0x1 << 11)
541 #define RT1011_POW_ADC_I_BIT				11
542 #define RT1011_POW_ADC_V					(0x1 << 10)
543 #define RT1011_POW_ADC_V_BIT				10
544 #define RT1011_POW_ADC_T					(0x1 << 9)
545 #define RT1011_POW_ADC_T_BIT				9
546 #define RT1011_POWD_ADC_T					(0x1 << 8)
547 #define RT1011_POWD_ADC_T_BIT			8
548 #define RT1011_POW_MIX_I					(0x1 << 7)
549 #define RT1011_POW_MIX_I_BIT				7
550 #define RT1011_POW_MIX_V					(0x1 << 6)
551 #define RT1011_POW_MIX_V_BIT				6
552 #define RT1011_POW_SUM_I					(0x1 << 5)
553 #define RT1011_POW_SUM_I_BIT				5
554 #define RT1011_POW_SUM_V					(0x1 << 4)
555 #define RT1011_POW_SUM_V_BIT				4
556 #define RT1011_POW_MIX_T					(0x1 << 2)
557 #define RT1011_POW_MIX_T_BIT				2
558 #define RT1011_BYPASS_MIX_T				(0x1 << 1)
559 #define RT1011_BYPASS_MIX_T_BIT			1
560 #define RT1011_POW_VREF_LV				(0x1 << 0)
561 #define RT1011_POW_VREF_LV_BIT			0
562 
563 /* POWER-4 (0x0328) */
564 #define RT1011_POW_EN_SWR			(0x1 << 12)
565 #define RT1011_POW_EN_SWR_BIT		12
566 #define RT1011_POW_EN_PASS_BGOK_SWR			(0x1 << 10)
567 #define RT1011_POW_EN_PASS_BGOK_SWR_BIT		10
568 #define RT1011_POW_EN_PASS_VPOK_SWR			(0x1 << 9)
569 #define RT1011_POW_EN_PASS_VPOK_SWR_BIT		9
570 
571 /* POWER-9 (0x032d) */
572 #define RT1011_POW_SDB_REG_MASK			(0x1 << 9)
573 #define RT1011_POW_SDB_REG_BIT		9
574 #define RT1011_POW_SDB_REG		(0x1 << 9)
575 #define RT1011_POW_SEL_SDB_MODE_MASK			(0x1 << 6)
576 #define RT1011_POW_SEL_SDB_MODE_BIT		6
577 #define RT1011_POW_SEL_SDB_MODE		(0x1 << 6)
578 #define RT1011_POW_MNL_SDB_MASK			(0x1 << 5)
579 #define RT1011_POW_MNL_SDB_BIT		5
580 #define RT1011_POW_MNL_SDB		(0x1 << 5)
581 
582 /* SPK Protection-Temperature Protection (0x050c) */
583 #define RT1011_STP_EN_MASK			(0x1 << 15)
584 #define RT1011_STP_EN_BIT		15
585 #define RT1011_STP_EN		(0x1 << 15)
586 #define RT1011_STP_RS_CLB_EN_MASK			(0x1 << 14)
587 #define RT1011_STP_RS_CLB_EN_BIT		14
588 #define RT1011_STP_RS_CLB_EN		(0x1 << 14)
589 
590 /* SPK Protection-Temperature Protection-4 (0x0510) */
591 #define RT1011_STP_R0_SELECT_MASK			(0x3 << 6)
592 #define RT1011_STP_R0_SELECT_EFUSE			(0x0 << 6)
593 #define RT1011_STP_R0_SELECT_START_VAL	(0x1 << 6)
594 #define RT1011_STP_R0_SELECT_REG			(0x2 << 6)
595 #define RT1011_STP_R0_SELECT_FORCE_ZERO	(0x3 << 6)
596 
597 /* SPK Protection-Temperature Protection-6 (0x0512) */
598 #define RT1011_STP_R0_EN_MASK			(0x1 << 7)
599 #define RT1011_STP_R0_EN_BIT		7
600 #define RT1011_STP_R0_EN		(0x1 << 7)
601 #define RT1011_STP_T0_EN_MASK			(0x1 << 6)
602 #define RT1011_STP_T0_EN_BIT		6
603 #define RT1011_STP_T0_EN		(0x1 << 6)
604 
605 /* Cross Biquad Setting-1 (0x0702) */
606 #define RT1011_MONO_LR_SEL_MASK			(0x3 << 5)
607 #define RT1011_MONO_L_CHANNEL			(0x0 << 5)
608 #define RT1011_MONO_R_CHANNEL			(0x1 << 5)
609 #define RT1011_MONO_LR_MIX_CHANNEL			(0x2 << 5)
610 
611 /* ClassD Internal Setting-1 (0x1300) */
612 #define RT1011_DRIVER_READY_SPK			(0x1 << 12)
613 #define RT1011_DRIVER_READY_SPK_BIT		12
614 #define RT1011_RECV_MODE_SPK_MASK			(0x1 << 5)
615 #define RT1011_SPK_MODE			(0x0 << 5)
616 #define RT1011_RECV_MODE			(0x1 << 5)
617 #define RT1011_RECV_MODE_SPK_BIT		5
618 
619 /* ClassD Internal Setting-3 (0x1304) */
620 #define RT1011_REG_GAIN_CLASSD_RI_SPK_MASK			(0x7 << 12)
621 #define RT1011_REG_GAIN_CLASSD_RI_410K (0x0 << 12)
622 #define RT1011_REG_GAIN_CLASSD_RI_95K (0x1 << 12)
623 #define RT1011_REG_GAIN_CLASSD_RI_82P5K (0x2 << 12)
624 #define RT1011_REG_GAIN_CLASSD_RI_72P5K (0x3 << 12)
625 #define RT1011_REG_GAIN_CLASSD_RI_62P5K (0x4 << 12)
626 
627 /* ClassD Internal Setting-8 (0x130c) */
628 #define RT1011_TM_PORPVDD_SPK		(0x1 << 1)
629 #define RT1011_TM_PORPVDD_SPK_BIT		1
630 
631 /* SPK Protection-Temperature Protection-SINE_GEN_REG-1 (0x1500) */
632 #define RT1011_STP_SIN_GEN_EN_MASK (0x1 << 13)
633 #define RT1011_STP_SIN_GEN_EN		(0x1 << 13)
634 #define RT1011_STP_SIN_GEN_EN_BIT		13
635 
636 
637 /* System Clock Source */
638 enum {
639 	RT1011_FS_SYS_PRE_S_MCLK,
640 	RT1011_FS_SYS_PRE_S_BCLK,
641 	RT1011_FS_SYS_PRE_S_PLL1,
642 	RT1011_FS_SYS_PRE_S_RCCLK,	/* 12M Hz */
643 };
644 
645 /* PLL Source 1/2 */
646 enum {
647 	RT1011_PLL1_S_BCLK,
648 	RT1011_PLL2_S_MCLK,
649 	RT1011_PLL2_S_RCCLK,	/* 12M Hz */
650 };
651 
652 enum {
653 	RT1011_AIF1,
654 	RT1011_AIFS
655 };
656 
657 enum {
658 	RT1011_I2S_REF_NONE,
659 	RT1011_I2S_REF_LEFT_CH,
660 	RT1011_I2S_REF_RIGHT_CH,
661 };
662 
663 /* BiQual & DRC related settings */
664 #define RT1011_BQ_DRC_NUM 128
665 struct rt1011_bq_drc_params {
666 	unsigned short val;
667 	unsigned short reg;
668 #ifdef CONFIG_64BIT
669 	unsigned int reserved;
670 #endif
671 };
672 enum {
673 	RT1011_ADVMODE_INITIAL_SET,
674 	RT1011_ADVMODE_SEP_BQ_COEFF,
675 	RT1011_ADVMODE_EQ_BQ_COEFF,
676 	RT1011_ADVMODE_BQ_UI_COEFF,
677 	RT1011_ADVMODE_SMARTBOOST_COEFF,
678 	RT1011_ADVMODE_NUM,
679 };
680 
681 struct rt1011_priv {
682 	struct snd_soc_component *component;
683 	struct regmap *regmap;
684 	struct work_struct cali_work;
685 	struct rt1011_bq_drc_params **bq_drc_params;
686 
687 	int sysclk;
688 	int sysclk_src;
689 	int lrck;
690 	int bclk;
691 	int id;
692 
693 	int pll_src;
694 	int pll_in;
695 	int pll_out;
696 
697 	int bq_drc_set;
698 	unsigned int r0_reg, cali_done;
699 	unsigned int r0_calib, temperature_calib;
700 	int recv_spk_mode;
701 	int i2s_ref;
702 };
703 
704 #endif		/* end of _RT1011_H_ */
705