1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2011 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #ifndef _IXGBE_H_ 29 #define _IXGBE_H_ 30 31 #include <linux/bitops.h> 32 #include <linux/types.h> 33 #include <linux/pci.h> 34 #include <linux/netdevice.h> 35 #include <linux/cpumask.h> 36 #include <linux/aer.h> 37 #include <linux/if_vlan.h> 38 39 #include "ixgbe_type.h" 40 #include "ixgbe_common.h" 41 #include "ixgbe_dcb.h" 42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) 43 #define IXGBE_FCOE 44 #include "ixgbe_fcoe.h" 45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ 46 #ifdef CONFIG_IXGBE_DCA 47 #include <linux/dca.h> 48 #endif 49 50 /* common prefix used by pr_<> macros */ 51 #undef pr_fmt 52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 53 54 /* TX/RX descriptor defines */ 55 #define IXGBE_DEFAULT_TXD 512 56 #define IXGBE_MAX_TXD 4096 57 #define IXGBE_MIN_TXD 64 58 59 #define IXGBE_DEFAULT_RXD 512 60 #define IXGBE_MAX_RXD 4096 61 #define IXGBE_MIN_RXD 64 62 63 /* flow control */ 64 #define IXGBE_MIN_FCRTL 0x40 65 #define IXGBE_MAX_FCRTL 0x7FF80 66 #define IXGBE_MIN_FCRTH 0x600 67 #define IXGBE_MAX_FCRTH 0x7FFF0 68 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 69 #define IXGBE_MIN_FCPAUSE 0 70 #define IXGBE_MAX_FCPAUSE 0xFFFF 71 72 /* Supported Rx Buffer Sizes */ 73 #define IXGBE_RXBUFFER_512 512 /* Used for packet split */ 74 #define IXGBE_RXBUFFER_2048 2048 75 #define IXGBE_RXBUFFER_4096 4096 76 #define IXGBE_RXBUFFER_8192 8192 77 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 78 79 /* 80 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we 81 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, 82 * this adds up to 512 bytes of extra data meaning the smallest allocation 83 * we could have is 1K. 84 * i.e. RXBUFFER_512 --> size-1024 slab 85 */ 86 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512 87 88 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 89 90 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 91 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 92 93 #define IXGBE_TX_FLAGS_CSUM (u32)(1) 94 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1) 95 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2) 96 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3) 97 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4) 98 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 5) 99 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 100 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 101 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 102 103 #define IXGBE_MAX_RSC_INT_RATE 162760 104 105 #define IXGBE_MAX_VF_MC_ENTRIES 30 106 #define IXGBE_MAX_VF_FUNCTIONS 64 107 #define IXGBE_MAX_VFTA_ENTRIES 128 108 #define MAX_EMULATION_MAC_ADDRS 16 109 #define VMDQ_P(p) ((p) + adapter->num_vfs) 110 111 struct vf_data_storage { 112 unsigned char vf_mac_addresses[ETH_ALEN]; 113 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 114 u16 num_vf_mc_hashes; 115 u16 default_vf_vlan_id; 116 u16 vlans_enabled; 117 bool clear_to_send; 118 bool pf_set_mac; 119 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 120 u16 pf_qos; 121 u16 tx_rate; 122 }; 123 124 /* wrapper around a pointer to a socket buffer, 125 * so a DMA handle can be stored along with the buffer */ 126 struct ixgbe_tx_buffer { 127 struct sk_buff *skb; 128 dma_addr_t dma; 129 unsigned long time_stamp; 130 u16 length; 131 u16 next_to_watch; 132 unsigned int bytecount; 133 u16 gso_segs; 134 u8 mapped_as_page; 135 }; 136 137 struct ixgbe_rx_buffer { 138 struct sk_buff *skb; 139 dma_addr_t dma; 140 struct page *page; 141 dma_addr_t page_dma; 142 unsigned int page_offset; 143 }; 144 145 struct ixgbe_queue_stats { 146 u64 packets; 147 u64 bytes; 148 }; 149 150 struct ixgbe_tx_queue_stats { 151 u64 restart_queue; 152 u64 tx_busy; 153 u64 completed; 154 u64 tx_done_old; 155 }; 156 157 struct ixgbe_rx_queue_stats { 158 u64 rsc_count; 159 u64 rsc_flush; 160 u64 non_eop_descs; 161 u64 alloc_rx_page_failed; 162 u64 alloc_rx_buff_failed; 163 }; 164 165 enum ixbge_ring_state_t { 166 __IXGBE_TX_FDIR_INIT_DONE, 167 __IXGBE_TX_DETECT_HANG, 168 __IXGBE_HANG_CHECK_ARMED, 169 __IXGBE_RX_PS_ENABLED, 170 __IXGBE_RX_RSC_ENABLED, 171 }; 172 173 #define ring_is_ps_enabled(ring) \ 174 test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state) 175 #define set_ring_ps_enabled(ring) \ 176 set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state) 177 #define clear_ring_ps_enabled(ring) \ 178 clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state) 179 #define check_for_tx_hang(ring) \ 180 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 181 #define set_check_for_tx_hang(ring) \ 182 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 183 #define clear_check_for_tx_hang(ring) \ 184 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 185 #define ring_is_rsc_enabled(ring) \ 186 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 187 #define set_ring_rsc_enabled(ring) \ 188 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 189 #define clear_ring_rsc_enabled(ring) \ 190 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 191 struct ixgbe_ring { 192 void *desc; /* descriptor ring memory */ 193 struct device *dev; /* device for DMA mapping */ 194 struct net_device *netdev; /* netdev ring belongs to */ 195 union { 196 struct ixgbe_tx_buffer *tx_buffer_info; 197 struct ixgbe_rx_buffer *rx_buffer_info; 198 }; 199 unsigned long state; 200 u8 atr_sample_rate; 201 u8 atr_count; 202 u16 count; /* amount of descriptors */ 203 u16 rx_buf_len; 204 u16 next_to_use; 205 u16 next_to_clean; 206 207 u8 queue_index; /* needed for multiqueue queue management */ 208 u8 reg_idx; /* holds the special value that gets 209 * the hardware register offset 210 * associated with this ring, which is 211 * different for DCB and RSS modes 212 */ 213 u8 dcb_tc; 214 215 u16 work_limit; /* max work per interrupt */ 216 217 u8 __iomem *tail; 218 219 unsigned int total_bytes; 220 unsigned int total_packets; 221 222 struct ixgbe_queue_stats stats; 223 struct u64_stats_sync syncp; 224 union { 225 struct ixgbe_tx_queue_stats tx_stats; 226 struct ixgbe_rx_queue_stats rx_stats; 227 }; 228 int numa_node; 229 unsigned int size; /* length in bytes */ 230 dma_addr_t dma; /* phys. address of descriptor ring */ 231 struct rcu_head rcu; 232 struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */ 233 } ____cacheline_internodealigned_in_smp; 234 235 enum ixgbe_ring_f_enum { 236 RING_F_NONE = 0, 237 RING_F_DCB, 238 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 239 RING_F_RSS, 240 RING_F_FDIR, 241 #ifdef IXGBE_FCOE 242 RING_F_FCOE, 243 #endif /* IXGBE_FCOE */ 244 245 RING_F_ARRAY_SIZE /* must be last in enum set */ 246 }; 247 248 #define IXGBE_MAX_DCB_INDICES 64 249 #define IXGBE_MAX_RSS_INDICES 16 250 #define IXGBE_MAX_VMDQ_INDICES 64 251 #define IXGBE_MAX_FDIR_INDICES 64 252 #ifdef IXGBE_FCOE 253 #define IXGBE_MAX_FCOE_INDICES 8 254 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) 255 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) 256 #else 257 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES 258 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES 259 #endif /* IXGBE_FCOE */ 260 struct ixgbe_ring_feature { 261 int indices; 262 int mask; 263 } ____cacheline_internodealigned_in_smp; 264 265 266 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 267 ? 8 : 1) 268 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 269 270 /* MAX_MSIX_Q_VECTORS of these are allocated, 271 * but we only use one per queue-specific vector. 272 */ 273 struct ixgbe_q_vector { 274 struct ixgbe_adapter *adapter; 275 unsigned int v_idx; /* index of q_vector within array, also used for 276 * finding the bit in EICR and friends that 277 * represents the vector for this ring */ 278 #ifdef CONFIG_IXGBE_DCA 279 int cpu; /* CPU for DCA */ 280 #endif 281 struct napi_struct napi; 282 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */ 283 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */ 284 u8 rxr_count; /* Rx ring count assigned to this vector */ 285 u8 txr_count; /* Tx ring count assigned to this vector */ 286 u8 tx_itr; 287 u8 rx_itr; 288 u32 eitr; 289 cpumask_var_t affinity_mask; 290 char name[IFNAMSIZ + 9]; 291 }; 292 293 /* Helper macros to switch between ints/sec and what the register uses. 294 * And yes, it's the same math going both ways. The lowest value 295 * supported by all of the ixgbe hardware is 8. 296 */ 297 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \ 298 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8) 299 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG 300 301 #define IXGBE_DESC_UNUSED(R) \ 302 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 303 (R)->next_to_clean - (R)->next_to_use - 1) 304 305 #define IXGBE_RX_DESC_ADV(R, i) \ 306 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 307 #define IXGBE_TX_DESC_ADV(R, i) \ 308 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 309 #define IXGBE_TX_CTXTDESC_ADV(R, i) \ 310 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 311 312 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128 313 #ifdef IXGBE_FCOE 314 /* Use 3K as the baby jumbo frame size for FCoE */ 315 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 316 #endif /* IXGBE_FCOE */ 317 318 #define OTHER_VECTOR 1 319 #define NON_Q_VECTORS (OTHER_VECTOR) 320 321 #define MAX_MSIX_VECTORS_82599 64 322 #define MAX_MSIX_Q_VECTORS_82599 64 323 #define MAX_MSIX_VECTORS_82598 18 324 #define MAX_MSIX_Q_VECTORS_82598 16 325 326 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599 327 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 328 329 #define MIN_MSIX_Q_VECTORS 2 330 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 331 332 /* board specific private data structure */ 333 struct ixgbe_adapter { 334 struct timer_list watchdog_timer; 335 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 336 u16 bd_number; 337 struct work_struct reset_task; 338 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; 339 340 /* DCB parameters */ 341 struct ieee_pfc *ixgbe_ieee_pfc; 342 struct ieee_ets *ixgbe_ieee_ets; 343 struct ixgbe_dcb_config dcb_cfg; 344 struct ixgbe_dcb_config temp_dcb_cfg; 345 u8 dcb_set_bitmap; 346 u8 dcbx_cap; 347 enum ixgbe_fc_mode last_lfc_mode; 348 349 /* Interrupt Throttle Rate */ 350 u32 rx_itr_setting; 351 u32 tx_itr_setting; 352 u16 eitr_low; 353 u16 eitr_high; 354 355 /* TX */ 356 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 357 int num_tx_queues; 358 u32 tx_timeout_count; 359 bool detect_tx_hung; 360 361 u64 restart_queue; 362 u64 lsc_int; 363 364 /* RX */ 365 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp; 366 int num_rx_queues; 367 int num_rx_pools; /* == num_rx_queues in 82598 */ 368 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 369 u64 hw_csum_rx_error; 370 u64 hw_rx_no_dma_resources; 371 u64 non_eop_descs; 372 int num_msix_vectors; 373 int max_msix_q_vectors; /* true count of q_vectors for device */ 374 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 375 struct msix_entry *msix_entries; 376 377 u32 alloc_rx_page_failed; 378 u32 alloc_rx_buff_failed; 379 380 /* Some features need tri-state capability, 381 * thus the additional *_CAPABLE flags. 382 */ 383 u32 flags; 384 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1) 385 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1) 386 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2) 387 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3) 388 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4) 389 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6) 390 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7) 391 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8) 392 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9) 393 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10) 394 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11) 395 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12) 396 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13) 397 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14) 398 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16) 399 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17) 400 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18) 401 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19) 402 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20) 403 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22) 404 #define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23) 405 #define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24) 406 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25) 407 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26) 408 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27) 409 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28) 410 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29) 411 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30) 412 413 u32 flags2; 414 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1) 415 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) 416 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) 417 /* default to trying for four seconds */ 418 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 419 420 /* OS defined structs */ 421 struct net_device *netdev; 422 struct pci_dev *pdev; 423 424 u32 test_icr; 425 struct ixgbe_ring test_tx_ring; 426 struct ixgbe_ring test_rx_ring; 427 428 /* structs defined in ixgbe_hw.h */ 429 struct ixgbe_hw hw; 430 u16 msg_enable; 431 struct ixgbe_hw_stats stats; 432 433 /* Interrupt Throttle Rate */ 434 u32 rx_eitr_param; 435 u32 tx_eitr_param; 436 437 unsigned long state; 438 u64 tx_busy; 439 unsigned int tx_ring_count; 440 unsigned int rx_ring_count; 441 442 u32 link_speed; 443 bool link_up; 444 unsigned long link_check_timeout; 445 446 struct work_struct watchdog_task; 447 struct work_struct sfp_task; 448 struct timer_list sfp_timer; 449 struct work_struct multispeed_fiber_task; 450 struct work_struct sfp_config_module_task; 451 u32 fdir_pballoc; 452 u32 atr_sample_rate; 453 spinlock_t fdir_perfect_lock; 454 struct work_struct fdir_reinit_task; 455 #ifdef IXGBE_FCOE 456 struct ixgbe_fcoe fcoe; 457 #endif /* IXGBE_FCOE */ 458 u64 rsc_total_count; 459 u64 rsc_total_flush; 460 u32 wol; 461 u16 eeprom_version; 462 463 int node; 464 struct work_struct check_overtemp_task; 465 u32 interrupt_event; 466 char lsc_int_name[IFNAMSIZ + 9]; 467 468 /* SR-IOV */ 469 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 470 unsigned int num_vfs; 471 struct vf_data_storage *vfinfo; 472 int vf_rate_link_speed; 473 }; 474 475 enum ixbge_state_t { 476 __IXGBE_TESTING, 477 __IXGBE_RESETTING, 478 __IXGBE_DOWN, 479 __IXGBE_SFP_MODULE_NOT_FOUND 480 }; 481 482 struct ixgbe_rsc_cb { 483 dma_addr_t dma; 484 u16 skb_cnt; 485 bool delay_unmap; 486 }; 487 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb) 488 489 enum ixgbe_boards { 490 board_82598, 491 board_82599, 492 board_X540, 493 }; 494 495 extern struct ixgbe_info ixgbe_82598_info; 496 extern struct ixgbe_info ixgbe_82599_info; 497 extern struct ixgbe_info ixgbe_X540_info; 498 #ifdef CONFIG_IXGBE_DCB 499 extern const struct dcbnl_rtnl_ops dcbnl_ops; 500 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, 501 struct ixgbe_dcb_config *dst_dcb_cfg, 502 int tc_max); 503 #endif 504 505 extern char ixgbe_driver_name[]; 506 extern const char ixgbe_driver_version[]; 507 508 extern int ixgbe_up(struct ixgbe_adapter *adapter); 509 extern void ixgbe_down(struct ixgbe_adapter *adapter); 510 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 511 extern void ixgbe_reset(struct ixgbe_adapter *adapter); 512 extern void ixgbe_set_ethtool_ops(struct net_device *netdev); 513 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *); 514 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *); 515 extern void ixgbe_free_rx_resources(struct ixgbe_ring *); 516 extern void ixgbe_free_tx_resources(struct ixgbe_ring *); 517 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); 518 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); 519 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 520 struct ixgbe_ring *); 521 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); 522 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 523 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 524 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, 525 struct ixgbe_adapter *, 526 struct ixgbe_ring *); 527 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 528 struct ixgbe_tx_buffer *); 529 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 530 extern void ixgbe_write_eitr(struct ixgbe_q_vector *); 531 extern int ethtool_ioctl(struct ifreq *ifr); 532 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 533 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc); 534 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc); 535 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 536 union ixgbe_atr_hash_dword input, 537 union ixgbe_atr_hash_dword common, 538 u8 queue); 539 extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 540 union ixgbe_atr_input *input, 541 struct ixgbe_atr_input_masks *input_masks, 542 u16 soft_id, u8 queue); 543 extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 544 struct ixgbe_ring *ring); 545 extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter, 546 struct ixgbe_ring *ring); 547 extern void ixgbe_set_rx_mode(struct net_device *netdev); 548 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc); 549 #ifdef IXGBE_FCOE 550 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 551 extern int ixgbe_fso(struct ixgbe_adapter *adapter, 552 struct ixgbe_ring *tx_ring, struct sk_buff *skb, 553 u32 tx_flags, u8 *hdr_len); 554 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter); 555 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 556 union ixgbe_adv_rx_desc *rx_desc, 557 struct sk_buff *skb); 558 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 559 struct scatterlist *sgl, unsigned int sgc); 560 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 561 struct scatterlist *sgl, unsigned int sgc); 562 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 563 extern int ixgbe_fcoe_enable(struct net_device *netdev); 564 extern int ixgbe_fcoe_disable(struct net_device *netdev); 565 #ifdef CONFIG_IXGBE_DCB 566 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 567 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 568 #endif /* CONFIG_IXGBE_DCB */ 569 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 570 #endif /* IXGBE_FCOE */ 571 572 #endif /* _IXGBE_H_ */ 573