1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _SBCHIPC_H 18 #define _SBCHIPC_H 19 20 #ifndef _LANGUAGE_ASSEMBLY 21 22 /* cpp contortions to concatenate w/arg prescan */ 23 #ifndef PAD 24 #define _PADLINE(line) pad ## line 25 #define _XSTR(line) _PADLINE(line) 26 #define PAD _XSTR(__LINE__) 27 #endif /* PAD */ 28 29 typedef volatile struct { 30 u32 chipid; /* 0x0 */ 31 u32 capabilities; 32 u32 corecontrol; /* corerev >= 1 */ 33 u32 bist; 34 35 /* OTP */ 36 u32 otpstatus; /* 0x10, corerev >= 10 */ 37 u32 otpcontrol; 38 u32 otpprog; 39 u32 otplayout; /* corerev >= 23 */ 40 41 /* Interrupt control */ 42 u32 intstatus; /* 0x20 */ 43 u32 intmask; 44 45 /* Chip specific regs */ 46 u32 chipcontrol; /* 0x28, rev >= 11 */ 47 u32 chipstatus; /* 0x2c, rev >= 11 */ 48 49 /* Jtag Master */ 50 u32 jtagcmd; /* 0x30, rev >= 10 */ 51 u32 jtagir; 52 u32 jtagdr; 53 u32 jtagctrl; 54 55 /* serial flash interface registers */ 56 u32 flashcontrol; /* 0x40 */ 57 u32 flashaddress; 58 u32 flashdata; 59 u32 PAD[1]; 60 61 /* Silicon backplane configuration broadcast control */ 62 u32 broadcastaddress; /* 0x50 */ 63 u32 broadcastdata; 64 65 /* gpio - cleared only by power-on-reset */ 66 u32 gpiopullup; /* 0x58, corerev >= 20 */ 67 u32 gpiopulldown; /* 0x5c, corerev >= 20 */ 68 u32 gpioin; /* 0x60 */ 69 u32 gpioout; /* 0x64 */ 70 u32 gpioouten; /* 0x68 */ 71 u32 gpiocontrol; /* 0x6C */ 72 u32 gpiointpolarity; /* 0x70 */ 73 u32 gpiointmask; /* 0x74 */ 74 75 /* GPIO events corerev >= 11 */ 76 u32 gpioevent; 77 u32 gpioeventintmask; 78 79 /* Watchdog timer */ 80 u32 watchdog; /* 0x80 */ 81 82 /* GPIO events corerev >= 11 */ 83 u32 gpioeventintpolarity; 84 85 /* GPIO based LED powersave registers corerev >= 16 */ 86 u32 gpiotimerval; /* 0x88 */ 87 u32 gpiotimeroutmask; 88 89 /* clock control */ 90 u32 clockcontrol_n; /* 0x90 */ 91 u32 clockcontrol_sb; /* aka m0 */ 92 u32 clockcontrol_pci; /* aka m1 */ 93 u32 clockcontrol_m2; /* mii/uart/mipsref */ 94 u32 clockcontrol_m3; /* cpu */ 95 u32 clkdiv; /* corerev >= 3 */ 96 u32 gpiodebugsel; /* corerev >= 28 */ 97 u32 capabilities_ext; /* 0xac */ 98 99 /* pll delay registers (corerev >= 4) */ 100 u32 pll_on_delay; /* 0xb0 */ 101 u32 fref_sel_delay; 102 u32 slow_clk_ctl; /* 5 < corerev < 10 */ 103 u32 PAD; 104 105 /* Instaclock registers (corerev >= 10) */ 106 u32 system_clk_ctl; /* 0xc0 */ 107 u32 clkstatestretch; 108 u32 PAD[2]; 109 110 /* Indirect backplane access (corerev >= 22) */ 111 u32 bp_addrlow; /* 0xd0 */ 112 u32 bp_addrhigh; 113 u32 bp_data; 114 u32 PAD; 115 u32 bp_indaccess; 116 u32 PAD[3]; 117 118 /* More clock dividers (corerev >= 32) */ 119 u32 clkdiv2; 120 u32 PAD[2]; 121 122 /* In AI chips, pointer to erom */ 123 u32 eromptr; /* 0xfc */ 124 125 /* ExtBus control registers (corerev >= 3) */ 126 u32 pcmcia_config; /* 0x100 */ 127 u32 pcmcia_memwait; 128 u32 pcmcia_attrwait; 129 u32 pcmcia_iowait; 130 u32 ide_config; 131 u32 ide_memwait; 132 u32 ide_attrwait; 133 u32 ide_iowait; 134 u32 prog_config; 135 u32 prog_waitcount; 136 u32 flash_config; 137 u32 flash_waitcount; 138 u32 SECI_config; /* 0x130 SECI configuration */ 139 u32 PAD[3]; 140 141 /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */ 142 u32 eci_output; /* 0x140 */ 143 u32 eci_control; 144 u32 eci_inputlo; 145 u32 eci_inputmi; 146 u32 eci_inputhi; 147 u32 eci_inputintpolaritylo; 148 u32 eci_inputintpolaritymi; 149 u32 eci_inputintpolarityhi; 150 u32 eci_intmasklo; 151 u32 eci_intmaskmi; 152 u32 eci_intmaskhi; 153 u32 eci_eventlo; 154 u32 eci_eventmi; 155 u32 eci_eventhi; 156 u32 eci_eventmasklo; 157 u32 eci_eventmaskmi; 158 u32 eci_eventmaskhi; 159 u32 PAD[3]; 160 161 /* SROM interface (corerev >= 32) */ 162 u32 sromcontrol; /* 0x190 */ 163 u32 sromaddress; 164 u32 sromdata; 165 u32 PAD[17]; 166 167 /* Clock control and hardware workarounds (corerev >= 20) */ 168 u32 clk_ctl_st; /* 0x1e0 */ 169 u32 hw_war; 170 u32 PAD[70]; 171 172 /* UARTs */ 173 u8 uart0data; /* 0x300 */ 174 u8 uart0imr; 175 u8 uart0fcr; 176 u8 uart0lcr; 177 u8 uart0mcr; 178 u8 uart0lsr; 179 u8 uart0msr; 180 u8 uart0scratch; 181 u8 PAD[248]; /* corerev >= 1 */ 182 183 u8 uart1data; /* 0x400 */ 184 u8 uart1imr; 185 u8 uart1fcr; 186 u8 uart1lcr; 187 u8 uart1mcr; 188 u8 uart1lsr; 189 u8 uart1msr; 190 u8 uart1scratch; 191 u32 PAD[126]; 192 193 /* PMU registers (corerev >= 20) */ 194 u32 pmucontrol; /* 0x600 */ 195 u32 pmucapabilities; 196 u32 pmustatus; 197 u32 res_state; 198 u32 res_pending; 199 u32 pmutimer; 200 u32 min_res_mask; 201 u32 max_res_mask; 202 u32 res_table_sel; 203 u32 res_dep_mask; 204 u32 res_updn_timer; 205 u32 res_timer; 206 u32 clkstretch; 207 u32 pmuwatchdog; 208 u32 gpiosel; /* 0x638, rev >= 1 */ 209 u32 gpioenable; /* 0x63c, rev >= 1 */ 210 u32 res_req_timer_sel; 211 u32 res_req_timer; 212 u32 res_req_mask; 213 u32 PAD; 214 u32 chipcontrol_addr; /* 0x650 */ 215 u32 chipcontrol_data; /* 0x654 */ 216 u32 regcontrol_addr; 217 u32 regcontrol_data; 218 u32 pllcontrol_addr; 219 u32 pllcontrol_data; 220 u32 pmustrapopt; /* 0x668, corerev >= 28 */ 221 u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ 222 u32 PAD[100]; 223 u16 sromotp[768]; 224 } chipcregs_t; 225 226 #endif /* _LANGUAGE_ASSEMBLY */ 227 228 #if defined(IL_BIGENDIAN) && defined(BCMHND74K) 229 /* Selective swapped defines for those registers we need in 230 * big-endian code. 231 */ 232 #define CC_CHIPID 4 233 #define CC_CAPABILITIES 0 234 #define CC_CHIPST 0x28 235 #define CC_EROMPTR 0xf8 236 237 #else /* !IL_BIGENDIAN || !BCMHND74K */ 238 239 #define CC_CHIPID 0 240 #define CC_CAPABILITIES 4 241 #define CC_CHIPST 0x2c 242 #define CC_EROMPTR 0xfc 243 244 #endif /* IL_BIGENDIAN && BCMHND74K */ 245 246 #define CC_OTPST 0x10 247 #define CC_JTAGCMD 0x30 248 #define CC_JTAGIR 0x34 249 #define CC_JTAGDR 0x38 250 #define CC_JTAGCTRL 0x3c 251 #define CC_GPIOPU 0x58 252 #define CC_GPIOPD 0x5c 253 #define CC_GPIOIN 0x60 254 #define CC_GPIOOUT 0x64 255 #define CC_GPIOOUTEN 0x68 256 #define CC_GPIOCTRL 0x6c 257 #define CC_GPIOPOL 0x70 258 #define CC_GPIOINTM 0x74 259 #define CC_WATCHDOG 0x80 260 #define CC_CLKC_N 0x90 261 #define CC_CLKC_M0 0x94 262 #define CC_CLKC_M1 0x98 263 #define CC_CLKC_M2 0x9c 264 #define CC_CLKC_M3 0xa0 265 #define CC_CLKDIV 0xa4 266 #define CC_SYS_CLK_CTL 0xc0 267 #define CC_CLK_CTL_ST SI_CLK_CTL_ST 268 #define PMU_CTL 0x600 269 #define PMU_CAP 0x604 270 #define PMU_ST 0x608 271 #define PMU_RES_STATE 0x60c 272 #define PMU_TIMER 0x614 273 #define PMU_MIN_RES_MASK 0x618 274 #define PMU_MAX_RES_MASK 0x61c 275 #define CC_CHIPCTL_ADDR 0x650 276 #define CC_CHIPCTL_DATA 0x654 277 #define PMU_REG_CONTROL_ADDR 0x658 278 #define PMU_REG_CONTROL_DATA 0x65C 279 #define PMU_PLL_CONTROL_ADDR 0x660 280 #define PMU_PLL_CONTROL_DATA 0x664 281 #define CC_SROM_OTP 0x800 /* SROM/OTP address space */ 282 283 /* chipid */ 284 #define CID_ID_MASK 0x0000ffff /* Chip Id mask */ 285 #define CID_REV_MASK 0x000f0000 /* Chip Revision mask */ 286 #define CID_REV_SHIFT 16 /* Chip Revision shift */ 287 #define CID_PKG_MASK 0x00f00000 /* Package Option mask */ 288 #define CID_PKG_SHIFT 20 /* Package Option shift */ 289 #define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */ 290 #define CID_CC_SHIFT 24 291 #define CID_TYPE_MASK 0xf0000000 /* Chip Type */ 292 #define CID_TYPE_SHIFT 28 293 294 /* capabilities */ 295 #define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */ 296 #define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ 297 #define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */ 298 #define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */ 299 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ 300 #define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ 301 #define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */ 302 #define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */ 303 #define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */ 304 #define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ 305 #define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ 306 #define CC_CAP_PWR_CTL 0x00040000 /* Power control */ 307 #define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */ 308 #define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */ 309 #define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */ 310 #define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ 311 #define CC_CAP_ROM 0x00800000 /* Internal boot rom active */ 312 #define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ 313 #define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ 314 #define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */ 315 #define CC_CAP_NFLASH 0x80000000 /* Nand flash present, rev >= 35 */ 316 317 #define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */ 318 #define CC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */ 319 320 /* PLL type */ 321 #define PLL_NONE 0x00000000 322 #define PLL_TYPE1 0x00010000 /* 48MHz base, 3 dividers */ 323 #define PLL_TYPE2 0x00020000 /* 48MHz, 4 dividers */ 324 #define PLL_TYPE3 0x00030000 /* 25MHz, 2 dividers */ 325 #define PLL_TYPE4 0x00008000 /* 48MHz, 4 dividers */ 326 #define PLL_TYPE5 0x00018000 /* 25MHz, 4 dividers */ 327 #define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */ 328 #define PLL_TYPE7 0x00038000 /* 25MHz, 4 dividers */ 329 330 /* ILP clock */ 331 #define ILP_CLOCK 32000 332 333 /* ALP clock on pre-PMU chips */ 334 #define ALP_CLOCK 20000000 335 336 /* HT clock */ 337 #define HT_CLOCK 80000000 338 339 /* corecontrol */ 340 #define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ 341 #define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ 342 #define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ 343 344 /* chipcontrol */ 345 #define CHIPCTRL_4321A0_DEFAULT 0x3a4 346 #define CHIPCTRL_4321A1_DEFAULT 0x0a4 347 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */ 348 349 /* Fields in the otpstatus register in rev >= 21 */ 350 #define OTPS_OL_MASK 0x000000ff 351 #define OTPS_OL_MFG 0x00000001 /* manuf row is locked */ 352 #define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */ 353 #define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */ 354 #define OTPS_OL_GU 0x00000008 /* general use region is locked */ 355 #define OTPS_GUP_MASK 0x00000f00 356 #define OTPS_GUP_SHIFT 8 357 #define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */ 358 #define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */ 359 #define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */ 360 #define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */ 361 #define OTPS_READY 0x00001000 362 #define OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */ 363 #define OTPS_RV_MASK 0x0fff0000 364 365 /* Fields in the otpcontrol register in rev >= 21 */ 366 #define OTPC_PROGSEL 0x00000001 367 #define OTPC_PCOUNT_MASK 0x0000000e 368 #define OTPC_PCOUNT_SHIFT 1 369 #define OTPC_VSEL_MASK 0x000000f0 370 #define OTPC_VSEL_SHIFT 4 371 #define OTPC_TMM_MASK 0x00000700 372 #define OTPC_TMM_SHIFT 8 373 #define OTPC_ODM 0x00000800 374 #define OTPC_PROGEN 0x80000000 375 376 /* Fields in otpprog in rev >= 21 and HND OTP */ 377 #define OTPP_COL_MASK 0x000000ff 378 #define OTPP_COL_SHIFT 0 379 #define OTPP_ROW_MASK 0x0000ff00 380 #define OTPP_ROW_SHIFT 8 381 #define OTPP_OC_MASK 0x0f000000 382 #define OTPP_OC_SHIFT 24 383 #define OTPP_READERR 0x10000000 384 #define OTPP_VALUE_MASK 0x20000000 385 #define OTPP_VALUE_SHIFT 29 386 #define OTPP_START_BUSY 0x80000000 387 #define OTPP_READ 0x40000000 /* HND OTP */ 388 389 /* otplayout reg corerev >= 36 */ 390 #define OTP_CISFORMAT_NEW 0x80000000 391 392 /* Opcodes for OTPP_OC field */ 393 #define OTPPOC_READ 0 394 #define OTPPOC_BIT_PROG 1 395 #define OTPPOC_VERIFY 3 396 #define OTPPOC_INIT 4 397 #define OTPPOC_SET 5 398 #define OTPPOC_RESET 6 399 #define OTPPOC_OCST 7 400 #define OTPPOC_ROW_LOCK 8 401 #define OTPPOC_PRESCN_TEST 9 402 403 /* Jtagm characteristics that appeared at a given corerev */ 404 #define JTAGM_CREV_OLD 10 /* Old command set, 16bit max IR */ 405 #define JTAGM_CREV_IRP 22 /* Able to do pause-ir */ 406 #define JTAGM_CREV_RTI 28 /* Able to do return-to-idle */ 407 408 /* jtagcmd */ 409 #define JCMD_START 0x80000000 410 #define JCMD_BUSY 0x80000000 411 #define JCMD_STATE_MASK 0x60000000 412 #define JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */ 413 #define JCMD_STATE_PIR 0x20000000 /* Pause IR */ 414 #define JCMD_STATE_PDR 0x40000000 /* Pause DR */ 415 #define JCMD_STATE_RTI 0x60000000 /* Run-test-idle */ 416 #define JCMD0_ACC_MASK 0x0000f000 417 #define JCMD0_ACC_IRDR 0x00000000 418 #define JCMD0_ACC_DR 0x00001000 419 #define JCMD0_ACC_IR 0x00002000 420 #define JCMD0_ACC_RESET 0x00003000 421 #define JCMD0_ACC_IRPDR 0x00004000 422 #define JCMD0_ACC_PDR 0x00005000 423 #define JCMD0_IRW_MASK 0x00000f00 424 #define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */ 425 #define JCMD_ACC_IRDR 0x00000000 426 #define JCMD_ACC_DR 0x00010000 427 #define JCMD_ACC_IR 0x00020000 428 #define JCMD_ACC_RESET 0x00030000 429 #define JCMD_ACC_IRPDR 0x00040000 430 #define JCMD_ACC_PDR 0x00050000 431 #define JCMD_ACC_PIR 0x00060000 432 #define JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */ 433 #define JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */ 434 #define JCMD_IRW_MASK 0x00001f00 435 #define JCMD_IRW_SHIFT 8 436 #define JCMD_DRW_MASK 0x0000003f 437 438 /* jtagctrl */ 439 #define JCTRL_FORCE_CLK 4 /* Force clock */ 440 #define JCTRL_EXT_EN 2 /* Enable external targets */ 441 #define JCTRL_EN 1 /* Enable Jtag master */ 442 443 /* Fields in clkdiv */ 444 #define CLKD_SFLASH 0x0f000000 445 #define CLKD_SFLASH_SHIFT 24 446 #define CLKD_OTP 0x000f0000 447 #define CLKD_OTP_SHIFT 16 448 #define CLKD_JTAG 0x00000f00 449 #define CLKD_JTAG_SHIFT 8 450 #define CLKD_UART 0x000000ff 451 452 #define CLKD2_SROM 0x00000003 453 454 /* intstatus/intmask */ 455 #define CI_GPIO 0x00000001 /* gpio intr */ 456 #define CI_EI 0x00000002 /* extif intr (corerev >= 3) */ 457 #define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */ 458 #define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */ 459 #define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */ 460 #define CI_UART 0x00000040 /* uart intr (corerev >= 21) */ 461 #define CI_WDRESET 0x80000000 /* watchdog reset occurred */ 462 463 /* slow_clk_ctl */ 464 #define SCC_SS_MASK 0x00000007 /* slow clock source mask */ 465 #define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ 466 #define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ 467 #define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ 468 #define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ 469 #define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 470 * 0: LPO is enabled 471 */ 472 #define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 473 * 0: power logic control 474 */ 475 #define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors 476 * PLL clock disable requests from core 477 */ 478 #define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't 479 * disable crystal when appropriate 480 */ 481 #define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ 482 #define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ 483 #define SCC_CD_SHIFT 16 484 485 /* system_clk_ctl */ 486 #define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ 487 #define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ 488 #define SYCC_FP 0x00000004 /* ForcePLLOn */ 489 #define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ 490 #define SYCC_HR 0x00000010 /* Force HT */ 491 #define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ 492 #define SYCC_CD_SHIFT 16 493 494 /* Indirect backplane access */ 495 #define BPIA_BYTEEN 0x0000000f 496 #define BPIA_SZ1 0x00000001 497 #define BPIA_SZ2 0x00000003 498 #define BPIA_SZ4 0x00000007 499 #define BPIA_SZ8 0x0000000f 500 #define BPIA_WRITE 0x00000100 501 #define BPIA_START 0x00000200 502 #define BPIA_BUSY 0x00000200 503 #define BPIA_ERROR 0x00000400 504 505 /* pcmcia/prog/flash_config */ 506 #define CF_EN 0x00000001 /* enable */ 507 #define CF_EM_MASK 0x0000000e /* mode */ 508 #define CF_EM_SHIFT 1 509 #define CF_EM_FLASH 0 /* flash/asynchronous mode */ 510 #define CF_EM_SYNC 2 /* synchronous mode */ 511 #define CF_EM_PCMCIA 4 /* pcmcia mode */ 512 #define CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */ 513 #define CF_BS 0x00000020 /* byteswap */ 514 #define CF_CD_MASK 0x000000c0 /* clock divider */ 515 #define CF_CD_SHIFT 6 516 #define CF_CD_DIV2 0x00000000 /* backplane/2 */ 517 #define CF_CD_DIV3 0x00000040 /* backplane/3 */ 518 #define CF_CD_DIV4 0x00000080 /* backplane/4 */ 519 #define CF_CE 0x00000100 /* clock enable */ 520 #define CF_SB 0x00000200 /* size/bytestrobe (synch only) */ 521 522 /* pcmcia_memwait */ 523 #define PM_W0_MASK 0x0000003f /* waitcount0 */ 524 #define PM_W1_MASK 0x00001f00 /* waitcount1 */ 525 #define PM_W1_SHIFT 8 526 #define PM_W2_MASK 0x001f0000 /* waitcount2 */ 527 #define PM_W2_SHIFT 16 528 #define PM_W3_MASK 0x1f000000 /* waitcount3 */ 529 #define PM_W3_SHIFT 24 530 531 /* pcmcia_attrwait */ 532 #define PA_W0_MASK 0x0000003f /* waitcount0 */ 533 #define PA_W1_MASK 0x00001f00 /* waitcount1 */ 534 #define PA_W1_SHIFT 8 535 #define PA_W2_MASK 0x001f0000 /* waitcount2 */ 536 #define PA_W2_SHIFT 16 537 #define PA_W3_MASK 0x1f000000 /* waitcount3 */ 538 #define PA_W3_SHIFT 24 539 540 /* pcmcia_iowait */ 541 #define PI_W0_MASK 0x0000003f /* waitcount0 */ 542 #define PI_W1_MASK 0x00001f00 /* waitcount1 */ 543 #define PI_W1_SHIFT 8 544 #define PI_W2_MASK 0x001f0000 /* waitcount2 */ 545 #define PI_W2_SHIFT 16 546 #define PI_W3_MASK 0x1f000000 /* waitcount3 */ 547 #define PI_W3_SHIFT 24 548 549 /* prog_waitcount */ 550 #define PW_W0_MASK 0x0000001f /* waitcount0 */ 551 #define PW_W1_MASK 0x00001f00 /* waitcount1 */ 552 #define PW_W1_SHIFT 8 553 #define PW_W2_MASK 0x001f0000 /* waitcount2 */ 554 #define PW_W2_SHIFT 16 555 #define PW_W3_MASK 0x1f000000 /* waitcount3 */ 556 #define PW_W3_SHIFT 24 557 558 #define PW_W0 0x0000000c 559 #define PW_W1 0x00000a00 560 #define PW_W2 0x00020000 561 #define PW_W3 0x01000000 562 563 /* flash_waitcount */ 564 #define FW_W0_MASK 0x0000003f /* waitcount0 */ 565 #define FW_W1_MASK 0x00001f00 /* waitcount1 */ 566 #define FW_W1_SHIFT 8 567 #define FW_W2_MASK 0x001f0000 /* waitcount2 */ 568 #define FW_W2_SHIFT 16 569 #define FW_W3_MASK 0x1f000000 /* waitcount3 */ 570 #define FW_W3_SHIFT 24 571 572 /* When Srom support present, fields in sromcontrol */ 573 #define SRC_START 0x80000000 574 #define SRC_BUSY 0x80000000 575 #define SRC_OPCODE 0x60000000 576 #define SRC_OP_READ 0x00000000 577 #define SRC_OP_WRITE 0x20000000 578 #define SRC_OP_WRDIS 0x40000000 579 #define SRC_OP_WREN 0x60000000 580 #define SRC_OTPSEL 0x00000010 581 #define SRC_LOCK 0x00000008 582 #define SRC_SIZE_MASK 0x00000006 583 #define SRC_SIZE_1K 0x00000000 584 #define SRC_SIZE_4K 0x00000002 585 #define SRC_SIZE_16K 0x00000004 586 #define SRC_SIZE_SHIFT 1 587 #define SRC_PRESENT 0x00000001 588 589 /* Fields in pmucontrol */ 590 #define PCTL_ILP_DIV_MASK 0xffff0000 591 #define PCTL_ILP_DIV_SHIFT 16 592 #define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */ 593 #define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */ 594 #define PCTL_HT_REQ_EN 0x00000100 595 #define PCTL_ALP_REQ_EN 0x00000080 596 #define PCTL_XTALFREQ_MASK 0x0000007c 597 #define PCTL_XTALFREQ_SHIFT 2 598 #define PCTL_ILP_DIV_EN 0x00000002 599 #define PCTL_LPO_SEL 0x00000001 600 601 /* Fields in clkstretch */ 602 #define CSTRETCH_HT 0xffff0000 603 #define CSTRETCH_ALP 0x0000ffff 604 605 /* gpiotimerval */ 606 #define GPIO_ONTIME_SHIFT 16 607 608 /* clockcontrol_n */ 609 #define CN_N1_MASK 0x3f /* n1 control */ 610 #define CN_N2_MASK 0x3f00 /* n2 control */ 611 #define CN_N2_SHIFT 8 612 #define CN_PLLC_MASK 0xf0000 /* pll control */ 613 #define CN_PLLC_SHIFT 16 614 615 /* clockcontrol_sb/pci/uart */ 616 #define CC_M1_MASK 0x3f /* m1 control */ 617 #define CC_M2_MASK 0x3f00 /* m2 control */ 618 #define CC_M2_SHIFT 8 619 #define CC_M3_MASK 0x3f0000 /* m3 control */ 620 #define CC_M3_SHIFT 16 621 #define CC_MC_MASK 0x1f000000 /* mux control */ 622 #define CC_MC_SHIFT 24 623 624 /* N3M Clock control magic field values */ 625 #define CC_F6_2 0x02 /* A factor of 2 in */ 626 #define CC_F6_3 0x03 /* 6-bit fields like */ 627 #define CC_F6_4 0x05 /* N1, M1 or M3 */ 628 #define CC_F6_5 0x09 629 #define CC_F6_6 0x11 630 #define CC_F6_7 0x21 631 632 #define CC_F5_BIAS 5 /* 5-bit fields get this added */ 633 634 #define CC_MC_BYPASS 0x08 635 #define CC_MC_M1 0x04 636 #define CC_MC_M1M2 0x02 637 #define CC_MC_M1M2M3 0x01 638 #define CC_MC_M1M3 0x11 639 640 /* Type 2 Clock control magic field values */ 641 #define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ 642 #define CC_T2M2_BIAS 3 /* m2 bias */ 643 644 #define CC_T2MC_M1BYP 1 645 #define CC_T2MC_M2BYP 2 646 #define CC_T2MC_M3BYP 4 647 648 /* Type 6 Clock control magic field values */ 649 #define CC_T6_MMASK 1 /* bits of interest in m */ 650 #define CC_T6_M0 120000000 /* sb clock for m = 0 */ 651 #define CC_T6_M1 100000000 /* sb clock for m = 1 */ 652 #define SB2MIPS_T6(sb) (2 * (sb)) 653 654 /* Common clock base */ 655 #define CC_CLOCK_BASE1 24000000 /* Half the clock freq */ 656 #define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLLs */ 657 658 /* Clock control values for 200MHz in 5350 */ 659 #define CLKC_5350_N 0x0311 660 #define CLKC_5350_M 0x04020009 661 662 /* Flash types in the chipcommon capabilities register */ 663 #define FLASH_NONE 0x000 /* No flash */ 664 #define SFLASH_ST 0x100 /* ST serial flash */ 665 #define SFLASH_AT 0x200 /* Atmel serial flash */ 666 #define PFLASH 0x700 /* Parallel flash */ 667 668 /* Bits in the ExtBus config registers */ 669 #define CC_CFG_EN 0x0001 /* Enable */ 670 #define CC_CFG_EM_MASK 0x000e /* Extif Mode */ 671 #define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */ 672 #define CC_CFG_EM_SYNC 0x0002 /* Synchronous */ 673 #define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */ 674 #define CC_CFG_EM_IDE 0x0006 /* IDE */ 675 #define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ 676 #define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */ 677 #define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */ 678 #define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */ 679 #define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */ 680 681 /* ExtBus address space */ 682 #define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */ 683 #define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */ 684 #define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */ 685 #define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */ 686 #define CC_EB_IDE 0x1a800000 /* IDE memory base */ 687 #define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */ 688 #define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */ 689 #define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */ 690 #define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */ 691 692 /* Start/busy bit in flashcontrol */ 693 #define SFLASH_OPCODE 0x000000ff 694 #define SFLASH_ACTION 0x00000700 695 #define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ 696 #define SFLASH_START 0x80000000 697 #define SFLASH_BUSY SFLASH_START 698 699 /* flashcontrol action codes */ 700 #define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */ 701 #define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */ 702 #define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */ 703 #define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */ 704 #define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */ 705 #define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */ 706 #define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */ 707 708 /* flashcontrol action+opcodes for ST flashes */ 709 #define SFLASH_ST_WREN 0x0006 /* Write Enable */ 710 #define SFLASH_ST_WRDIS 0x0004 /* Write Disable */ 711 #define SFLASH_ST_RDSR 0x0105 /* Read Status Register */ 712 #define SFLASH_ST_WRSR 0x0101 /* Write Status Register */ 713 #define SFLASH_ST_READ 0x0303 /* Read Data Bytes */ 714 #define SFLASH_ST_PP 0x0302 /* Page Program */ 715 #define SFLASH_ST_SE 0x02d8 /* Sector Erase */ 716 #define SFLASH_ST_BE 0x00c7 /* Bulk Erase */ 717 #define SFLASH_ST_DP 0x00b9 /* Deep Power-down */ 718 #define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */ 719 #define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */ 720 #define SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */ 721 722 /* Status register bits for ST flashes */ 723 #define SFLASH_ST_WIP 0x01 /* Write In Progress */ 724 #define SFLASH_ST_WEL 0x02 /* Write Enable Latch */ 725 #define SFLASH_ST_BP_MASK 0x1c /* Block Protect */ 726 #define SFLASH_ST_BP_SHIFT 2 727 #define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */ 728 729 /* flashcontrol action+opcodes for Atmel flashes */ 730 #define SFLASH_AT_READ 0x07e8 731 #define SFLASH_AT_PAGE_READ 0x07d2 732 #define SFLASH_AT_BUF1_READ 733 #define SFLASH_AT_BUF2_READ 734 #define SFLASH_AT_STATUS 0x01d7 735 #define SFLASH_AT_BUF1_WRITE 0x0384 736 #define SFLASH_AT_BUF2_WRITE 0x0387 737 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 738 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 739 #define SFLASH_AT_BUF1_PROGRAM 0x0288 740 #define SFLASH_AT_BUF2_PROGRAM 0x0289 741 #define SFLASH_AT_PAGE_ERASE 0x0281 742 #define SFLASH_AT_BLOCK_ERASE 0x0250 743 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 744 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 745 #define SFLASH_AT_BUF1_LOAD 0x0253 746 #define SFLASH_AT_BUF2_LOAD 0x0255 747 #define SFLASH_AT_BUF1_COMPARE 0x0260 748 #define SFLASH_AT_BUF2_COMPARE 0x0261 749 #define SFLASH_AT_BUF1_REPROGRAM 0x0258 750 #define SFLASH_AT_BUF2_REPROGRAM 0x0259 751 752 /* Status register bits for Atmel flashes */ 753 #define SFLASH_AT_READY 0x80 754 #define SFLASH_AT_MISMATCH 0x40 755 #define SFLASH_AT_ID_MASK 0x38 756 #define SFLASH_AT_ID_SHIFT 3 757 758 /* 759 * These are the UART port assignments, expressed as offsets from the base 760 * register. These assignments should hold for any serial port based on 761 * a 8250, 16450, or 16550(A). 762 */ 763 764 #define UART_RX 0 /* In: Receive buffer (DLAB=0) */ 765 #define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ 766 #define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ 767 #define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */ 768 #define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ 769 #define UART_IIR 2 /* In: Interrupt Identity Register */ 770 #define UART_FCR 2 /* Out: FIFO Control Register */ 771 #define UART_LCR 3 /* Out: Line Control Register */ 772 #define UART_MCR 4 /* Out: Modem Control Register */ 773 #define UART_LSR 5 /* In: Line Status Register */ 774 #define UART_MSR 6 /* In: Modem Status Register */ 775 #define UART_SCR 7 /* I/O: Scratch Register */ 776 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 777 #define UART_LCR_WLEN8 0x03 /* Word length: 8 bits */ 778 #define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */ 779 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 780 #define UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */ 781 #define UART_LSR_TDHR 0x40 /* Data-hold-register empty */ 782 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 783 #define UART_LSR_BREAK 0x10 /* Break interrupt */ 784 #define UART_LSR_FRAMING 0x08 /* Framing error */ 785 #define UART_LSR_PARITY 0x04 /* Parity error */ 786 #define UART_LSR_OVERRUN 0x02 /* Overrun error */ 787 #define UART_LSR_RXRDY 0x01 /* Receiver ready */ 788 #define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */ 789 790 /* Interrupt Identity Register (IIR) bits */ 791 #define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */ 792 #define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */ 793 #define UART_IIR_MDM_CHG 0x0 /* Modem status changed */ 794 #define UART_IIR_NOINT 0x1 /* No interrupt pending */ 795 #define UART_IIR_THRE 0x2 /* THR empty */ 796 #define UART_IIR_RCVD_DATA 0x4 /* Received data available */ 797 #define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */ 798 #define UART_IIR_CHAR_TIME 0xc /* Character time */ 799 800 /* Interrupt Enable Register (IER) bits */ 801 #define UART_IER_EDSSI 8 /* enable modem status interrupt */ 802 #define UART_IER_ELSI 4 /* enable receiver line status interrupt */ 803 #define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ 804 #define UART_IER_ERBFI 1 /* enable data available interrupt */ 805 806 /* pmustatus */ 807 #define PST_EXTLPOAVAIL 0x0100 808 #define PST_WDRESET 0x0080 809 #define PST_INTPEND 0x0040 810 #define PST_SBCLKST 0x0030 811 #define PST_SBCLKST_ILP 0x0010 812 #define PST_SBCLKST_ALP 0x0020 813 #define PST_SBCLKST_HT 0x0030 814 #define PST_ALPAVAIL 0x0008 815 #define PST_HTAVAIL 0x0004 816 #define PST_RESINIT 0x0003 817 818 /* pmucapabilities */ 819 #define PCAP_REV_MASK 0x000000ff 820 #define PCAP_RC_MASK 0x00001f00 821 #define PCAP_RC_SHIFT 8 822 #define PCAP_TC_MASK 0x0001e000 823 #define PCAP_TC_SHIFT 13 824 #define PCAP_PC_MASK 0x001e0000 825 #define PCAP_PC_SHIFT 17 826 #define PCAP_VC_MASK 0x01e00000 827 #define PCAP_VC_SHIFT 21 828 #define PCAP_CC_MASK 0x1e000000 829 #define PCAP_CC_SHIFT 25 830 #define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ 831 #define PCAP5_PC_SHIFT 17 832 #define PCAP5_VC_MASK 0x07c00000 833 #define PCAP5_VC_SHIFT 22 834 #define PCAP5_CC_MASK 0xf8000000 835 #define PCAP5_CC_SHIFT 27 836 837 /* PMU Resource Request Timer registers */ 838 /* This is based on PmuRev0 */ 839 #define PRRT_TIME_MASK 0x03ff 840 #define PRRT_INTEN 0x0400 841 #define PRRT_REQ_ACTIVE 0x0800 842 #define PRRT_ALP_REQ 0x1000 843 #define PRRT_HT_REQ 0x2000 844 845 /* PMU resource bit position */ 846 #define PMURES_BIT(bit) (1 << (bit)) 847 848 /* PMU resource number limit */ 849 #define PMURES_MAX_RESNUM 30 850 851 /* PMU chip control0 register */ 852 #define PMU_CHIPCTL0 0 853 854 /* PMU chip control1 register */ 855 #define PMU_CHIPCTL1 1 856 #define PMU_CC1_RXC_DLL_BYPASS 0x00010000 857 858 #define PMU_CC1_IF_TYPE_MASK 0x00000030 859 #define PMU_CC1_IF_TYPE_RMII 0x00000000 860 #define PMU_CC1_IF_TYPE_MII 0x00000010 861 #define PMU_CC1_IF_TYPE_RGMII 0x00000020 862 863 #define PMU_CC1_SW_TYPE_MASK 0x000000c0 864 #define PMU_CC1_SW_TYPE_EPHY 0x00000000 865 #define PMU_CC1_SW_TYPE_EPHYMII 0x00000040 866 #define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 867 #define PMU_CC1_SW_TYPE_RGMII 0x000000c0 868 869 /* PMU corerev and chip specific PLL controls. 870 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number 871 * to differentiate different PLLs controlled by the same PMU rev. 872 */ 873 /* pllcontrol registers */ 874 /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ 875 #define PMU0_PLL0_PLLCTL0 0 876 #define PMU0_PLL0_PC0_PDIV_MASK 1 877 #define PMU0_PLL0_PC0_PDIV_FREQ 25000 878 #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 879 #define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 880 #define PMU0_PLL0_PC0_DIV_ARM_BASE 8 881 882 /* PC0_DIV_ARM for PLLOUT_ARM */ 883 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 884 #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 885 #define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 886 #define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ 887 #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 888 #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 889 #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 890 #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 891 892 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ 893 #define PMU0_PLL0_PLLCTL1 1 894 #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 895 #define PMU0_PLL0_PC1_WILD_INT_SHIFT 28 896 #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 897 #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 898 #define PMU0_PLL0_PC1_STOP_MOD 0x00000040 899 900 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ 901 #define PMU0_PLL0_PLLCTL2 2 902 #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf 903 #define PMU0_PLL0_PC2_WILD_INT_SHIFT 4 904 905 /* pllcontrol registers */ 906 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 907 #define PMU1_PLL0_PLLCTL0 0 908 #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 909 #define PMU1_PLL0_PC0_P1DIV_SHIFT 20 910 #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 911 #define PMU1_PLL0_PC0_P2DIV_SHIFT 24 912 913 /* m<x>div */ 914 #define PMU1_PLL0_PLLCTL1 1 915 #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff 916 #define PMU1_PLL0_PC1_M1DIV_SHIFT 0 917 #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 918 #define PMU1_PLL0_PC1_M2DIV_SHIFT 8 919 #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 920 #define PMU1_PLL0_PC1_M3DIV_SHIFT 16 921 #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 922 #define PMU1_PLL0_PC1_M4DIV_SHIFT 24 923 924 #define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 925 #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 926 #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 927 928 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 929 #define PMU1_PLL0_PLLCTL2 2 930 #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff 931 #define PMU1_PLL0_PC2_M5DIV_SHIFT 0 932 #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 933 #define PMU1_PLL0_PC2_M6DIV_SHIFT 8 934 #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 935 #define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 936 #define PMU1_PLL0_PC2_NDIV_MODE_MASH 1 937 #define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */ 938 #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 939 #define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 940 941 /* ndiv_frac */ 942 #define PMU1_PLL0_PLLCTL3 3 943 #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff 944 #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 945 946 /* pll_ctrl */ 947 #define PMU1_PLL0_PLLCTL4 4 948 949 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 950 #define PMU1_PLL0_PLLCTL5 5 951 #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 952 #define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 953 954 /* PMU rev 2 control words */ 955 #define PMU2_PHY_PLL_PLLCTL 4 956 #define PMU2_SI_PLL_PLLCTL 10 957 958 /* PMU rev 2 */ 959 /* pllcontrol registers */ 960 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 961 #define PMU2_PLL_PLLCTL0 0 962 #define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 963 #define PMU2_PLL_PC0_P1DIV_SHIFT 20 964 #define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 965 #define PMU2_PLL_PC0_P2DIV_SHIFT 24 966 967 /* m<x>div */ 968 #define PMU2_PLL_PLLCTL1 1 969 #define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff 970 #define PMU2_PLL_PC1_M1DIV_SHIFT 0 971 #define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 972 #define PMU2_PLL_PC1_M2DIV_SHIFT 8 973 #define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 974 #define PMU2_PLL_PC1_M3DIV_SHIFT 16 975 #define PMU2_PLL_PC1_M4DIV_MASK 0xff000000 976 #define PMU2_PLL_PC1_M4DIV_SHIFT 24 977 978 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 979 #define PMU2_PLL_PLLCTL2 2 980 #define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff 981 #define PMU2_PLL_PC2_M5DIV_SHIFT 0 982 #define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 983 #define PMU2_PLL_PC2_M6DIV_SHIFT 8 984 #define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 985 #define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 986 #define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 987 #define PMU2_PLL_PC2_NDIV_INT_SHIFT 20 988 989 /* ndiv_frac */ 990 #define PMU2_PLL_PLLCTL3 3 991 #define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff 992 #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 993 994 /* pll_ctrl */ 995 #define PMU2_PLL_PLLCTL4 4 996 997 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 998 #define PMU2_PLL_PLLCTL5 5 999 #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 1000 #define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 1001 #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 1002 #define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 1003 #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 1004 #define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 1005 #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 1006 #define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 1007 #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 1008 #define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 1009 #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 1010 #define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 1011 1012 /* PMU rev 5 (& 6) */ 1013 #define PMU5_PLL_P1P2_OFF 0 1014 #define PMU5_PLL_P1_MASK 0x0f000000 1015 #define PMU5_PLL_P1_SHIFT 24 1016 #define PMU5_PLL_P2_MASK 0x00f00000 1017 #define PMU5_PLL_P2_SHIFT 20 1018 #define PMU5_PLL_M14_OFF 1 1019 #define PMU5_PLL_MDIV_MASK 0x000000ff 1020 #define PMU5_PLL_MDIV_WIDTH 8 1021 #define PMU5_PLL_NM5_OFF 2 1022 #define PMU5_PLL_NDIV_MASK 0xfff00000 1023 #define PMU5_PLL_NDIV_SHIFT 20 1024 #define PMU5_PLL_NDIV_MODE_MASK 0x000e0000 1025 #define PMU5_PLL_NDIV_MODE_SHIFT 17 1026 #define PMU5_PLL_FMAB_OFF 3 1027 #define PMU5_PLL_MRAT_MASK 0xf0000000 1028 #define PMU5_PLL_MRAT_SHIFT 28 1029 #define PMU5_PLL_ABRAT_MASK 0x08000000 1030 #define PMU5_PLL_ABRAT_SHIFT 27 1031 #define PMU5_PLL_FDIV_MASK 0x07ffffff 1032 #define PMU5_PLL_PLLCTL_OFF 4 1033 #define PMU5_PLL_PCHI_OFF 5 1034 #define PMU5_PLL_PCHI_MASK 0x0000003f 1035 1036 /* pmu XtalFreqRatio */ 1037 #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF 1038 #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 1039 #define PMU_XTALFREQ_REG_MEASURE_SHIFT 31 1040 1041 /* Divider allocation in 4716/47162/5356/5357 */ 1042 #define PMU5_MAINPLL_CPU 1 1043 #define PMU5_MAINPLL_MEM 2 1044 #define PMU5_MAINPLL_SI 3 1045 1046 #define PMU7_PLL_PLLCTL7 7 1047 #define PMU7_PLL_PLLCTL8 8 1048 #define PMU7_PLL_PLLCTL11 11 1049 1050 /* PLL usage in 4716/47162 */ 1051 #define PMU4716_MAINPLL_PLL0 12 1052 1053 /* PLL usage in 5356/5357 */ 1054 #define PMU5356_MAINPLL_PLL0 0 1055 #define PMU5357_MAINPLL_PLL0 0 1056 1057 /* 4716/47162 resources */ 1058 #define RES4716_PROC_PLL_ON 0x00000040 1059 #define RES4716_PROC_HT_AVAIL 0x00000080 1060 1061 /* 4716/4717/4718 Chip specific ChipControl register bits */ 1062 #define CCTRL471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared with pflash */ 1063 1064 /* 5354 resources */ 1065 #define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ 1066 #define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ 1067 #define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ 1068 #define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 1069 #define RES5354_ILP_REQUEST 4 /* 0x00010 */ 1070 #define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 1071 #define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 1072 #define RES5354_ROM_SWITCH 7 /* 0x00080 */ 1073 #define RES5354_PA_REF_LDO 8 /* 0x00100 */ 1074 #define RES5354_RADIO_LDO 9 /* 0x00200 */ 1075 #define RES5354_AFE_LDO 10 /* 0x00400 */ 1076 #define RES5354_PLL_LDO 11 /* 0x00800 */ 1077 #define RES5354_BG_FILTBYP 12 /* 0x01000 */ 1078 #define RES5354_TX_FILTBYP 13 /* 0x02000 */ 1079 #define RES5354_RX_FILTBYP 14 /* 0x04000 */ 1080 #define RES5354_XTAL_PU 15 /* 0x08000 */ 1081 #define RES5354_XTAL_EN 16 /* 0x10000 */ 1082 #define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ 1083 #define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ 1084 #define RES5354_BB_PLL_PU 19 /* 0x80000 */ 1085 1086 /* 5357 Chip specific ChipControl register bits */ 1087 #define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ 1088 #define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ 1089 1090 /* 4328 resources */ 1091 #define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ 1092 #define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ 1093 #define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ 1094 #define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 1095 #define RES4328_ILP_REQUEST 4 /* 0x00010 */ 1096 #define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 1097 #define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 1098 #define RES4328_ROM_SWITCH 7 /* 0x00080 */ 1099 #define RES4328_PA_REF_LDO 8 /* 0x00100 */ 1100 #define RES4328_RADIO_LDO 9 /* 0x00200 */ 1101 #define RES4328_AFE_LDO 10 /* 0x00400 */ 1102 #define RES4328_PLL_LDO 11 /* 0x00800 */ 1103 #define RES4328_BG_FILTBYP 12 /* 0x01000 */ 1104 #define RES4328_TX_FILTBYP 13 /* 0x02000 */ 1105 #define RES4328_RX_FILTBYP 14 /* 0x04000 */ 1106 #define RES4328_XTAL_PU 15 /* 0x08000 */ 1107 #define RES4328_XTAL_EN 16 /* 0x10000 */ 1108 #define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ 1109 #define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ 1110 #define RES4328_BB_PLL_PU 19 /* 0x80000 */ 1111 1112 /* 4325 A0/A1 resources */ 1113 #define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ 1114 #define RES4325_CBUCK_BURST 1 /* 0x00000002 */ 1115 #define RES4325_CBUCK_PWM 2 /* 0x00000004 */ 1116 #define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ 1117 #define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ 1118 #define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ 1119 #define RES4325_ILP_REQUEST 6 /* 0x00000040 */ 1120 #define RES4325_ABUCK_BURST 7 /* 0x00000080 */ 1121 #define RES4325_ABUCK_PWM 8 /* 0x00000100 */ 1122 #define RES4325_LNLDO1_PU 9 /* 0x00000200 */ 1123 #define RES4325_OTP_PU 10 /* 0x00000400 */ 1124 #define RES4325_LNLDO3_PU 11 /* 0x00000800 */ 1125 #define RES4325_LNLDO4_PU 12 /* 0x00001000 */ 1126 #define RES4325_XTAL_PU 13 /* 0x00002000 */ 1127 #define RES4325_ALP_AVAIL 14 /* 0x00004000 */ 1128 #define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ 1129 #define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ 1130 #define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1131 #define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1132 #define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ 1133 #define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1134 #define RES4325_HT_AVAIL 21 /* 0x00200000 */ 1135 1136 /* 4325 B0/C0 resources */ 1137 #define RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */ 1138 #define RES4325B0_CBUCK_BURST 2 /* 0x00000004 */ 1139 #define RES4325B0_CBUCK_PWM 3 /* 0x00000008 */ 1140 #define RES4325B0_CLDO_PU 4 /* 0x00000010 */ 1141 1142 /* 4325 C1 resources */ 1143 #define RES4325C1_LNLDO2_PU 12 /* 0x00001000 */ 1144 1145 /* 4325 chip-specific ChipStatus register bits */ 1146 #define CST4325_SPROM_OTP_SEL_MASK 0x00000003 1147 #define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ 1148 #define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ 1149 #define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */ 1150 #define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */ 1151 #define CST4325_SDIO_USB_MODE_MASK 0x00000004 1152 #define CST4325_SDIO_USB_MODE_SHIFT 2 1153 #define CST4325_RCAL_VALID_MASK 0x00000008 1154 #define CST4325_RCAL_VALID_SHIFT 3 1155 #define CST4325_RCAL_VALUE_MASK 0x000001f0 1156 #define CST4325_RCAL_VALUE_SHIFT 4 1157 #define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ 1158 #define CST4325_PMUTOP_2B_SHIFT 9 1159 1160 #define RES4329_RESERVED0 0 /* 0x00000001 */ 1161 #define RES4329_CBUCK_LPOM 1 /* 0x00000002 */ 1162 #define RES4329_CBUCK_BURST 2 /* 0x00000004 */ 1163 #define RES4329_CBUCK_PWM 3 /* 0x00000008 */ 1164 #define RES4329_CLDO_PU 4 /* 0x00000010 */ 1165 #define RES4329_PALDO_PU 5 /* 0x00000020 */ 1166 #define RES4329_ILP_REQUEST 6 /* 0x00000040 */ 1167 #define RES4329_RESERVED7 7 /* 0x00000080 */ 1168 #define RES4329_RESERVED8 8 /* 0x00000100 */ 1169 #define RES4329_LNLDO1_PU 9 /* 0x00000200 */ 1170 #define RES4329_OTP_PU 10 /* 0x00000400 */ 1171 #define RES4329_RESERVED11 11 /* 0x00000800 */ 1172 #define RES4329_LNLDO2_PU 12 /* 0x00001000 */ 1173 #define RES4329_XTAL_PU 13 /* 0x00002000 */ 1174 #define RES4329_ALP_AVAIL 14 /* 0x00004000 */ 1175 #define RES4329_RX_PWRSW_PU 15 /* 0x00008000 */ 1176 #define RES4329_TX_PWRSW_PU 16 /* 0x00010000 */ 1177 #define RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1178 #define RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1179 #define RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */ 1180 #define RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1181 #define RES4329_HT_AVAIL 21 /* 0x00200000 */ 1182 1183 #define CST4329_SPROM_OTP_SEL_MASK 0x00000003 1184 #define CST4329_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ 1185 #define CST4329_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ 1186 #define CST4329_OTP_SEL 2 /* OTP is powered up, no SPROM */ 1187 #define CST4329_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */ 1188 #define CST4329_SPI_SDIO_MODE_MASK 0x00000004 1189 #define CST4329_SPI_SDIO_MODE_SHIFT 2 1190 1191 /* 4312 chip-specific ChipStatus register bits */ 1192 #define CST4312_SPROM_OTP_SEL_MASK 0x00000003 1193 #define CST4312_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ 1194 #define CST4312_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ 1195 #define CST4312_OTP_SEL 2 /* OTP is powered up, no SPROM */ 1196 #define CST4312_OTP_BAD 3 /* OTP is broken, SPROM is present */ 1197 1198 /* 4312 resources (all PMU chips with little memory constraint) */ 1199 #define RES4312_SWITCHER_BURST 0 /* 0x00000001 */ 1200 #define RES4312_SWITCHER_PWM 1 /* 0x00000002 */ 1201 #define RES4312_PA_REF_LDO 2 /* 0x00000004 */ 1202 #define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ 1203 #define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ 1204 #define RES4312_RADIO_LDO 5 /* 0x00000020 */ 1205 #define RES4312_ILP_REQUEST 6 /* 0x00000040 */ 1206 #define RES4312_BG_FILTBYP 7 /* 0x00000080 */ 1207 #define RES4312_TX_FILTBYP 8 /* 0x00000100 */ 1208 #define RES4312_RX_FILTBYP 9 /* 0x00000200 */ 1209 #define RES4312_XTAL_PU 10 /* 0x00000400 */ 1210 #define RES4312_ALP_AVAIL 11 /* 0x00000800 */ 1211 #define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ 1212 #define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ 1213 #define RES4312_HT_AVAIL 14 /* 0x00004000 */ 1214 1215 /* 4322 resources */ 1216 #define RES4322_RF_LDO 0 1217 #define RES4322_ILP_REQUEST 1 1218 #define RES4322_XTAL_PU 2 1219 #define RES4322_ALP_AVAIL 3 1220 #define RES4322_SI_PLL_ON 4 1221 #define RES4322_HT_SI_AVAIL 5 1222 #define RES4322_PHY_PLL_ON 6 1223 #define RES4322_HT_PHY_AVAIL 7 1224 #define RES4322_OTP_PU 8 1225 1226 /* 4322 chip-specific ChipStatus register bits */ 1227 #define CST4322_XTAL_FREQ_20_40MHZ 0x00000020 1228 #define CST4322_SPROM_OTP_SEL_MASK 0x000000c0 1229 #define CST4322_SPROM_OTP_SEL_SHIFT 6 1230 #define CST4322_NO_SPROM_OTP 0 /* no OTP, no SPROM */ 1231 #define CST4322_SPROM_PRESENT 1 /* SPROM is present */ 1232 #define CST4322_OTP_PRESENT 2 /* OTP is present */ 1233 #define CST4322_PCI_OR_USB 0x00000100 1234 #define CST4322_BOOT_MASK 0x00000600 1235 #define CST4322_BOOT_SHIFT 9 1236 #define CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 1237 #define CST4322_BOOT_FROM_ROM 1 /* boot from ROM */ 1238 #define CST4322_BOOT_FROM_FLASH 2 /* boot from FLASH */ 1239 #define CST4322_BOOT_FROM_INVALID 3 1240 #define CST4322_ILP_DIV_EN 0x00000800 1241 #define CST4322_FLASH_TYPE_MASK 0x00001000 1242 #define CST4322_FLASH_TYPE_SHIFT 12 1243 #define CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */ 1244 #define CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /* ATMEL flash */ 1245 #define CST4322_ARM_TAP_SEL 0x00002000 1246 #define CST4322_RES_INIT_MODE_MASK 0x0000c000 1247 #define CST4322_RES_INIT_MODE_SHIFT 14 1248 #define CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */ 1249 #define CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */ 1250 #define CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */ 1251 #define CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */ 1252 #define CST4322_PCIPLLCLK_GATING 0x00010000 1253 #define CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 1254 #define CST4322_PCI_CARDBUS_MODE 0x00040000 1255 1256 /* 43224 chip-specific ChipControl register bits */ 1257 #define CCTRL43224_GPIO_TOGGLE 0x8000 1258 #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ 1259 #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ 1260 1261 /* 43236 resources */ 1262 #define RES43236_REGULATOR 0 1263 #define RES43236_ILP_REQUEST 1 1264 #define RES43236_XTAL_PU 2 1265 #define RES43236_ALP_AVAIL 3 1266 #define RES43236_SI_PLL_ON 4 1267 #define RES43236_HT_SI_AVAIL 5 1268 1269 /* 43236 chip-specific ChipControl register bits */ 1270 #define CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */ 1271 #define CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 1272 #define CCTRL43236_EXT_LNA (1<<2) /* 0 disable */ 1273 #define CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ 1274 #define CCTRL43236_GSIO (1<<4) /* 0 disable */ 1275 1276 /* 43236 Chip specific ChipStatus register bits */ 1277 #define CST43236_SFLASH_MASK 0x00000040 1278 #define CST43236_OTP_MASK 0x00000080 1279 #define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ 1280 #define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ 1281 #define CST43236_BOOT_MASK 0x00001800 1282 #define CST43236_BOOT_SHIFT 11 1283 #define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 1284 #define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ 1285 #define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ 1286 #define CST43236_BOOT_FROM_INVALID 3 1287 1288 /* 4331 resources */ 1289 #define RES4331_REGULATOR 0 1290 #define RES4331_ILP_REQUEST 1 1291 #define RES4331_XTAL_PU 2 1292 #define RES4331_ALP_AVAIL 3 1293 #define RES4331_SI_PLL_ON 4 1294 #define RES4331_HT_SI_AVAIL 5 1295 1296 /* 4331 chip-specific ChipControl register bits */ 1297 #define CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ 1298 #define CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 1299 #define CCTRL4331_EXT_LNA (1<<2) /* 0 disable */ 1300 #define CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ 1301 #define CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ 1302 #define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ 1303 #define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ 1304 #define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ 1305 #define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ 1306 #define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ 1307 #define CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */ 1308 #define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */ 1309 #define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */ 1310 #define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */ 1311 1312 /* 4331 Chip specific ChipStatus register bits */ 1313 #define CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ 1314 #define CST4331_SPROM_PRESENT 0x00000002 1315 #define CST4331_OTP_PRESENT 0x00000004 1316 #define CST4331_LDO_RF 0x00000008 1317 #define CST4331_LDO_PAR 0x00000010 1318 1319 /* 4315 resources */ 1320 #define RES4315_CBUCK_LPOM 1 /* 0x00000002 */ 1321 #define RES4315_CBUCK_BURST 2 /* 0x00000004 */ 1322 #define RES4315_CBUCK_PWM 3 /* 0x00000008 */ 1323 #define RES4315_CLDO_PU 4 /* 0x00000010 */ 1324 #define RES4315_PALDO_PU 5 /* 0x00000020 */ 1325 #define RES4315_ILP_REQUEST 6 /* 0x00000040 */ 1326 #define RES4315_LNLDO1_PU 9 /* 0x00000200 */ 1327 #define RES4315_OTP_PU 10 /* 0x00000400 */ 1328 #define RES4315_LNLDO2_PU 12 /* 0x00001000 */ 1329 #define RES4315_XTAL_PU 13 /* 0x00002000 */ 1330 #define RES4315_ALP_AVAIL 14 /* 0x00004000 */ 1331 #define RES4315_RX_PWRSW_PU 15 /* 0x00008000 */ 1332 #define RES4315_TX_PWRSW_PU 16 /* 0x00010000 */ 1333 #define RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1334 #define RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1335 #define RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */ 1336 #define RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1337 #define RES4315_HT_AVAIL 21 /* 0x00200000 */ 1338 1339 /* 4315 chip-specific ChipStatus register bits */ 1340 #define CST4315_SPROM_OTP_SEL_MASK 0x00000003 /* gpio [7:6], SDIO CIS selection */ 1341 #define CST4315_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */ 1342 #define CST4315_SPROM_SEL 0x00000001 /* use SPROM, OTP is powered up */ 1343 #define CST4315_OTP_SEL 0x00000002 /* use OTP, OTP is powered up */ 1344 #define CST4315_OTP_PWRDN 0x00000003 /* use SPROM, OTP is powered down */ 1345 #define CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */ 1346 #define CST4315_RCAL_VALID 0x00000008 1347 #define CST4315_RCAL_VALUE_MASK 0x000001f0 1348 #define CST4315_RCAL_VALUE_SHIFT 4 1349 #define CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */ 1350 #define CST4315_CBUCK_MODE_MASK 0x00000c00 1351 #define CST4315_CBUCK_MODE_BURST 0x00000400 1352 #define CST4315_CBUCK_MODE_LPBURST 0x00000c00 1353 1354 /* 4319 resources */ 1355 #define RES4319_CBUCK_LPOM 1 /* 0x00000002 */ 1356 #define RES4319_CBUCK_BURST 2 /* 0x00000004 */ 1357 #define RES4319_CBUCK_PWM 3 /* 0x00000008 */ 1358 #define RES4319_CLDO_PU 4 /* 0x00000010 */ 1359 #define RES4319_PALDO_PU 5 /* 0x00000020 */ 1360 #define RES4319_ILP_REQUEST 6 /* 0x00000040 */ 1361 #define RES4319_LNLDO1_PU 9 /* 0x00000200 */ 1362 #define RES4319_OTP_PU 10 /* 0x00000400 */ 1363 #define RES4319_LNLDO2_PU 12 /* 0x00001000 */ 1364 #define RES4319_XTAL_PU 13 /* 0x00002000 */ 1365 #define RES4319_ALP_AVAIL 14 /* 0x00004000 */ 1366 #define RES4319_RX_PWRSW_PU 15 /* 0x00008000 */ 1367 #define RES4319_TX_PWRSW_PU 16 /* 0x00010000 */ 1368 #define RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1369 #define RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1370 #define RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ 1371 #define RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1372 #define RES4319_HT_AVAIL 21 /* 0x00200000 */ 1373 1374 /* 4319 chip-specific ChipStatus register bits */ 1375 #define CST4319_SPI_CPULESSUSB 0x00000001 1376 #define CST4319_SPI_CLK_POL 0x00000002 1377 #define CST4319_SPI_CLK_PH 0x00000008 1378 #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /* gpio [7:6], SDIO CIS selection */ 1379 #define CST4319_SPROM_OTP_SEL_SHIFT 6 1380 #define CST4319_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */ 1381 #define CST4319_SPROM_SEL 0x00000040 /* use SPROM, OTP is powered up */ 1382 #define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */ 1383 #define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */ 1384 #define CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ 1385 #define CST4319_REMAP_SEL_MASK 0x00000600 1386 #define CST4319_ILPDIV_EN 0x00000800 1387 #define CST4319_XTAL_PD_POL 0x00001000 1388 #define CST4319_LPO_SEL 0x00002000 1389 #define CST4319_RES_INIT_MODE 0x0000c000 1390 #define CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ 1391 #define CST4319_CBUCK_MODE_MASK 0x00060000 1392 #define CST4319_CBUCK_MODE_BURST 0x00020000 1393 #define CST4319_CBUCK_MODE_LPBURST 0x00060000 1394 #define CST4319_RCAL_VALID 0x01000000 1395 #define CST4319_RCAL_VALUE_MASK 0x3e000000 1396 #define CST4319_RCAL_VALUE_SHIFT 25 1397 1398 #define PMU1_PLL0_CHIPCTL0 0 1399 #define PMU1_PLL0_CHIPCTL1 1 1400 #define PMU1_PLL0_CHIPCTL2 2 1401 #define CCTL_4319USB_XTAL_SEL_MASK 0x00180000 1402 #define CCTL_4319USB_XTAL_SEL_SHIFT 19 1403 #define CCTL_4319USB_48MHZ_PLL_SEL 1 1404 #define CCTL_4319USB_24MHZ_PLL_SEL 2 1405 1406 /* PMU resources for 4336 */ 1407 #define RES4336_CBUCK_LPOM 0 1408 #define RES4336_CBUCK_BURST 1 1409 #define RES4336_CBUCK_LP_PWM 2 1410 #define RES4336_CBUCK_PWM 3 1411 #define RES4336_CLDO_PU 4 1412 #define RES4336_DIS_INT_RESET_PD 5 1413 #define RES4336_ILP_REQUEST 6 1414 #define RES4336_LNLDO_PU 7 1415 #define RES4336_LDO3P3_PU 8 1416 #define RES4336_OTP_PU 9 1417 #define RES4336_XTAL_PU 10 1418 #define RES4336_ALP_AVAIL 11 1419 #define RES4336_RADIO_PU 12 1420 #define RES4336_BG_PU 13 1421 #define RES4336_VREG1p4_PU_PU 14 1422 #define RES4336_AFE_PWRSW_PU 15 1423 #define RES4336_RX_PWRSW_PU 16 1424 #define RES4336_TX_PWRSW_PU 17 1425 #define RES4336_BB_PWRSW_PU 18 1426 #define RES4336_SYNTH_PWRSW_PU 19 1427 #define RES4336_MISC_PWRSW_PU 20 1428 #define RES4336_LOGEN_PWRSW_PU 21 1429 #define RES4336_BBPLL_PWRSW_PU 22 1430 #define RES4336_MACPHY_CLKAVAIL 23 1431 #define RES4336_HT_AVAIL 24 1432 #define RES4336_RSVD 25 1433 1434 /* 4336 chip-specific ChipStatus register bits */ 1435 #define CST4336_SPI_MODE_MASK 0x00000001 1436 #define CST4336_SPROM_PRESENT 0x00000002 1437 #define CST4336_OTP_PRESENT 0x00000004 1438 #define CST4336_ARMREMAP_0 0x00000008 1439 #define CST4336_ILPDIV_EN_MASK 0x00000010 1440 #define CST4336_ILPDIV_EN_SHIFT 4 1441 #define CST4336_XTAL_PD_POL_MASK 0x00000020 1442 #define CST4336_XTAL_PD_POL_SHIFT 5 1443 #define CST4336_LPO_SEL_MASK 0x00000040 1444 #define CST4336_LPO_SEL_SHIFT 6 1445 #define CST4336_RES_INIT_MODE_MASK 0x00000180 1446 #define CST4336_RES_INIT_MODE_SHIFT 7 1447 #define CST4336_CBUCK_MODE_MASK 0x00000600 1448 #define CST4336_CBUCK_MODE_SHIFT 9 1449 1450 /* 4330 resources */ 1451 #define RES4330_CBUCK_LPOM 0 1452 #define RES4330_CBUCK_BURST 1 1453 #define RES4330_CBUCK_LP_PWM 2 1454 #define RES4330_CBUCK_PWM 3 1455 #define RES4330_CLDO_PU 4 1456 #define RES4330_DIS_INT_RESET_PD 5 1457 #define RES4330_ILP_REQUEST 6 1458 #define RES4330_LNLDO_PU 7 1459 #define RES4330_LDO3P3_PU 8 1460 #define RES4330_OTP_PU 9 1461 #define RES4330_XTAL_PU 10 1462 #define RES4330_ALP_AVAIL 11 1463 #define RES4330_RADIO_PU 12 1464 #define RES4330_BG_PU 13 1465 #define RES4330_VREG1p4_PU_PU 14 1466 #define RES4330_AFE_PWRSW_PU 15 1467 #define RES4330_RX_PWRSW_PU 16 1468 #define RES4330_TX_PWRSW_PU 17 1469 #define RES4330_BB_PWRSW_PU 18 1470 #define RES4330_SYNTH_PWRSW_PU 19 1471 #define RES4330_MISC_PWRSW_PU 20 1472 #define RES4330_LOGEN_PWRSW_PU 21 1473 #define RES4330_BBPLL_PWRSW_PU 22 1474 #define RES4330_MACPHY_CLKAVAIL 23 1475 #define RES4330_HT_AVAIL 24 1476 #define RES4330_5gRX_PWRSW_PU 25 1477 #define RES4330_5gTX_PWRSW_PU 26 1478 #define RES4330_5g_LOGEN_PWRSW_PU 27 1479 1480 /* 4330 chip-specific ChipStatus register bits */ 1481 #define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */ 1482 #define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */ 1483 #define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */ 1484 #define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */ 1485 #define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */ 1486 #define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */ 1487 #define CST4330_OTP_PRESENT 0x00000010 1488 #define CST4330_LPO_AUTODET_EN 0x00000020 1489 #define CST4330_ARMREMAP_0 0x00000040 1490 #define CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */ 1491 #define CST4330_ILPDIV_EN 0x00000100 1492 #define CST4330_LPO_SEL 0x00000200 1493 #define CST4330_RES_INIT_MODE_SHIFT 10 1494 #define CST4330_RES_INIT_MODE_MASK 0x00000c00 1495 #define CST4330_CBUCK_MODE_SHIFT 12 1496 #define CST4330_CBUCK_MODE_MASK 0x00003000 1497 #define CST4330_CBUCK_POWER_OK 0x00004000 1498 #define CST4330_BB_PLL_LOCKED 0x00008000 1499 #define SOCDEVRAM_4330_BP_ADDR 0x1E000000 1500 #define SOCDEVRAM_4330_ARM_ADDR 0x00800000 1501 1502 /* 4313 resources */ 1503 #define RES4313_BB_PU_RSRC 0 1504 #define RES4313_ILP_REQ_RSRC 1 1505 #define RES4313_XTAL_PU_RSRC 2 1506 #define RES4313_ALP_AVAIL_RSRC 3 1507 #define RES4313_RADIO_PU_RSRC 4 1508 #define RES4313_BG_PU_RSRC 5 1509 #define RES4313_VREG1P4_PU_RSRC 6 1510 #define RES4313_AFE_PWRSW_RSRC 7 1511 #define RES4313_RX_PWRSW_RSRC 8 1512 #define RES4313_TX_PWRSW_RSRC 9 1513 #define RES4313_BB_PWRSW_RSRC 10 1514 #define RES4313_SYNTH_PWRSW_RSRC 11 1515 #define RES4313_MISC_PWRSW_RSRC 12 1516 #define RES4313_BB_PLL_PWRSW_RSRC 13 1517 #define RES4313_HT_AVAIL_RSRC 14 1518 #define RES4313_MACPHY_CLK_AVAIL_RSRC 15 1519 1520 /* 4313 chip-specific ChipStatus register bits */ 1521 #define CST4313_SPROM_PRESENT 1 1522 #define CST4313_OTP_PRESENT 2 1523 #define CST4313_SPROM_OTP_SEL_MASK 0x00000002 1524 #define CST4313_SPROM_OTP_SEL_SHIFT 0 1525 1526 /* 4313 Chip specific ChipControl register bits */ 1527 #define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ 1528 1529 /* 43228 resources */ 1530 #define RES43228_NOT_USED 0 1531 #define RES43228_ILP_REQUEST 1 1532 #define RES43228_XTAL_PU 2 1533 #define RES43228_ALP_AVAIL 3 1534 #define RES43228_PLL_EN 4 1535 #define RES43228_HT_PHY_AVAIL 5 1536 1537 /* 43228 chipstatus reg bits */ 1538 #define CST43228_ILP_DIV_EN 0x1 1539 #define CST43228_OTP_PRESENT 0x2 1540 #define CST43228_SERDES_REFCLK_PADSEL 0x4 1541 #define CST43228_SDIO_MODE 0x8 1542 1543 #define CST43228_SDIO_OTP_PRESENT 0x10 1544 #define CST43228_SDIO_RESET 0x20 1545 1546 /* 1547 * Maximum delay for the PMU state transition in us. 1548 * This is an upper bound intended for spinwaits etc. 1549 */ 1550 #define PMU_MAX_TRANSITION_DLY 15000 1551 1552 /* PMU resource up transition time in ILP cycles */ 1553 #define PMURES_UP_TRANSITION 2 1554 1555 /* 1556 * Register eci_inputlo bitfield values. 1557 * - BT packet type information bits [7:0] 1558 */ 1559 /* [3:0] - Task (link) type */ 1560 #define BT_ACL 0x00 1561 #define BT_SCO 0x01 1562 #define BT_eSCO 0x02 1563 #define BT_A2DP 0x03 1564 #define BT_SNIFF 0x04 1565 #define BT_PAGE_SCAN 0x05 1566 #define BT_INQUIRY_SCAN 0x06 1567 #define BT_PAGE 0x07 1568 #define BT_INQUIRY 0x08 1569 #define BT_MSS 0x09 1570 #define BT_PARK 0x0a 1571 #define BT_RSSISCAN 0x0b 1572 #define BT_MD_ACL 0x0c 1573 #define BT_MD_eSCO 0x0d 1574 #define BT_SCAN_WITH_SCO_LINK 0x0e 1575 #define BT_SCAN_WITHOUT_SCO_LINK 0x0f 1576 /* [7:4] = packet duration code */ 1577 /* [8] - Master / Slave */ 1578 #define BT_MASTER 0 1579 #define BT_SLAVE 1 1580 /* [11:9] - multi-level priority */ 1581 #define BT_LOWEST_PRIO 0x0 1582 #define BT_HIGHEST_PRIO 0x3 1583 1584 /* WLAN - number of antenna */ 1585 #define WLAN_NUM_ANT1 TXANT_0 1586 #define WLAN_NUM_ANT2 TXANT_1 1587 1588 #endif /* _SBCHIPC_H */ 1589