1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *  FUJITSU Extended Socket Network Device driver
4  *  Copyright (c) 2015 FUJITSU LIMITED
5  */
6 
7 #ifndef FJES_REGS_H_
8 #define FJES_REGS_H_
9 
10 #include <linux/bitops.h>
11 
12 #define XSCT_DEVICE_REGISTER_SIZE 0x1000
13 
14 /* register offset */
15 /* Information registers */
16 #define XSCT_OWNER_EPID     0x0000  /* Owner EPID */
17 #define XSCT_MAX_EP         0x0004  /* Maximum EP */
18 
19 /* Device Control registers */
20 #define XSCT_DCTL           0x0010  /* Device Control */
21 
22 /* Command Control registers */
23 #define XSCT_CR             0x0020  /* Command request */
24 #define XSCT_CS             0x0024  /* Command status */
25 #define XSCT_SHSTSAL        0x0028  /* Share status address Low */
26 #define XSCT_SHSTSAH        0x002C  /* Share status address High */
27 
28 #define XSCT_REQBL          0x0034  /* Request Buffer length */
29 #define XSCT_REQBAL         0x0038  /* Request Buffer Address Low */
30 #define XSCT_REQBAH         0x003C  /* Request Buffer Address High */
31 
32 #define XSCT_RESPBL         0x0044  /* Response Buffer Length */
33 #define XSCT_RESPBAL        0x0048  /* Response Buffer Address Low */
34 #define XSCT_RESPBAH        0x004C  /* Response Buffer Address High */
35 
36 /* Interrupt Control registers */
37 #define XSCT_IS             0x0080  /* Interrupt status */
38 #define XSCT_IMS            0x0084  /* Interrupt mask set */
39 #define XSCT_IMC            0x0088  /* Interrupt mask clear */
40 #define XSCT_IG             0x008C  /* Interrupt generator */
41 #define XSCT_ICTL           0x0090  /* Interrupt control */
42 
43 /* register structure */
44 /* Information registers */
45 union REG_OWNER_EPID {
46 	struct {
47 		__le32 epid:16;
48 		__le32:16;
49 	} bits;
50 	__le32 reg;
51 };
52 
53 union REG_MAX_EP {
54 	struct {
55 		__le32 maxep:16;
56 		__le32:16;
57 	} bits;
58 	__le32 reg;
59 };
60 
61 /* Device Control registers */
62 union REG_DCTL {
63 	struct {
64 		__le32 reset:1;
65 		__le32 rsv0:15;
66 		__le32 rsv1:16;
67 	} bits;
68 	__le32 reg;
69 };
70 
71 /* Command Control registers */
72 union REG_CR {
73 	struct {
74 		__le32 req_code:16;
75 		__le32 err_info:14;
76 		__le32 error:1;
77 		__le32 req_start:1;
78 	} bits;
79 	__le32 reg;
80 };
81 
82 union REG_CS {
83 	struct {
84 		__le32 req_code:16;
85 		__le32 rsv0:14;
86 		__le32 busy:1;
87 		__le32 complete:1;
88 	} bits;
89 	__le32 reg;
90 };
91 
92 /* Interrupt Control registers */
93 union REG_ICTL {
94 	struct {
95 		__le32 automak:1;
96 		__le32 rsv0:31;
97 	} bits;
98 	__le32 reg;
99 };
100 
101 enum REG_ICTL_MASK {
102 	REG_ICTL_MASK_INFO_UPDATE     = 1 << 20,
103 	REG_ICTL_MASK_DEV_STOP_REQ    = 1 << 19,
104 	REG_ICTL_MASK_TXRX_STOP_REQ   = 1 << 18,
105 	REG_ICTL_MASK_TXRX_STOP_DONE  = 1 << 17,
106 	REG_ICTL_MASK_RX_DATA         = 1 << 16,
107 	REG_ICTL_MASK_ALL             = GENMASK(20, 16),
108 };
109 
110 enum REG_IS_MASK {
111 	REG_IS_MASK_IS_ASSERT	= 1 << 31,
112 	REG_IS_MASK_EPID	= GENMASK(15, 0),
113 };
114 
115 struct fjes_hw;
116 
117 u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg);
118 
119 #define wr32(reg, val) \
120 do { \
121 	u8 *base = hw->base; \
122 	writel((val), &base[(reg)]); \
123 } while (0)
124 
125 #define rd32(reg) (fjes_hw_rd32(hw, reg))
126 
127 #endif /* FJES_REGS_H_ */
128