1 /* bnx2x_sp.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2011-2012 Broadcom Corporation 4 * 5 * Unless you and Broadcom execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Broadcom software provided under a 12 * license other than the GPL, without Broadcom's express prior written 13 * consent. 14 * 15 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16 * Written by: Vladislav Zolotarov 17 * 18 */ 19 #ifndef BNX2X_SP_VERBS 20 #define BNX2X_SP_VERBS 21 22 struct bnx2x; 23 struct eth_context; 24 25 /* Bits representing general command's configuration */ 26 enum { 27 RAMROD_TX, 28 RAMROD_RX, 29 /* Wait until all pending commands complete */ 30 RAMROD_COMP_WAIT, 31 /* Don't send a ramrod, only update a registry */ 32 RAMROD_DRV_CLR_ONLY, 33 /* Configure HW according to the current object state */ 34 RAMROD_RESTORE, 35 /* Execute the next command now */ 36 RAMROD_EXEC, 37 /* 38 * Don't add a new command and continue execution of posponed 39 * commands. If not set a new command will be added to the 40 * pending commands list. 41 */ 42 RAMROD_CONT, 43 }; 44 45 typedef enum { 46 BNX2X_OBJ_TYPE_RX, 47 BNX2X_OBJ_TYPE_TX, 48 BNX2X_OBJ_TYPE_RX_TX, 49 } bnx2x_obj_type; 50 51 /* Filtering states */ 52 enum { 53 BNX2X_FILTER_MAC_PENDING, 54 BNX2X_FILTER_VLAN_PENDING, 55 BNX2X_FILTER_VLAN_MAC_PENDING, 56 BNX2X_FILTER_RX_MODE_PENDING, 57 BNX2X_FILTER_RX_MODE_SCHED, 58 BNX2X_FILTER_ISCSI_ETH_START_SCHED, 59 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 60 BNX2X_FILTER_FCOE_ETH_START_SCHED, 61 BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 62 BNX2X_FILTER_MCAST_PENDING, 63 BNX2X_FILTER_MCAST_SCHED, 64 BNX2X_FILTER_RSS_CONF_PENDING, 65 }; 66 67 struct bnx2x_raw_obj { 68 u8 func_id; 69 70 /* Queue params */ 71 u8 cl_id; 72 u32 cid; 73 74 /* Ramrod data buffer params */ 75 void *rdata; 76 dma_addr_t rdata_mapping; 77 78 /* Ramrod state params */ 79 int state; /* "ramrod is pending" state bit */ 80 unsigned long *pstate; /* pointer to state buffer */ 81 82 bnx2x_obj_type obj_type; 83 84 int (*wait_comp)(struct bnx2x *bp, 85 struct bnx2x_raw_obj *o); 86 87 bool (*check_pending)(struct bnx2x_raw_obj *o); 88 void (*clear_pending)(struct bnx2x_raw_obj *o); 89 void (*set_pending)(struct bnx2x_raw_obj *o); 90 }; 91 92 /************************* VLAN-MAC commands related parameters ***************/ 93 struct bnx2x_mac_ramrod_data { 94 u8 mac[ETH_ALEN]; 95 }; 96 97 struct bnx2x_vlan_ramrod_data { 98 u16 vlan; 99 }; 100 101 struct bnx2x_vlan_mac_ramrod_data { 102 u8 mac[ETH_ALEN]; 103 u16 vlan; 104 }; 105 106 union bnx2x_classification_ramrod_data { 107 struct bnx2x_mac_ramrod_data mac; 108 struct bnx2x_vlan_ramrod_data vlan; 109 struct bnx2x_vlan_mac_ramrod_data vlan_mac; 110 }; 111 112 /* VLAN_MAC commands */ 113 enum bnx2x_vlan_mac_cmd { 114 BNX2X_VLAN_MAC_ADD, 115 BNX2X_VLAN_MAC_DEL, 116 BNX2X_VLAN_MAC_MOVE, 117 }; 118 119 struct bnx2x_vlan_mac_data { 120 /* Requested command: BNX2X_VLAN_MAC_XX */ 121 enum bnx2x_vlan_mac_cmd cmd; 122 /* 123 * used to contain the data related vlan_mac_flags bits from 124 * ramrod parameters. 125 */ 126 unsigned long vlan_mac_flags; 127 128 /* Needed for MOVE command */ 129 struct bnx2x_vlan_mac_obj *target_obj; 130 131 union bnx2x_classification_ramrod_data u; 132 }; 133 134 /*************************** Exe Queue obj ************************************/ 135 union bnx2x_exe_queue_cmd_data { 136 struct bnx2x_vlan_mac_data vlan_mac; 137 138 struct { 139 /* TODO */ 140 } mcast; 141 }; 142 143 struct bnx2x_exeq_elem { 144 struct list_head link; 145 146 /* Length of this element in the exe_chunk. */ 147 int cmd_len; 148 149 union bnx2x_exe_queue_cmd_data cmd_data; 150 }; 151 152 union bnx2x_qable_obj; 153 154 union bnx2x_exeq_comp_elem { 155 union event_ring_elem *elem; 156 }; 157 158 struct bnx2x_exe_queue_obj; 159 160 typedef int (*exe_q_validate)(struct bnx2x *bp, 161 union bnx2x_qable_obj *o, 162 struct bnx2x_exeq_elem *elem); 163 164 typedef int (*exe_q_remove)(struct bnx2x *bp, 165 union bnx2x_qable_obj *o, 166 struct bnx2x_exeq_elem *elem); 167 168 /** 169 * @return positive is entry was optimized, 0 - if not, negative 170 * in case of an error. 171 */ 172 typedef int (*exe_q_optimize)(struct bnx2x *bp, 173 union bnx2x_qable_obj *o, 174 struct bnx2x_exeq_elem *elem); 175 typedef int (*exe_q_execute)(struct bnx2x *bp, 176 union bnx2x_qable_obj *o, 177 struct list_head *exe_chunk, 178 unsigned long *ramrod_flags); 179 typedef struct bnx2x_exeq_elem * 180 (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 181 struct bnx2x_exeq_elem *elem); 182 183 struct bnx2x_exe_queue_obj { 184 /* 185 * Commands pending for an execution. 186 */ 187 struct list_head exe_queue; 188 189 /* 190 * Commands pending for an completion. 191 */ 192 struct list_head pending_comp; 193 194 spinlock_t lock; 195 196 /* Maximum length of commands' list for one execution */ 197 int exe_chunk_len; 198 199 union bnx2x_qable_obj *owner; 200 201 /****** Virtual functions ******/ 202 /** 203 * Called before commands execution for commands that are really 204 * going to be executed (after 'optimize'). 205 * 206 * Must run under exe_queue->lock 207 */ 208 exe_q_validate validate; 209 210 /** 211 * Called before removing pending commands, cleaning allocated 212 * resources (e.g., credits from validate) 213 */ 214 exe_q_remove remove; 215 216 /** 217 * This will try to cancel the current pending commands list 218 * considering the new command. 219 * 220 * Returns the number of optimized commands or a negative error code 221 * 222 * Must run under exe_queue->lock 223 */ 224 exe_q_optimize optimize; 225 226 /** 227 * Run the next commands chunk (owner specific). 228 */ 229 exe_q_execute execute; 230 231 /** 232 * Return the exe_queue element containing the specific command 233 * if any. Otherwise return NULL. 234 */ 235 exe_q_get get; 236 }; 237 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 238 /* 239 * Element in the VLAN_MAC registry list having all currenty configured 240 * rules. 241 */ 242 struct bnx2x_vlan_mac_registry_elem { 243 struct list_head link; 244 245 /* 246 * Used to store the cam offset used for the mac/vlan/vlan-mac. 247 * Relevant for 57710 and 57711 only. VLANs and MACs share the 248 * same CAM for these chips. 249 */ 250 int cam_offset; 251 252 /* Needed for DEL and RESTORE flows */ 253 unsigned long vlan_mac_flags; 254 255 union bnx2x_classification_ramrod_data u; 256 }; 257 258 /* Bits representing VLAN_MAC commands specific flags */ 259 enum { 260 BNX2X_UC_LIST_MAC, 261 BNX2X_ETH_MAC, 262 BNX2X_ISCSI_ETH_MAC, 263 BNX2X_NETQ_ETH_MAC, 264 BNX2X_DONT_CONSUME_CAM_CREDIT, 265 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 266 }; 267 268 struct bnx2x_vlan_mac_ramrod_params { 269 /* Object to run the command from */ 270 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 271 272 /* General command flags: COMP_WAIT, etc. */ 273 unsigned long ramrod_flags; 274 275 /* Command specific configuration request */ 276 struct bnx2x_vlan_mac_data user_req; 277 }; 278 279 struct bnx2x_vlan_mac_obj { 280 struct bnx2x_raw_obj raw; 281 282 /* Bookkeeping list: will prevent the addition of already existing 283 * entries. 284 */ 285 struct list_head head; 286 287 /* TODO: Add it's initialization in the init functions */ 288 struct bnx2x_exe_queue_obj exe_queue; 289 290 /* MACs credit pool */ 291 struct bnx2x_credit_pool_obj *macs_pool; 292 293 /* VLANs credit pool */ 294 struct bnx2x_credit_pool_obj *vlans_pool; 295 296 /* RAMROD command to be used */ 297 int ramrod_cmd; 298 299 /* copy first n elements onto preallocated buffer 300 * 301 * @param n number of elements to get 302 * @param buf buffer preallocated by caller into which elements 303 * will be copied. Note elements are 4-byte aligned 304 * so buffer size must be able to accomodate the 305 * aligned elements. 306 * 307 * @return number of copied bytes 308 */ 309 int (*get_n_elements)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 310 int n, u8 *buf); 311 312 /** 313 * Checks if ADD-ramrod with the given params may be performed. 314 * 315 * @return zero if the element may be added 316 */ 317 318 int (*check_add)(struct bnx2x *bp, 319 struct bnx2x_vlan_mac_obj *o, 320 union bnx2x_classification_ramrod_data *data); 321 322 /** 323 * Checks if DEL-ramrod with the given params may be performed. 324 * 325 * @return true if the element may be deleted 326 */ 327 struct bnx2x_vlan_mac_registry_elem * 328 (*check_del)(struct bnx2x *bp, 329 struct bnx2x_vlan_mac_obj *o, 330 union bnx2x_classification_ramrod_data *data); 331 332 /** 333 * Checks if DEL-ramrod with the given params may be performed. 334 * 335 * @return true if the element may be deleted 336 */ 337 bool (*check_move)(struct bnx2x *bp, 338 struct bnx2x_vlan_mac_obj *src_o, 339 struct bnx2x_vlan_mac_obj *dst_o, 340 union bnx2x_classification_ramrod_data *data); 341 342 /** 343 * Update the relevant credit object(s) (consume/return 344 * correspondingly). 345 */ 346 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 347 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 348 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 349 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 350 351 /** 352 * Configures one rule in the ramrod data buffer. 353 */ 354 void (*set_one_rule)(struct bnx2x *bp, 355 struct bnx2x_vlan_mac_obj *o, 356 struct bnx2x_exeq_elem *elem, int rule_idx, 357 int cam_offset); 358 359 /** 360 * Delete all configured elements having the given 361 * vlan_mac_flags specification. Assumes no pending for 362 * execution commands. Will schedule all all currently 363 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 364 * specification for deletion and will use the given 365 * ramrod_flags for the last DEL operation. 366 * 367 * @param bp 368 * @param o 369 * @param ramrod_flags RAMROD_XX flags 370 * 371 * @return 0 if the last operation has completed successfully 372 * and there are no more elements left, positive value 373 * if there are pending for completion commands, 374 * negative value in case of failure. 375 */ 376 int (*delete_all)(struct bnx2x *bp, 377 struct bnx2x_vlan_mac_obj *o, 378 unsigned long *vlan_mac_flags, 379 unsigned long *ramrod_flags); 380 381 /** 382 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 383 * configured elements list. 384 * 385 * @param bp 386 * @param p Command parameters (RAMROD_COMP_WAIT bit in 387 * ramrod_flags is only taken into an account) 388 * @param ppos a pointer to the cooky that should be given back in the 389 * next call to make function handle the next element. If 390 * *ppos is set to NULL it will restart the iterator. 391 * If returned *ppos == NULL this means that the last 392 * element has been handled. 393 * 394 * @return int 395 */ 396 int (*restore)(struct bnx2x *bp, 397 struct bnx2x_vlan_mac_ramrod_params *p, 398 struct bnx2x_vlan_mac_registry_elem **ppos); 399 400 /** 401 * Should be called on a completion arival. 402 * 403 * @param bp 404 * @param o 405 * @param cqe Completion element we are handling 406 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 407 * pending commands will be executed. 408 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 409 * may also be set if needed. 410 * 411 * @return 0 if there are neither pending nor waiting for 412 * completion commands. Positive value if there are 413 * pending for execution or for completion commands. 414 * Negative value in case of an error (including an 415 * error in the cqe). 416 */ 417 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 418 union event_ring_elem *cqe, 419 unsigned long *ramrod_flags); 420 421 /** 422 * Wait for completion of all commands. Don't schedule new ones, 423 * just wait. It assumes that the completion code will schedule 424 * for new commands. 425 */ 426 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 427 }; 428 429 enum { 430 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 431 BNX2X_LLH_CAM_ETH_LINE, 432 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 433 }; 434 435 436 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 437 438 /* RX_MODE ramrod spesial flags: set in rx_mode_flags field in 439 * a bnx2x_rx_mode_ramrod_params. 440 */ 441 enum { 442 BNX2X_RX_MODE_FCOE_ETH, 443 BNX2X_RX_MODE_ISCSI_ETH, 444 }; 445 446 enum { 447 BNX2X_ACCEPT_UNICAST, 448 BNX2X_ACCEPT_MULTICAST, 449 BNX2X_ACCEPT_ALL_UNICAST, 450 BNX2X_ACCEPT_ALL_MULTICAST, 451 BNX2X_ACCEPT_BROADCAST, 452 BNX2X_ACCEPT_UNMATCHED, 453 BNX2X_ACCEPT_ANY_VLAN 454 }; 455 456 struct bnx2x_rx_mode_ramrod_params { 457 struct bnx2x_rx_mode_obj *rx_mode_obj; 458 unsigned long *pstate; 459 int state; 460 u8 cl_id; 461 u32 cid; 462 u8 func_id; 463 unsigned long ramrod_flags; 464 unsigned long rx_mode_flags; 465 466 /* 467 * rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 468 * a tstorm_eth_mac_filter_config (e1x). 469 */ 470 void *rdata; 471 dma_addr_t rdata_mapping; 472 473 /* Rx mode settings */ 474 unsigned long rx_accept_flags; 475 476 /* internal switching settings */ 477 unsigned long tx_accept_flags; 478 }; 479 480 struct bnx2x_rx_mode_obj { 481 int (*config_rx_mode)(struct bnx2x *bp, 482 struct bnx2x_rx_mode_ramrod_params *p); 483 484 int (*wait_comp)(struct bnx2x *bp, 485 struct bnx2x_rx_mode_ramrod_params *p); 486 }; 487 488 /********************** Set multicast group ***********************************/ 489 490 struct bnx2x_mcast_list_elem { 491 struct list_head link; 492 u8 *mac; 493 }; 494 495 union bnx2x_mcast_config_data { 496 u8 *mac; 497 u8 bin; /* used in a RESTORE flow */ 498 }; 499 500 struct bnx2x_mcast_ramrod_params { 501 struct bnx2x_mcast_obj *mcast_obj; 502 503 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 504 unsigned long ramrod_flags; 505 506 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 507 /** TODO: 508 * - rename it to macs_num. 509 * - Add a new command type for handling pending commands 510 * (remove "zero semantics"). 511 * 512 * Length of mcast_list. If zero and ADD_CONT command - post 513 * pending commands. 514 */ 515 int mcast_list_len; 516 }; 517 518 enum { 519 BNX2X_MCAST_CMD_ADD, 520 BNX2X_MCAST_CMD_CONT, 521 BNX2X_MCAST_CMD_DEL, 522 BNX2X_MCAST_CMD_RESTORE, 523 }; 524 525 struct bnx2x_mcast_obj { 526 struct bnx2x_raw_obj raw; 527 528 union { 529 struct { 530 #define BNX2X_MCAST_BINS_NUM 256 531 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 532 u64 vec[BNX2X_MCAST_VEC_SZ]; 533 534 /** Number of BINs to clear. Should be updated 535 * immediately when a command arrives in order to 536 * properly create DEL commands. 537 */ 538 int num_bins_set; 539 } aprox_match; 540 541 struct { 542 struct list_head macs; 543 int num_macs_set; 544 } exact_match; 545 } registry; 546 547 /* Pending commands */ 548 struct list_head pending_cmds_head; 549 550 /* A state that is set in raw.pstate, when there are pending commands */ 551 int sched_state; 552 553 /* Maximal number of mcast MACs configured in one command */ 554 int max_cmd_len; 555 556 /* Total number of currently pending MACs to configure: both 557 * in the pending commands list and in the current command. 558 */ 559 int total_pending_num; 560 561 u8 engine_id; 562 563 /** 564 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 565 */ 566 int (*config_mcast)(struct bnx2x *bp, 567 struct bnx2x_mcast_ramrod_params *p, int cmd); 568 569 /** 570 * Fills the ramrod data during the RESTORE flow. 571 * 572 * @param bp 573 * @param o 574 * @param start_idx Registry index to start from 575 * @param rdata_idx Index in the ramrod data to start from 576 * 577 * @return -1 if we handled the whole registry or index of the last 578 * handled registry element. 579 */ 580 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 581 int start_bin, int *rdata_idx); 582 583 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 584 struct bnx2x_mcast_ramrod_params *p, int cmd); 585 586 void (*set_one_rule)(struct bnx2x *bp, 587 struct bnx2x_mcast_obj *o, int idx, 588 union bnx2x_mcast_config_data *cfg_data, int cmd); 589 590 /** Checks if there are more mcast MACs to be set or a previous 591 * command is still pending. 592 */ 593 bool (*check_pending)(struct bnx2x_mcast_obj *o); 594 595 /** 596 * Set/Clear/Check SCHEDULED state of the object 597 */ 598 void (*set_sched)(struct bnx2x_mcast_obj *o); 599 void (*clear_sched)(struct bnx2x_mcast_obj *o); 600 bool (*check_sched)(struct bnx2x_mcast_obj *o); 601 602 /* Wait until all pending commands complete */ 603 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 604 605 /** 606 * Handle the internal object counters needed for proper 607 * commands handling. Checks that the provided parameters are 608 * feasible. 609 */ 610 int (*validate)(struct bnx2x *bp, 611 struct bnx2x_mcast_ramrod_params *p, int cmd); 612 613 /** 614 * Restore the values of internal counters in case of a failure. 615 */ 616 void (*revert)(struct bnx2x *bp, 617 struct bnx2x_mcast_ramrod_params *p, 618 int old_num_bins); 619 620 int (*get_registry_size)(struct bnx2x_mcast_obj *o); 621 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 622 }; 623 624 /*************************** Credit handling **********************************/ 625 struct bnx2x_credit_pool_obj { 626 627 /* Current amount of credit in the pool */ 628 atomic_t credit; 629 630 /* Maximum allowed credit. put() will check against it. */ 631 int pool_sz; 632 633 /* 634 * Allocate a pool table statically. 635 * 636 * Currently the mamimum allowed size is MAX_MAC_CREDIT_E2(272) 637 * 638 * The set bit in the table will mean that the entry is available. 639 */ 640 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 641 u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 642 643 /* Base pool offset (initialized differently */ 644 int base_pool_offset; 645 646 /** 647 * Get the next free pool entry. 648 * 649 * @return true if there was a free entry in the pool 650 */ 651 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 652 653 /** 654 * Return the entry back to the pool. 655 * 656 * @return true if entry is legal and has been successfully 657 * returned to the pool. 658 */ 659 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 660 661 /** 662 * Get the requested amount of credit from the pool. 663 * 664 * @param cnt Amount of requested credit 665 * @return true if the operation is successful 666 */ 667 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 668 669 /** 670 * Returns the credit to the pool. 671 * 672 * @param cnt Amount of credit to return 673 * @return true if the operation is successful 674 */ 675 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 676 677 /** 678 * Reads the current amount of credit. 679 */ 680 int (*check)(struct bnx2x_credit_pool_obj *o); 681 }; 682 683 /*************************** RSS configuration ********************************/ 684 enum { 685 /* RSS_MODE bits are mutually exclusive */ 686 BNX2X_RSS_MODE_DISABLED, 687 BNX2X_RSS_MODE_REGULAR, 688 BNX2X_RSS_MODE_VLAN_PRI, 689 BNX2X_RSS_MODE_E1HOV_PRI, 690 BNX2X_RSS_MODE_IP_DSCP, 691 692 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 693 694 BNX2X_RSS_IPV4, 695 BNX2X_RSS_IPV4_TCP, 696 BNX2X_RSS_IPV6, 697 BNX2X_RSS_IPV6_TCP, 698 }; 699 700 struct bnx2x_config_rss_params { 701 struct bnx2x_rss_config_obj *rss_obj; 702 703 /* may have RAMROD_COMP_WAIT set only */ 704 unsigned long ramrod_flags; 705 706 /* BNX2X_RSS_X bits */ 707 unsigned long rss_flags; 708 709 /* Number hash bits to take into an account */ 710 u8 rss_result_mask; 711 712 /* Indirection table */ 713 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 714 715 /* RSS hash values */ 716 u32 rss_key[10]; 717 718 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 719 u16 toe_rss_bitmap; 720 }; 721 722 struct bnx2x_rss_config_obj { 723 struct bnx2x_raw_obj raw; 724 725 /* RSS engine to use */ 726 u8 engine_id; 727 728 /* Last configured indirection table */ 729 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 730 731 int (*config_rss)(struct bnx2x *bp, 732 struct bnx2x_config_rss_params *p); 733 }; 734 735 /*********************** Queue state update ***********************************/ 736 737 /* UPDATE command options */ 738 enum { 739 BNX2X_Q_UPDATE_IN_VLAN_REM, 740 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 741 BNX2X_Q_UPDATE_OUT_VLAN_REM, 742 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 743 BNX2X_Q_UPDATE_ANTI_SPOOF, 744 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 745 BNX2X_Q_UPDATE_ACTIVATE, 746 BNX2X_Q_UPDATE_ACTIVATE_CHNG, 747 BNX2X_Q_UPDATE_DEF_VLAN_EN, 748 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 749 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 750 BNX2X_Q_UPDATE_SILENT_VLAN_REM 751 }; 752 753 /* Allowed Queue states */ 754 enum bnx2x_q_state { 755 BNX2X_Q_STATE_RESET, 756 BNX2X_Q_STATE_INITIALIZED, 757 BNX2X_Q_STATE_ACTIVE, 758 BNX2X_Q_STATE_MULTI_COS, 759 BNX2X_Q_STATE_MCOS_TERMINATED, 760 BNX2X_Q_STATE_INACTIVE, 761 BNX2X_Q_STATE_STOPPED, 762 BNX2X_Q_STATE_TERMINATED, 763 BNX2X_Q_STATE_FLRED, 764 BNX2X_Q_STATE_MAX, 765 }; 766 767 /* Allowed commands */ 768 enum bnx2x_queue_cmd { 769 BNX2X_Q_CMD_INIT, 770 BNX2X_Q_CMD_SETUP, 771 BNX2X_Q_CMD_SETUP_TX_ONLY, 772 BNX2X_Q_CMD_DEACTIVATE, 773 BNX2X_Q_CMD_ACTIVATE, 774 BNX2X_Q_CMD_UPDATE, 775 BNX2X_Q_CMD_UPDATE_TPA, 776 BNX2X_Q_CMD_HALT, 777 BNX2X_Q_CMD_CFC_DEL, 778 BNX2X_Q_CMD_TERMINATE, 779 BNX2X_Q_CMD_EMPTY, 780 BNX2X_Q_CMD_MAX, 781 }; 782 783 /* queue SETUP + INIT flags */ 784 enum { 785 BNX2X_Q_FLG_TPA, 786 BNX2X_Q_FLG_TPA_IPV6, 787 BNX2X_Q_FLG_TPA_GRO, 788 BNX2X_Q_FLG_STATS, 789 BNX2X_Q_FLG_ZERO_STATS, 790 BNX2X_Q_FLG_ACTIVE, 791 BNX2X_Q_FLG_OV, 792 BNX2X_Q_FLG_VLAN, 793 BNX2X_Q_FLG_COS, 794 BNX2X_Q_FLG_HC, 795 BNX2X_Q_FLG_HC_EN, 796 BNX2X_Q_FLG_DHC, 797 BNX2X_Q_FLG_FCOE, 798 BNX2X_Q_FLG_LEADING_RSS, 799 BNX2X_Q_FLG_MCAST, 800 BNX2X_Q_FLG_DEF_VLAN, 801 BNX2X_Q_FLG_TX_SWITCH, 802 BNX2X_Q_FLG_TX_SEC, 803 BNX2X_Q_FLG_ANTI_SPOOF, 804 BNX2X_Q_FLG_SILENT_VLAN_REM 805 }; 806 807 /* Queue type options: queue type may be a compination of below. */ 808 enum bnx2x_q_type { 809 /** TODO: Consider moving both these flags into the init() 810 * ramrod params. 811 */ 812 BNX2X_Q_TYPE_HAS_RX, 813 BNX2X_Q_TYPE_HAS_TX, 814 }; 815 816 #define BNX2X_PRIMARY_CID_INDEX 0 817 #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 818 #define BNX2X_MULTI_TX_COS_E2_E3A0 2 819 #define BNX2X_MULTI_TX_COS_E3B0 3 820 #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 821 822 823 struct bnx2x_queue_init_params { 824 struct { 825 unsigned long flags; 826 u16 hc_rate; 827 u8 fw_sb_id; 828 u8 sb_cq_index; 829 } tx; 830 831 struct { 832 unsigned long flags; 833 u16 hc_rate; 834 u8 fw_sb_id; 835 u8 sb_cq_index; 836 } rx; 837 838 /* CID context in the host memory */ 839 struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 840 841 /* maximum number of cos supported by hardware */ 842 u8 max_cos; 843 }; 844 845 struct bnx2x_queue_terminate_params { 846 /* index within the tx_only cids of this queue object */ 847 u8 cid_index; 848 }; 849 850 struct bnx2x_queue_cfc_del_params { 851 /* index within the tx_only cids of this queue object */ 852 u8 cid_index; 853 }; 854 855 struct bnx2x_queue_update_params { 856 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 857 u16 def_vlan; 858 u16 silent_removal_value; 859 u16 silent_removal_mask; 860 /* index within the tx_only cids of this queue object */ 861 u8 cid_index; 862 }; 863 864 struct rxq_pause_params { 865 u16 bd_th_lo; 866 u16 bd_th_hi; 867 u16 rcq_th_lo; 868 u16 rcq_th_hi; 869 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 870 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 871 u16 pri_map; 872 }; 873 874 /* general */ 875 struct bnx2x_general_setup_params { 876 /* valid iff BNX2X_Q_FLG_STATS */ 877 u8 stat_id; 878 879 u8 spcl_id; 880 u16 mtu; 881 u8 cos; 882 }; 883 884 struct bnx2x_rxq_setup_params { 885 /* dma */ 886 dma_addr_t dscr_map; 887 dma_addr_t sge_map; 888 dma_addr_t rcq_map; 889 dma_addr_t rcq_np_map; 890 891 u16 drop_flags; 892 u16 buf_sz; 893 u8 fw_sb_id; 894 u8 cl_qzone_id; 895 896 /* valid iff BNX2X_Q_FLG_TPA */ 897 u16 tpa_agg_sz; 898 u16 sge_buf_sz; 899 u8 max_sges_pkt; 900 u8 max_tpa_queues; 901 u8 rss_engine_id; 902 903 /* valid iff BNX2X_Q_FLG_MCAST */ 904 u8 mcast_engine_id; 905 906 u8 cache_line_log; 907 908 u8 sb_cq_index; 909 910 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 911 u16 silent_removal_value; 912 u16 silent_removal_mask; 913 }; 914 915 struct bnx2x_txq_setup_params { 916 /* dma */ 917 dma_addr_t dscr_map; 918 919 u8 fw_sb_id; 920 u8 sb_cq_index; 921 u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 922 u16 traffic_type; 923 /* equals to the leading rss client id, used for TX classification*/ 924 u8 tss_leading_cl_id; 925 926 /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 927 u16 default_vlan; 928 }; 929 930 struct bnx2x_queue_setup_params { 931 struct bnx2x_general_setup_params gen_params; 932 struct bnx2x_txq_setup_params txq_params; 933 struct bnx2x_rxq_setup_params rxq_params; 934 struct rxq_pause_params pause_params; 935 unsigned long flags; 936 }; 937 938 struct bnx2x_queue_setup_tx_only_params { 939 struct bnx2x_general_setup_params gen_params; 940 struct bnx2x_txq_setup_params txq_params; 941 unsigned long flags; 942 /* index within the tx_only cids of this queue object */ 943 u8 cid_index; 944 }; 945 946 struct bnx2x_queue_state_params { 947 struct bnx2x_queue_sp_obj *q_obj; 948 949 /* Current command */ 950 enum bnx2x_queue_cmd cmd; 951 952 /* may have RAMROD_COMP_WAIT set only */ 953 unsigned long ramrod_flags; 954 955 /* Params according to the current command */ 956 union { 957 struct bnx2x_queue_update_params update; 958 struct bnx2x_queue_setup_params setup; 959 struct bnx2x_queue_init_params init; 960 struct bnx2x_queue_setup_tx_only_params tx_only; 961 struct bnx2x_queue_terminate_params terminate; 962 struct bnx2x_queue_cfc_del_params cfc_del; 963 } params; 964 }; 965 966 struct bnx2x_queue_sp_obj { 967 u32 cids[BNX2X_MULTI_TX_COS]; 968 u8 cl_id; 969 u8 func_id; 970 971 /* 972 * number of traffic classes supported by queue. 973 * The primary connection of the queue suppotrs the first traffic 974 * class. Any further traffic class is suppoted by a tx-only 975 * connection. 976 * 977 * Therefore max_cos is also a number of valid entries in the cids 978 * array. 979 */ 980 u8 max_cos; 981 u8 num_tx_only, next_tx_only; 982 983 enum bnx2x_q_state state, next_state; 984 985 /* bits from enum bnx2x_q_type */ 986 unsigned long type; 987 988 /* BNX2X_Q_CMD_XX bits. This object implements "one 989 * pending" paradigm but for debug and tracing purposes it's 990 * more convinient to have different bits for different 991 * commands. 992 */ 993 unsigned long pending; 994 995 /* Buffer to use as a ramrod data and its mapping */ 996 void *rdata; 997 dma_addr_t rdata_mapping; 998 999 /** 1000 * Performs one state change according to the given parameters. 1001 * 1002 * @return 0 in case of success and negative value otherwise. 1003 */ 1004 int (*send_cmd)(struct bnx2x *bp, 1005 struct bnx2x_queue_state_params *params); 1006 1007 /** 1008 * Sets the pending bit according to the requested transition. 1009 */ 1010 int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1011 struct bnx2x_queue_state_params *params); 1012 1013 /** 1014 * Checks that the requested state transition is legal. 1015 */ 1016 int (*check_transition)(struct bnx2x *bp, 1017 struct bnx2x_queue_sp_obj *o, 1018 struct bnx2x_queue_state_params *params); 1019 1020 /** 1021 * Completes the pending command. 1022 */ 1023 int (*complete_cmd)(struct bnx2x *bp, 1024 struct bnx2x_queue_sp_obj *o, 1025 enum bnx2x_queue_cmd); 1026 1027 int (*wait_comp)(struct bnx2x *bp, 1028 struct bnx2x_queue_sp_obj *o, 1029 enum bnx2x_queue_cmd cmd); 1030 }; 1031 1032 /********************** Function state update *********************************/ 1033 /* Allowed Function states */ 1034 enum bnx2x_func_state { 1035 BNX2X_F_STATE_RESET, 1036 BNX2X_F_STATE_INITIALIZED, 1037 BNX2X_F_STATE_STARTED, 1038 BNX2X_F_STATE_TX_STOPPED, 1039 BNX2X_F_STATE_MAX, 1040 }; 1041 1042 /* Allowed Function commands */ 1043 enum bnx2x_func_cmd { 1044 BNX2X_F_CMD_HW_INIT, 1045 BNX2X_F_CMD_START, 1046 BNX2X_F_CMD_STOP, 1047 BNX2X_F_CMD_HW_RESET, 1048 BNX2X_F_CMD_TX_STOP, 1049 BNX2X_F_CMD_TX_START, 1050 BNX2X_F_CMD_MAX, 1051 }; 1052 1053 struct bnx2x_func_hw_init_params { 1054 /* A load phase returned by MCP. 1055 * 1056 * May be: 1057 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1058 * FW_MSG_CODE_DRV_LOAD_COMMON 1059 * FW_MSG_CODE_DRV_LOAD_PORT 1060 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1061 */ 1062 u32 load_phase; 1063 }; 1064 1065 struct bnx2x_func_hw_reset_params { 1066 /* A load phase returned by MCP. 1067 * 1068 * May be: 1069 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1070 * FW_MSG_CODE_DRV_LOAD_COMMON 1071 * FW_MSG_CODE_DRV_LOAD_PORT 1072 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1073 */ 1074 u32 reset_phase; 1075 }; 1076 1077 struct bnx2x_func_start_params { 1078 /* Multi Function mode: 1079 * - Single Function 1080 * - Switch Dependent 1081 * - Switch Independent 1082 */ 1083 u16 mf_mode; 1084 1085 /* Switch Dependent mode outer VLAN tag */ 1086 u16 sd_vlan_tag; 1087 1088 /* Function cos mode */ 1089 u8 network_cos_mode; 1090 }; 1091 1092 struct bnx2x_func_tx_start_params { 1093 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1094 u8 dcb_enabled; 1095 u8 dcb_version; 1096 u8 dont_add_pri_0_en; 1097 }; 1098 1099 struct bnx2x_func_state_params { 1100 struct bnx2x_func_sp_obj *f_obj; 1101 1102 /* Current command */ 1103 enum bnx2x_func_cmd cmd; 1104 1105 /* may have RAMROD_COMP_WAIT set only */ 1106 unsigned long ramrod_flags; 1107 1108 /* Params according to the current command */ 1109 union { 1110 struct bnx2x_func_hw_init_params hw_init; 1111 struct bnx2x_func_hw_reset_params hw_reset; 1112 struct bnx2x_func_start_params start; 1113 struct bnx2x_func_tx_start_params tx_start; 1114 } params; 1115 }; 1116 1117 struct bnx2x_func_sp_drv_ops { 1118 /* Init tool + runtime initialization: 1119 * - Common Chip 1120 * - Common (per Path) 1121 * - Port 1122 * - Function phases 1123 */ 1124 int (*init_hw_cmn_chip)(struct bnx2x *bp); 1125 int (*init_hw_cmn)(struct bnx2x *bp); 1126 int (*init_hw_port)(struct bnx2x *bp); 1127 int (*init_hw_func)(struct bnx2x *bp); 1128 1129 /* Reset Function HW: Common, Port, Function phases. */ 1130 void (*reset_hw_cmn)(struct bnx2x *bp); 1131 void (*reset_hw_port)(struct bnx2x *bp); 1132 void (*reset_hw_func)(struct bnx2x *bp); 1133 1134 /* Init/Free GUNZIP resources */ 1135 int (*gunzip_init)(struct bnx2x *bp); 1136 void (*gunzip_end)(struct bnx2x *bp); 1137 1138 /* Prepare/Release FW resources */ 1139 int (*init_fw)(struct bnx2x *bp); 1140 void (*release_fw)(struct bnx2x *bp); 1141 }; 1142 1143 struct bnx2x_func_sp_obj { 1144 enum bnx2x_func_state state, next_state; 1145 1146 /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1147 * pending" paradigm but for debug and tracing purposes it's 1148 * more convinient to have different bits for different 1149 * commands. 1150 */ 1151 unsigned long pending; 1152 1153 /* Buffer to use as a ramrod data and its mapping */ 1154 void *rdata; 1155 dma_addr_t rdata_mapping; 1156 1157 /* this mutex validates that when pending flag is taken, the next 1158 * ramrod to be sent will be the one set the pending bit 1159 */ 1160 struct mutex one_pending_mutex; 1161 1162 /* Driver interface */ 1163 struct bnx2x_func_sp_drv_ops *drv; 1164 1165 /** 1166 * Performs one state change according to the given parameters. 1167 * 1168 * @return 0 in case of success and negative value otherwise. 1169 */ 1170 int (*send_cmd)(struct bnx2x *bp, 1171 struct bnx2x_func_state_params *params); 1172 1173 /** 1174 * Checks that the requested state transition is legal. 1175 */ 1176 int (*check_transition)(struct bnx2x *bp, 1177 struct bnx2x_func_sp_obj *o, 1178 struct bnx2x_func_state_params *params); 1179 1180 /** 1181 * Completes the pending command. 1182 */ 1183 int (*complete_cmd)(struct bnx2x *bp, 1184 struct bnx2x_func_sp_obj *o, 1185 enum bnx2x_func_cmd cmd); 1186 1187 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1188 enum bnx2x_func_cmd cmd); 1189 }; 1190 1191 /********************** Interfaces ********************************************/ 1192 /* Queueable objects set */ 1193 union bnx2x_qable_obj { 1194 struct bnx2x_vlan_mac_obj vlan_mac; 1195 }; 1196 /************** Function state update *********/ 1197 void bnx2x_init_func_obj(struct bnx2x *bp, 1198 struct bnx2x_func_sp_obj *obj, 1199 void *rdata, dma_addr_t rdata_mapping, 1200 struct bnx2x_func_sp_drv_ops *drv_iface); 1201 1202 int bnx2x_func_state_change(struct bnx2x *bp, 1203 struct bnx2x_func_state_params *params); 1204 1205 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1206 struct bnx2x_func_sp_obj *o); 1207 /******************* Queue State **************/ 1208 void bnx2x_init_queue_obj(struct bnx2x *bp, 1209 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1210 u8 cid_cnt, u8 func_id, void *rdata, 1211 dma_addr_t rdata_mapping, unsigned long type); 1212 1213 int bnx2x_queue_state_change(struct bnx2x *bp, 1214 struct bnx2x_queue_state_params *params); 1215 1216 /********************* VLAN-MAC ****************/ 1217 void bnx2x_init_mac_obj(struct bnx2x *bp, 1218 struct bnx2x_vlan_mac_obj *mac_obj, 1219 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1220 dma_addr_t rdata_mapping, int state, 1221 unsigned long *pstate, bnx2x_obj_type type, 1222 struct bnx2x_credit_pool_obj *macs_pool); 1223 1224 void bnx2x_init_vlan_obj(struct bnx2x *bp, 1225 struct bnx2x_vlan_mac_obj *vlan_obj, 1226 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1227 dma_addr_t rdata_mapping, int state, 1228 unsigned long *pstate, bnx2x_obj_type type, 1229 struct bnx2x_credit_pool_obj *vlans_pool); 1230 1231 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1232 struct bnx2x_vlan_mac_obj *vlan_mac_obj, 1233 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1234 dma_addr_t rdata_mapping, int state, 1235 unsigned long *pstate, bnx2x_obj_type type, 1236 struct bnx2x_credit_pool_obj *macs_pool, 1237 struct bnx2x_credit_pool_obj *vlans_pool); 1238 1239 int bnx2x_config_vlan_mac(struct bnx2x *bp, 1240 struct bnx2x_vlan_mac_ramrod_params *p); 1241 1242 int bnx2x_vlan_mac_move(struct bnx2x *bp, 1243 struct bnx2x_vlan_mac_ramrod_params *p, 1244 struct bnx2x_vlan_mac_obj *dest_o); 1245 1246 /********************* RX MODE ****************/ 1247 1248 void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1249 struct bnx2x_rx_mode_obj *o); 1250 1251 /** 1252 * Send and RX_MODE ramrod according to the provided parameters. 1253 * 1254 * @param bp 1255 * @param p Command parameters 1256 * 1257 * @return 0 - if operation was successfull and there is no pending completions, 1258 * positive number - if there are pending completions, 1259 * negative - if there were errors 1260 */ 1261 int bnx2x_config_rx_mode(struct bnx2x *bp, 1262 struct bnx2x_rx_mode_ramrod_params *p); 1263 1264 /****************** MULTICASTS ****************/ 1265 1266 void bnx2x_init_mcast_obj(struct bnx2x *bp, 1267 struct bnx2x_mcast_obj *mcast_obj, 1268 u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1269 u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1270 int state, unsigned long *pstate, 1271 bnx2x_obj_type type); 1272 1273 /** 1274 * Configure multicast MACs list. May configure a new list 1275 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1276 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1277 * configuration, continue to execute the pending commands 1278 * (BNX2X_MCAST_CMD_CONT). 1279 * 1280 * If previous command is still pending or if number of MACs to 1281 * configure is more that maximum number of MACs in one command, 1282 * the current command will be enqueued to the tail of the 1283 * pending commands list. 1284 * 1285 * @param bp 1286 * @param p 1287 * @param command to execute: BNX2X_MCAST_CMD_X 1288 * 1289 * @return 0 is operation was sucessfull and there are no pending completions, 1290 * negative if there were errors, positive if there are pending 1291 * completions. 1292 */ 1293 int bnx2x_config_mcast(struct bnx2x *bp, 1294 struct bnx2x_mcast_ramrod_params *p, int cmd); 1295 1296 /****************** CREDIT POOL ****************/ 1297 void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1298 struct bnx2x_credit_pool_obj *p, u8 func_id, 1299 u8 func_num); 1300 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1301 struct bnx2x_credit_pool_obj *p, u8 func_id, 1302 u8 func_num); 1303 1304 1305 /****************** RSS CONFIGURATION ****************/ 1306 void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1307 struct bnx2x_rss_config_obj *rss_obj, 1308 u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1309 void *rdata, dma_addr_t rdata_mapping, 1310 int state, unsigned long *pstate, 1311 bnx2x_obj_type type); 1312 1313 /** 1314 * Updates RSS configuration according to provided parameters. 1315 * 1316 * @param bp 1317 * @param p 1318 * 1319 * @return 0 in case of success 1320 */ 1321 int bnx2x_config_rss(struct bnx2x *bp, 1322 struct bnx2x_config_rss_params *p); 1323 1324 /** 1325 * Return the current ind_table configuration. 1326 * 1327 * @param bp 1328 * @param ind_table buffer to fill with the current indirection 1329 * table content. Should be at least 1330 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1331 */ 1332 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1333 u8 *ind_table); 1334 1335 #endif /* BNX2X_SP_VERBS */ 1336