1 /*
2  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3  *                VA Linux Systems Inc., Fremont, California.
4  * Copyright 2008 Red Hat Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Original Authors:
25  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26  *
27  * Kernel port Author: Dave Airlie
28  */
29 
30 #ifndef RADEON_MODE_H
31 #define RADEON_MODE_H
32 
33 #include <drm/display/drm_dp_helper.h>
34 #include <drm/display/drm_dp_mst_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_encoder.h>
38 #include <drm/drm_fixed.h>
39 #include <drm/drm_crtc_helper.h>
40 #include <linux/i2c.h>
41 #include <linux/i2c-algo-bit.h>
42 
43 struct radeon_bo;
44 struct radeon_device;
45 
46 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
47 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
48 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
49 
50 #define RADEON_MAX_HPD_PINS 7
51 #define RADEON_MAX_CRTCS 6
52 #define RADEON_MAX_AFMT_BLOCKS 7
53 
54 enum radeon_rmx_type {
55 	RMX_OFF,
56 	RMX_FULL,
57 	RMX_CENTER,
58 	RMX_ASPECT
59 };
60 
61 enum radeon_tv_std {
62 	TV_STD_NTSC,
63 	TV_STD_PAL,
64 	TV_STD_PAL_M,
65 	TV_STD_PAL_60,
66 	TV_STD_NTSC_J,
67 	TV_STD_SCART_PAL,
68 	TV_STD_SECAM,
69 	TV_STD_PAL_CN,
70 	TV_STD_PAL_N,
71 };
72 
73 enum radeon_underscan_type {
74 	UNDERSCAN_OFF,
75 	UNDERSCAN_ON,
76 	UNDERSCAN_AUTO,
77 };
78 
79 enum radeon_hpd_id {
80 	RADEON_HPD_1 = 0,
81 	RADEON_HPD_2,
82 	RADEON_HPD_3,
83 	RADEON_HPD_4,
84 	RADEON_HPD_5,
85 	RADEON_HPD_6,
86 	RADEON_HPD_NONE = 0xff,
87 };
88 
89 enum radeon_output_csc {
90 	RADEON_OUTPUT_CSC_BYPASS = 0,
91 	RADEON_OUTPUT_CSC_TVRGB = 1,
92 	RADEON_OUTPUT_CSC_YCBCR601 = 2,
93 	RADEON_OUTPUT_CSC_YCBCR709 = 3,
94 };
95 
96 #define RADEON_MAX_I2C_BUS 16
97 
98 /* radeon gpio-based i2c
99  * 1. "mask" reg and bits
100  *    grabs the gpio pins for software use
101  *    0=not held  1=held
102  * 2. "a" reg and bits
103  *    output pin value
104  *    0=low 1=high
105  * 3. "en" reg and bits
106  *    sets the pin direction
107  *    0=input 1=output
108  * 4. "y" reg and bits
109  *    input pin value
110  *    0=low 1=high
111  */
112 struct radeon_i2c_bus_rec {
113 	bool valid;
114 	/* id used by atom */
115 	uint8_t i2c_id;
116 	/* id used by atom */
117 	enum radeon_hpd_id hpd;
118 	/* can be used with hw i2c engine */
119 	bool hw_capable;
120 	/* uses multi-media i2c engine */
121 	bool mm_i2c;
122 	/* regs and bits */
123 	uint32_t mask_clk_reg;
124 	uint32_t mask_data_reg;
125 	uint32_t a_clk_reg;
126 	uint32_t a_data_reg;
127 	uint32_t en_clk_reg;
128 	uint32_t en_data_reg;
129 	uint32_t y_clk_reg;
130 	uint32_t y_data_reg;
131 	uint32_t mask_clk_mask;
132 	uint32_t mask_data_mask;
133 	uint32_t a_clk_mask;
134 	uint32_t a_data_mask;
135 	uint32_t en_clk_mask;
136 	uint32_t en_data_mask;
137 	uint32_t y_clk_mask;
138 	uint32_t y_data_mask;
139 };
140 
141 struct radeon_tmds_pll {
142     uint32_t freq;
143     uint32_t value;
144 };
145 
146 #define RADEON_MAX_BIOS_CONNECTOR 16
147 
148 /* pll flags */
149 #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
150 #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
151 #define RADEON_PLL_USE_REF_DIV          (1 << 2)
152 #define RADEON_PLL_LEGACY               (1 << 3)
153 #define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
154 #define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
155 #define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
156 #define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
157 #define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
158 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
159 #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
160 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
161 #define RADEON_PLL_USE_POST_DIV         (1 << 12)
162 #define RADEON_PLL_IS_LCD               (1 << 13)
163 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
164 
165 struct radeon_pll {
166 	/* reference frequency */
167 	uint32_t reference_freq;
168 
169 	/* fixed dividers */
170 	uint32_t reference_div;
171 	uint32_t post_div;
172 
173 	/* pll in/out limits */
174 	uint32_t pll_in_min;
175 	uint32_t pll_in_max;
176 	uint32_t pll_out_min;
177 	uint32_t pll_out_max;
178 	uint32_t lcd_pll_out_min;
179 	uint32_t lcd_pll_out_max;
180 	uint32_t best_vco;
181 
182 	/* divider limits */
183 	uint32_t min_ref_div;
184 	uint32_t max_ref_div;
185 	uint32_t min_post_div;
186 	uint32_t max_post_div;
187 	uint32_t min_feedback_div;
188 	uint32_t max_feedback_div;
189 	uint32_t min_frac_feedback_div;
190 	uint32_t max_frac_feedback_div;
191 
192 	/* flags for the current clock */
193 	uint32_t flags;
194 
195 	/* pll id */
196 	uint32_t id;
197 };
198 
199 struct radeon_i2c_chan {
200 	struct i2c_adapter adapter;
201 	struct drm_device *dev;
202 	struct i2c_algo_bit_data bit;
203 	struct radeon_i2c_bus_rec rec;
204 	struct drm_dp_aux aux;
205 	bool has_aux;
206 	struct mutex mutex;
207 };
208 
209 /* mostly for macs, but really any system without connector tables */
210 enum radeon_connector_table {
211 	CT_NONE = 0,
212 	CT_GENERIC,
213 	CT_IBOOK,
214 	CT_POWERBOOK_EXTERNAL,
215 	CT_POWERBOOK_INTERNAL,
216 	CT_POWERBOOK_VGA,
217 	CT_MINI_EXTERNAL,
218 	CT_MINI_INTERNAL,
219 	CT_IMAC_G5_ISIGHT,
220 	CT_EMAC,
221 	CT_RN50_POWER,
222 	CT_MAC_X800,
223 	CT_MAC_G5_9600,
224 	CT_SAM440EP,
225 	CT_MAC_G4_SILVER
226 };
227 
228 enum radeon_dvo_chip {
229 	DVO_SIL164,
230 	DVO_SIL1178,
231 };
232 
233 struct radeon_fbdev;
234 
235 struct radeon_afmt {
236 	bool enabled;
237 	int offset;
238 	bool last_buffer_filled_status;
239 	int id;
240 };
241 
242 struct radeon_mode_info {
243 	struct atom_context *atom_context;
244 	struct card_info *atom_card_info;
245 	enum radeon_connector_table connector_table;
246 	bool mode_config_initialized;
247 	struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
248 	struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
249 	/* DVI-I properties */
250 	struct drm_property *coherent_mode_property;
251 	/* DAC enable load detect */
252 	struct drm_property *load_detect_property;
253 	/* TV standard */
254 	struct drm_property *tv_std_property;
255 	/* legacy TMDS PLL detect */
256 	struct drm_property *tmds_pll_property;
257 	/* underscan */
258 	struct drm_property *underscan_property;
259 	struct drm_property *underscan_hborder_property;
260 	struct drm_property *underscan_vborder_property;
261 	/* audio */
262 	struct drm_property *audio_property;
263 	/* FMT dithering */
264 	struct drm_property *dither_property;
265 	/* Output CSC */
266 	struct drm_property *output_csc_property;
267 	/* hardcoded DFP edid from BIOS */
268 	struct edid *bios_hardcoded_edid;
269 	int bios_hardcoded_edid_size;
270 
271 	/* pointer to fbdev info structure */
272 	struct radeon_fbdev *rfbdev;
273 	/* firmware flags */
274 	u16 firmware_flags;
275 	/* pointer to backlight encoder */
276 	struct radeon_encoder *bl_encoder;
277 
278 	/* bitmask for active encoder frontends */
279 	uint32_t active_encoders;
280 };
281 
282 #define RADEON_MAX_BL_LEVEL 0xFF
283 
284 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
285 
286 struct radeon_backlight_privdata {
287 	struct radeon_encoder *encoder;
288 	uint8_t negative;
289 };
290 
291 #endif
292 
293 #define MAX_H_CODE_TIMING_LEN 32
294 #define MAX_V_CODE_TIMING_LEN 32
295 
296 /* need to store these as reading
297    back code tables is excessive */
298 struct radeon_tv_regs {
299 	uint32_t tv_uv_adr;
300 	uint32_t timing_cntl;
301 	uint32_t hrestart;
302 	uint32_t vrestart;
303 	uint32_t frestart;
304 	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
305 	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
306 };
307 
308 struct radeon_atom_ss {
309 	uint16_t percentage;
310 	uint16_t percentage_divider;
311 	uint8_t type;
312 	uint16_t step;
313 	uint8_t delay;
314 	uint8_t range;
315 	uint8_t refdiv;
316 	/* asic_ss */
317 	uint16_t rate;
318 	uint16_t amount;
319 };
320 
321 enum radeon_flip_status {
322 	RADEON_FLIP_NONE,
323 	RADEON_FLIP_PENDING,
324 	RADEON_FLIP_SUBMITTED
325 };
326 
327 struct radeon_crtc {
328 	struct drm_crtc base;
329 	int crtc_id;
330 	bool enabled;
331 	bool can_tile;
332 	bool cursor_out_of_bounds;
333 	uint32_t crtc_offset;
334 	struct drm_gem_object *cursor_bo;
335 	uint64_t cursor_addr;
336 	int cursor_x;
337 	int cursor_y;
338 	int cursor_hot_x;
339 	int cursor_hot_y;
340 	int cursor_width;
341 	int cursor_height;
342 	int max_cursor_width;
343 	int max_cursor_height;
344 	uint32_t legacy_display_base_addr;
345 	enum radeon_rmx_type rmx_type;
346 	u8 h_border;
347 	u8 v_border;
348 	fixed20_12 vsc;
349 	fixed20_12 hsc;
350 	struct drm_display_mode native_mode;
351 	int pll_id;
352 	/* page flipping */
353 	struct workqueue_struct *flip_queue;
354 	struct radeon_flip_work *flip_work;
355 	enum radeon_flip_status flip_status;
356 	/* pll sharing */
357 	struct radeon_atom_ss ss;
358 	bool ss_enabled;
359 	u32 adjusted_clock;
360 	int bpc;
361 	u32 pll_reference_div;
362 	u32 pll_post_div;
363 	u32 pll_flags;
364 	struct drm_encoder *encoder;
365 	struct drm_connector *connector;
366 	/* for dpm */
367 	u32 line_time;
368 	u32 wm_low;
369 	u32 wm_high;
370 	u32 lb_vblank_lead_lines;
371 	struct drm_display_mode hw_mode;
372 	enum radeon_output_csc output_csc;
373 };
374 
375 struct radeon_encoder_primary_dac {
376 	/* legacy primary dac */
377 	uint32_t ps2_pdac_adj;
378 };
379 
380 struct radeon_encoder_lvds {
381 	/* legacy lvds */
382 	uint16_t panel_vcc_delay;
383 	uint8_t  panel_pwr_delay;
384 	uint8_t  panel_digon_delay;
385 	uint8_t  panel_blon_delay;
386 	uint16_t panel_ref_divider;
387 	uint8_t  panel_post_divider;
388 	uint16_t panel_fb_divider;
389 	bool     use_bios_dividers;
390 	uint32_t lvds_gen_cntl;
391 	/* panel mode */
392 	struct drm_display_mode native_mode;
393 	struct backlight_device *bl_dev;
394 	int      dpms_mode;
395 	uint8_t  backlight_level;
396 };
397 
398 struct radeon_encoder_tv_dac {
399 	/* legacy tv dac */
400 	uint32_t ps2_tvdac_adj;
401 	uint32_t ntsc_tvdac_adj;
402 	uint32_t pal_tvdac_adj;
403 
404 	int               h_pos;
405 	int               v_pos;
406 	int               h_size;
407 	int               supported_tv_stds;
408 	bool              tv_on;
409 	enum radeon_tv_std tv_std;
410 	struct radeon_tv_regs tv;
411 };
412 
413 struct radeon_encoder_int_tmds {
414 	/* legacy int tmds */
415 	struct radeon_tmds_pll tmds_pll[4];
416 };
417 
418 struct radeon_encoder_ext_tmds {
419 	/* tmds over dvo */
420 	struct radeon_i2c_chan *i2c_bus;
421 	uint8_t slave_addr;
422 	enum radeon_dvo_chip dvo_chip;
423 };
424 
425 /* spread spectrum */
426 struct radeon_encoder_atom_dig {
427 	bool linkb;
428 	/* atom dig */
429 	bool coherent_mode;
430 	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
431 	/* atom lvds/edp */
432 	uint32_t lcd_misc;
433 	uint16_t panel_pwr_delay;
434 	uint32_t lcd_ss_id;
435 	/* panel mode */
436 	struct drm_display_mode native_mode;
437 	struct backlight_device *bl_dev;
438 	int dpms_mode;
439 	uint8_t backlight_level;
440 	int panel_mode;
441 	struct radeon_afmt *afmt;
442 	struct r600_audio_pin *pin;
443 	int active_mst_links;
444 };
445 
446 struct radeon_encoder_atom_dac {
447 	enum radeon_tv_std tv_std;
448 };
449 
450 struct radeon_encoder_mst {
451 	int crtc;
452 	struct radeon_encoder *primary;
453 	struct radeon_connector *connector;
454 	struct drm_dp_mst_port *port;
455 	int pbn;
456 	int fe;
457 	bool fe_from_be;
458 	bool enc_active;
459 };
460 
461 struct radeon_encoder {
462 	struct drm_encoder base;
463 	uint32_t encoder_enum;
464 	uint32_t encoder_id;
465 	uint32_t devices;
466 	uint32_t active_device;
467 	uint32_t flags;
468 	uint32_t pixel_clock;
469 	enum radeon_rmx_type rmx_type;
470 	enum radeon_underscan_type underscan_type;
471 	uint32_t underscan_hborder;
472 	uint32_t underscan_vborder;
473 	struct drm_display_mode native_mode;
474 	void *enc_priv;
475 	int audio_polling_active;
476 	bool is_ext_encoder;
477 	u16 caps;
478 	struct radeon_audio_funcs *audio;
479 	enum radeon_output_csc output_csc;
480 	bool can_mst;
481 	uint32_t offset;
482 	bool is_mst_encoder;
483 	/* front end for this mst encoder */
484 };
485 
486 struct radeon_connector_atom_dig {
487 	uint32_t igp_lane_info;
488 	/* displayport */
489 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
490 	u8 dp_sink_type;
491 	int dp_clock;
492 	int dp_lane_count;
493 	bool edp_on;
494 	bool is_mst;
495 };
496 
497 struct radeon_gpio_rec {
498 	bool valid;
499 	u8 id;
500 	u32 reg;
501 	u32 mask;
502 	u32 shift;
503 };
504 
505 struct radeon_hpd {
506 	enum radeon_hpd_id hpd;
507 	u8 plugged_state;
508 	struct radeon_gpio_rec gpio;
509 };
510 
511 struct radeon_router {
512 	u32 router_id;
513 	struct radeon_i2c_bus_rec i2c_info;
514 	u8 i2c_addr;
515 	/* i2c mux */
516 	bool ddc_valid;
517 	u8 ddc_mux_type;
518 	u8 ddc_mux_control_pin;
519 	u8 ddc_mux_state;
520 	/* clock/data mux */
521 	bool cd_valid;
522 	u8 cd_mux_type;
523 	u8 cd_mux_control_pin;
524 	u8 cd_mux_state;
525 };
526 
527 enum radeon_connector_audio {
528 	RADEON_AUDIO_DISABLE = 0,
529 	RADEON_AUDIO_ENABLE = 1,
530 	RADEON_AUDIO_AUTO = 2
531 };
532 
533 enum radeon_connector_dither {
534 	RADEON_FMT_DITHER_DISABLE = 0,
535 	RADEON_FMT_DITHER_ENABLE = 1,
536 };
537 
538 struct stream_attribs {
539 	uint16_t fe;
540 	uint16_t slots;
541 };
542 
543 struct radeon_connector {
544 	struct drm_connector base;
545 	uint32_t connector_id;
546 	uint32_t devices;
547 	struct radeon_i2c_chan *ddc_bus;
548 	/* some systems have an hdmi and vga port with a shared ddc line */
549 	bool shared_ddc;
550 	bool use_digital;
551 	/* we need to mind the EDID between detect
552 	   and get modes due to analog/digital/tvencoder */
553 	struct edid *edid;
554 	void *con_priv;
555 	bool dac_load_detect;
556 	bool detected_by_load; /* if the connection status was determined by load */
557 	bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
558 	uint16_t connector_object_id;
559 	struct radeon_hpd hpd;
560 	struct radeon_router router;
561 	struct radeon_i2c_chan *router_bus;
562 	enum radeon_connector_audio audio;
563 	enum radeon_connector_dither dither;
564 	int pixelclock_for_modeset;
565 	bool is_mst_connector;
566 	struct radeon_connector *mst_port;
567 	struct drm_dp_mst_port *port;
568 	struct drm_dp_mst_topology_mgr mst_mgr;
569 
570 	struct radeon_encoder *mst_encoder;
571 	struct stream_attribs cur_stream_attribs[6];
572 	int enabled_attribs;
573 };
574 
575 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
576 				((em) == ATOM_ENCODER_MODE_DP_MST))
577 
578 struct atom_clock_dividers {
579 	u32 post_div;
580 	union {
581 		struct {
582 #ifdef __BIG_ENDIAN
583 			u32 reserved : 6;
584 			u32 whole_fb_div : 12;
585 			u32 frac_fb_div : 14;
586 #else
587 			u32 frac_fb_div : 14;
588 			u32 whole_fb_div : 12;
589 			u32 reserved : 6;
590 #endif
591 		};
592 		u32 fb_div;
593 	};
594 	u32 ref_div;
595 	bool enable_post_div;
596 	bool enable_dithen;
597 	u32 vco_mode;
598 	u32 real_clock;
599 	/* added for CI */
600 	u32 post_divider;
601 	u32 flags;
602 };
603 
604 struct atom_mpll_param {
605 	union {
606 		struct {
607 #ifdef __BIG_ENDIAN
608 			u32 reserved : 8;
609 			u32 clkfrac : 12;
610 			u32 clkf : 12;
611 #else
612 			u32 clkf : 12;
613 			u32 clkfrac : 12;
614 			u32 reserved : 8;
615 #endif
616 		};
617 		u32 fb_div;
618 	};
619 	u32 post_div;
620 	u32 bwcntl;
621 	u32 dll_speed;
622 	u32 vco_mode;
623 	u32 yclk_sel;
624 	u32 qdr;
625 	u32 half_rate;
626 };
627 
628 #define MEM_TYPE_GDDR5  0x50
629 #define MEM_TYPE_GDDR4  0x40
630 #define MEM_TYPE_GDDR3  0x30
631 #define MEM_TYPE_DDR2   0x20
632 #define MEM_TYPE_GDDR1  0x10
633 #define MEM_TYPE_DDR3   0xb0
634 #define MEM_TYPE_MASK   0xf0
635 
636 struct atom_memory_info {
637 	u8 mem_vendor;
638 	u8 mem_type;
639 };
640 
641 #define MAX_AC_TIMING_ENTRIES 16
642 
643 struct atom_memory_clock_range_table
644 {
645 	u8 num_entries;
646 	u8 rsv[3];
647 	u32 mclk[MAX_AC_TIMING_ENTRIES];
648 };
649 
650 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
651 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
652 
653 struct atom_mc_reg_entry {
654 	u32 mclk_max;
655 	u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
656 };
657 
658 struct atom_mc_register_address {
659 	u16 s1;
660 	u8 pre_reg_data;
661 };
662 
663 struct atom_mc_reg_table {
664 	u8 last;
665 	u8 num_entries;
666 	struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
667 	struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
668 };
669 
670 #define MAX_VOLTAGE_ENTRIES 32
671 
672 struct atom_voltage_table_entry
673 {
674 	u16 value;
675 	u32 smio_low;
676 };
677 
678 struct atom_voltage_table
679 {
680 	u32 count;
681 	u32 mask_low;
682 	u32 phase_delay;
683 	struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
684 };
685 
686 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
687 #define DRM_SCANOUTPOS_VALID        (1 << 0)
688 #define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
689 #define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
690 #define USE_REAL_VBLANKSTART 		(1 << 30)
691 #define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)
692 
693 extern void
694 radeon_add_atom_connector(struct drm_device *dev,
695 			  uint32_t connector_id,
696 			  uint32_t supported_device,
697 			  int connector_type,
698 			  struct radeon_i2c_bus_rec *i2c_bus,
699 			  uint32_t igp_lane_info,
700 			  uint16_t connector_object_id,
701 			  struct radeon_hpd *hpd,
702 			  struct radeon_router *router);
703 extern void
704 radeon_add_legacy_connector(struct drm_device *dev,
705 			    uint32_t connector_id,
706 			    uint32_t supported_device,
707 			    int connector_type,
708 			    struct radeon_i2c_bus_rec *i2c_bus,
709 			    uint16_t connector_object_id,
710 			    struct radeon_hpd *hpd);
711 extern uint32_t
712 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
713 			uint8_t dac);
714 extern void radeon_link_encoder_connector(struct drm_device *dev);
715 
716 extern enum radeon_tv_std
717 radeon_combios_get_tv_info(struct radeon_device *rdev);
718 extern enum radeon_tv_std
719 radeon_atombios_get_tv_info(struct radeon_device *rdev);
720 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
721 						 u16 *vddc, u16 *vddci, u16 *mvdd);
722 
723 extern void
724 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
725 				      struct drm_encoder *encoder,
726 				      bool connected);
727 extern void
728 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
729 				       struct drm_encoder *encoder,
730 				       bool connected);
731 
732 extern struct drm_connector *
733 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
734 extern struct drm_connector *
735 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
736 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
737 				    u32 pixel_clock);
738 
739 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
740 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
741 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
742 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
743 
744 extern struct edid *radeon_connector_edid(struct drm_connector *connector);
745 
746 extern void radeon_connector_hotplug(struct drm_connector *connector);
747 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
748 				       struct drm_display_mode *mode);
749 extern void radeon_dp_set_link_config(struct drm_connector *connector,
750 				      const struct drm_display_mode *mode);
751 extern void radeon_dp_link_train(struct drm_encoder *encoder,
752 				 struct drm_connector *connector);
753 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
754 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
755 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
756 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
757 				    struct drm_connector *connector);
758 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
759 					 u8 power_state);
760 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
761 extern ssize_t
762 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
763 
764 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
765 extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
766 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
767 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
768 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
769 					   int action, uint8_t lane_num,
770 					   uint8_t lane_set);
771 extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
772 					    int action, uint8_t lane_num,
773 					    uint8_t lane_set, int fe);
774 extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder,
775 						 int fe);
776 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
777 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
778 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
779 
780 extern void radeon_i2c_init(struct radeon_device *rdev);
781 extern void radeon_i2c_fini(struct radeon_device *rdev);
782 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
783 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
784 extern void radeon_i2c_add(struct radeon_device *rdev,
785 			   struct radeon_i2c_bus_rec *rec,
786 			   const char *name);
787 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
788 						 struct radeon_i2c_bus_rec *i2c_bus);
789 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
790 						 struct radeon_i2c_bus_rec *rec,
791 						 const char *name);
792 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
793 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
794 				u8 slave_addr,
795 				u8 addr,
796 				u8 *val);
797 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
798 				u8 slave_addr,
799 				u8 addr,
800 				u8 val);
801 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
802 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
803 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
804 
805 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
806 					     struct radeon_atom_ss *ss,
807 					     int id);
808 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
809 					     struct radeon_atom_ss *ss,
810 					     int id, u32 clock);
811 extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
812 							  u8 id);
813 
814 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
815 				      uint64_t freq,
816 				      uint32_t *dot_clock_p,
817 				      uint32_t *fb_div_p,
818 				      uint32_t *frac_fb_div_p,
819 				      uint32_t *ref_div_p,
820 				      uint32_t *post_div_p);
821 
822 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
823 				     u32 freq,
824 				     u32 *dot_clock_p,
825 				     u32 *fb_div_p,
826 				     u32 *frac_fb_div_p,
827 				     u32 *ref_div_p,
828 				     u32 *post_div_p);
829 
830 extern void radeon_setup_encoder_clones(struct drm_device *dev);
831 
832 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
833 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
834 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
835 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
836 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
837 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
838 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
839 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
840 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
841 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
842 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
843 
844 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
845 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
846 				   struct drm_framebuffer *old_fb);
847 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
848 					 struct drm_framebuffer *fb,
849 					 int x, int y,
850 					 enum mode_set_atomic state);
851 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
852 				   struct drm_display_mode *mode,
853 				   struct drm_display_mode *adjusted_mode,
854 				   int x, int y,
855 				   struct drm_framebuffer *old_fb);
856 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
857 
858 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
859 				 struct drm_framebuffer *old_fb);
860 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
861 				       struct drm_framebuffer *fb,
862 				       int x, int y,
863 				       enum mode_set_atomic state);
864 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
865 				   struct drm_framebuffer *fb,
866 				   int x, int y, int atomic);
867 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
868 				   struct drm_file *file_priv,
869 				   uint32_t handle,
870 				   uint32_t width,
871 				   uint32_t height,
872 				   int32_t hot_x,
873 				   int32_t hot_y);
874 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
875 				   int x, int y);
876 extern void radeon_cursor_reset(struct drm_crtc *crtc);
877 
878 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
879 				      unsigned int flags, int *vpos, int *hpos,
880 				      ktime_t *stime, ktime_t *etime,
881 				      const struct drm_display_mode *mode);
882 
883 extern bool
884 radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq,
885 				 int *vpos, int *hpos,
886 				 ktime_t *stime, ktime_t *etime,
887 				 const struct drm_display_mode *mode);
888 
889 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
890 extern struct edid *
891 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
892 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
893 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
894 extern struct radeon_encoder_atom_dig *
895 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
896 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
897 					  struct radeon_encoder_int_tmds *tmds);
898 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
899 						     struct radeon_encoder_int_tmds *tmds);
900 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
901 						   struct radeon_encoder_int_tmds *tmds);
902 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
903 							 struct radeon_encoder_ext_tmds *tmds);
904 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
905 						       struct radeon_encoder_ext_tmds *tmds);
906 extern struct radeon_encoder_primary_dac *
907 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
908 extern struct radeon_encoder_tv_dac *
909 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
910 extern struct radeon_encoder_lvds *
911 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
912 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
913 extern struct radeon_encoder_tv_dac *
914 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
915 extern struct radeon_encoder_primary_dac *
916 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
917 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
918 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
919 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
920 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
921 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
922 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
923 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
924 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
925 extern void
926 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
927 extern void
928 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
929 extern void
930 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
931 extern void
932 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
933 int radeon_framebuffer_init(struct drm_device *dev,
934 			     struct drm_framebuffer *rfb,
935 			     const struct drm_mode_fb_cmd2 *mode_cmd,
936 			     struct drm_gem_object *obj);
937 
938 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
939 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
940 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
941 void radeon_atombios_init_crtc(struct drm_device *dev,
942 			       struct radeon_crtc *radeon_crtc);
943 void radeon_legacy_init_crtc(struct drm_device *dev,
944 			     struct radeon_crtc *radeon_crtc);
945 
946 void radeon_get_clock_info(struct drm_device *dev);
947 
948 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
949 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
950 
951 void radeon_enc_destroy(struct drm_encoder *encoder);
952 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
953 void radeon_combios_asic_init(struct drm_device *dev);
954 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
955 					const struct drm_display_mode *mode,
956 					struct drm_display_mode *adjusted_mode);
957 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
958 			     struct drm_display_mode *adjusted_mode);
959 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
960 
961 /* legacy tv */
962 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
963 				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
964 				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
965 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
966 				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
967 				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
968 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
969 				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
970 				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
971 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
972 			       struct drm_display_mode *mode,
973 			       struct drm_display_mode *adjusted_mode);
974 
975 /* fmt blocks */
976 void avivo_program_fmt(struct drm_encoder *encoder);
977 void dce3_program_fmt(struct drm_encoder *encoder);
978 void dce4_program_fmt(struct drm_encoder *encoder);
979 void dce8_program_fmt(struct drm_encoder *encoder);
980 
981 /* fbdev layer */
982 int radeon_fbdev_init(struct radeon_device *rdev);
983 void radeon_fbdev_fini(struct radeon_device *rdev);
984 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
985 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
986 
987 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
988 
989 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
990 
991 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
992 
993 /* mst */
994 int radeon_dp_mst_init(struct radeon_connector *radeon_connector);
995 int radeon_dp_mst_probe(struct radeon_connector *radeon_connector);
996 int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector);
997 void radeon_mst_debugfs_init(struct radeon_device *rdev);
998 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode);
999 
1000 void radeon_setup_mst_connector(struct drm_device *dev);
1001 
1002 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
1003 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
1004 #endif
1005