1 /*
2 * Samsung S5P Multi Format Codec v 5.0
3 *
4 * This file contains definitions of enums and structs used by the codec
5 * driver.
6 *
7 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
8 * Kamil Debski, <k.debski@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version
14 */
15
16 #ifndef S5P_MFC_COMMON_H_
17 #define S5P_MFC_COMMON_H_
18
19 #include "regs-mfc.h"
20 #include <linux/platform_device.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-ioctl.h>
25 #include <media/videobuf2-core.h>
26
27 /* Definitions related to MFC memory */
28
29 /* Offset base used to differentiate between CAPTURE and OUTPUT
30 * while mmaping */
31 #define DST_QUEUE_OFF_BASE (TASK_SIZE / 2)
32
33 /* Offset used by the hardware to store addresses */
34 #define MFC_OFFSET_SHIFT 11
35
36 #define FIRMWARE_ALIGN 0x20000 /* 128KB */
37 #define MFC_H264_CTX_BUF_SIZE 0x96000 /* 600KB per H264 instance */
38 #define MFC_CTX_BUF_SIZE 0x2800 /* 10KB per instance */
39 #define DESC_BUF_SIZE 0x20000 /* 128KB for DESC buffer */
40 #define SHARED_BUF_SIZE 0x2000 /* 8KB for shared buffer */
41
42 #define DEF_CPB_SIZE 0x40000 /* 512KB */
43
44 #define MFC_BANK1_ALLOC_CTX 0
45 #define MFC_BANK2_ALLOC_CTX 1
46
47 #define MFC_BANK1_ALIGN_ORDER 13
48 #define MFC_BANK2_ALIGN_ORDER 13
49 #define MFC_BASE_ALIGN_ORDER 17
50
51 #include <media/videobuf2-dma-contig.h>
52
s5p_mfc_mem_cookie(void * a,void * b)53 static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
54 {
55 /* Same functionality as the vb2_dma_contig_plane_paddr */
56 dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b);
57
58 return *paddr;
59 }
60
61 /* MFC definitions */
62 #define MFC_MAX_EXTRA_DPB 5
63 #define MFC_MAX_BUFFERS 32
64 #define MFC_NUM_CONTEXTS 4
65 /* Interrupt timeout */
66 #define MFC_INT_TIMEOUT 2000
67 /* Busy wait timeout */
68 #define MFC_BW_TIMEOUT 500
69 /* Watchdog interval */
70 #define MFC_WATCHDOG_INTERVAL 1000
71 /* After how many executions watchdog should assume lock up */
72 #define MFC_WATCHDOG_CNT 10
73 #define MFC_NO_INSTANCE_SET -1
74 #define MFC_ENC_CAP_PLANE_COUNT 1
75 #define MFC_ENC_OUT_PLANE_COUNT 2
76 #define STUFF_BYTE 4
77 #define MFC_MAX_CTRLS 64
78
79 #define mfc_read(dev, offset) readl(dev->regs_base + (offset))
80 #define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
81 (offset))
82
83 /**
84 * enum s5p_mfc_fmt_type - type of the pixelformat
85 */
86 enum s5p_mfc_fmt_type {
87 MFC_FMT_DEC,
88 MFC_FMT_ENC,
89 MFC_FMT_RAW,
90 };
91
92 /**
93 * enum s5p_mfc_node_type - The type of an MFC device node.
94 */
95 enum s5p_mfc_node_type {
96 MFCNODE_INVALID = -1,
97 MFCNODE_DECODER = 0,
98 MFCNODE_ENCODER = 1,
99 };
100
101 /**
102 * enum s5p_mfc_inst_type - The type of an MFC instance.
103 */
104 enum s5p_mfc_inst_type {
105 MFCINST_INVALID,
106 MFCINST_DECODER,
107 MFCINST_ENCODER,
108 };
109
110 /**
111 * enum s5p_mfc_inst_state - The state of an MFC instance.
112 */
113 enum s5p_mfc_inst_state {
114 MFCINST_FREE = 0,
115 MFCINST_INIT = 100,
116 MFCINST_GOT_INST,
117 MFCINST_HEAD_PARSED,
118 MFCINST_BUFS_SET,
119 MFCINST_RUNNING,
120 MFCINST_FINISHING,
121 MFCINST_FINISHED,
122 MFCINST_RETURN_INST,
123 MFCINST_ERROR,
124 MFCINST_ABORT,
125 MFCINST_RES_CHANGE_INIT,
126 MFCINST_RES_CHANGE_FLUSH,
127 MFCINST_RES_CHANGE_END,
128 };
129
130 /**
131 * enum s5p_mfc_queue_state - The state of buffer queue.
132 */
133 enum s5p_mfc_queue_state {
134 QUEUE_FREE,
135 QUEUE_BUFS_REQUESTED,
136 QUEUE_BUFS_QUERIED,
137 QUEUE_BUFS_MMAPED,
138 };
139
140 /**
141 * enum s5p_mfc_decode_arg - type of frame decoding
142 */
143 enum s5p_mfc_decode_arg {
144 MFC_DEC_FRAME,
145 MFC_DEC_LAST_FRAME,
146 MFC_DEC_RES_CHANGE,
147 };
148
149 struct s5p_mfc_ctx;
150
151 /**
152 * struct s5p_mfc_buf - MFC buffer
153 */
154 struct s5p_mfc_buf {
155 struct list_head list;
156 struct vb2_buffer *b;
157 union {
158 struct {
159 size_t luma;
160 size_t chroma;
161 } raw;
162 size_t stream;
163 } cookie;
164 int used;
165 };
166
167 /**
168 * struct s5p_mfc_pm - power management data structure
169 */
170 struct s5p_mfc_pm {
171 struct clk *clock;
172 struct clk *clock_gate;
173 atomic_t power;
174 struct device *device;
175 };
176
177 /**
178 * struct s5p_mfc_dev - The struct containing driver internal parameters.
179 *
180 * @v4l2_dev: v4l2_device
181 * @vfd_dec: video device for decoding
182 * @vfd_enc: video device for encoding
183 * @plat_dev: platform device
184 * @mem_dev_l: child device of the left memory bank (0)
185 * @mem_dev_r: child device of the right memory bank (1)
186 * @regs_base: base address of the MFC hw registers
187 * @irq: irq resource
188 * @mfc_mem: MFC registers memory resource
189 * @dec_ctrl_handler: control framework handler for decoding
190 * @enc_ctrl_handler: control framework handler for encoding
191 * @pm: power management control
192 * @num_inst: couter of active MFC instances
193 * @irqlock: lock for operations on videobuf2 queues
194 * @condlock: lock for changing/checking if a context is ready to be
195 * processed
196 * @mfc_mutex: lock for video_device
197 * @int_cond: variable used by the waitqueue
198 * @int_type: type of last interrupt
199 * @int_err: error number for last interrupt
200 * @queue: waitqueue for waiting for completion of device commands
201 * @fw_size: size of firmware
202 * @bank1: address of the beggining of bank 1 memory
203 * @bank2: address of the beggining of bank 2 memory
204 * @hw_lock: used for hardware locking
205 * @ctx: array of driver contexts
206 * @curr_ctx: number of the currently running context
207 * @ctx_work_bits: used to mark which contexts are waiting for hardware
208 * @watchdog_cnt: counter for the watchdog
209 * @watchdog_workqueue: workqueue for the watchdog
210 * @watchdog_work: worker for the watchdog
211 * @alloc_ctx: videobuf2 allocator contexts for two memory banks
212 * @enter_suspend: flag set when entering suspend
213 *
214 */
215 struct s5p_mfc_dev {
216 struct v4l2_device v4l2_dev;
217 struct video_device *vfd_dec;
218 struct video_device *vfd_enc;
219 struct platform_device *plat_dev;
220 struct device *mem_dev_l;
221 struct device *mem_dev_r;
222 void __iomem *regs_base;
223 int irq;
224 struct resource *mfc_mem;
225 struct v4l2_ctrl_handler dec_ctrl_handler;
226 struct v4l2_ctrl_handler enc_ctrl_handler;
227 struct s5p_mfc_pm pm;
228 int num_inst;
229 spinlock_t irqlock; /* lock when operating on videobuf2 queues */
230 spinlock_t condlock; /* lock when changing/checking if a context is
231 ready to be processed */
232 struct mutex mfc_mutex; /* video_device lock */
233 int int_cond;
234 int int_type;
235 unsigned int int_err;
236 wait_queue_head_t queue;
237 size_t fw_size;
238 size_t bank1;
239 size_t bank2;
240 unsigned long hw_lock;
241 struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
242 int curr_ctx;
243 unsigned long ctx_work_bits;
244 atomic_t watchdog_cnt;
245 struct timer_list watchdog_timer;
246 struct workqueue_struct *watchdog_workqueue;
247 struct work_struct watchdog_work;
248 void *alloc_ctx[2];
249 unsigned long enter_suspend;
250 };
251
252 /**
253 * struct s5p_mfc_h264_enc_params - encoding parameters for h264
254 */
255 struct s5p_mfc_h264_enc_params {
256 enum v4l2_mpeg_video_h264_profile profile;
257 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
258 s8 loop_filter_alpha;
259 s8 loop_filter_beta;
260 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
261 u8 max_ref_pic;
262 u8 num_ref_pic_4p;
263 int _8x8_transform;
264 int rc_mb;
265 int rc_mb_dark;
266 int rc_mb_smooth;
267 int rc_mb_static;
268 int rc_mb_activity;
269 int vui_sar;
270 u8 vui_sar_idc;
271 u16 vui_ext_sar_width;
272 u16 vui_ext_sar_height;
273 int open_gop;
274 u16 open_gop_size;
275 u8 rc_frame_qp;
276 u8 rc_min_qp;
277 u8 rc_max_qp;
278 u8 rc_p_frame_qp;
279 u8 rc_b_frame_qp;
280 enum v4l2_mpeg_video_h264_level level_v4l2;
281 int level;
282 u16 cpb_size;
283 };
284
285 /**
286 * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
287 */
288 struct s5p_mfc_mpeg4_enc_params {
289 /* MPEG4 Only */
290 enum v4l2_mpeg_video_mpeg4_profile profile;
291 int quarter_pixel;
292 /* Common for MPEG4, H263 */
293 u16 vop_time_res;
294 u16 vop_frm_delta;
295 u8 rc_frame_qp;
296 u8 rc_min_qp;
297 u8 rc_max_qp;
298 u8 rc_p_frame_qp;
299 u8 rc_b_frame_qp;
300 enum v4l2_mpeg_video_mpeg4_level level_v4l2;
301 int level;
302 };
303
304 /**
305 * struct s5p_mfc_enc_params - general encoding parameters
306 */
307 struct s5p_mfc_enc_params {
308 u16 width;
309 u16 height;
310
311 u16 gop_size;
312 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
313 u16 slice_mb;
314 u32 slice_bit;
315 u16 intra_refresh_mb;
316 int pad;
317 u8 pad_luma;
318 u8 pad_cb;
319 u8 pad_cr;
320 int rc_frame;
321 u32 rc_bitrate;
322 u16 rc_reaction_coeff;
323 u16 vbv_size;
324
325 enum v4l2_mpeg_video_header_mode seq_hdr_mode;
326 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
327 int fixed_target_bit;
328
329 u8 num_b_frame;
330 u32 rc_framerate_num;
331 u32 rc_framerate_denom;
332 int interlace;
333
334 union {
335 struct s5p_mfc_h264_enc_params h264;
336 struct s5p_mfc_mpeg4_enc_params mpeg4;
337 } codec;
338
339 };
340
341 /**
342 * struct s5p_mfc_codec_ops - codec ops, used by encoding
343 */
344 struct s5p_mfc_codec_ops {
345 /* initialization routines */
346 int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
347 int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
348 /* execution routines */
349 int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
350 int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
351 };
352
353 #define call_cop(c, op, args...) \
354 (((c)->c_ops->op) ? \
355 ((c)->c_ops->op(args)) : 0)
356
357 /**
358 * struct s5p_mfc_ctx - This struct contains the instance context
359 *
360 * @dev: pointer to the s5p_mfc_dev of the device
361 * @fh: struct v4l2_fh
362 * @num: number of the context that this structure describes
363 * @int_cond: variable used by the waitqueue
364 * @int_type: type of the last interrupt
365 * @int_err: error number received from MFC hw in the interrupt
366 * @queue: waitqueue that can be used to wait for this context to
367 * finish
368 * @src_fmt: source pixelformat information
369 * @dst_fmt: destination pixelformat information
370 * @vq_src: vb2 queue for source buffers
371 * @vq_dst: vb2 queue for destination buffers
372 * @src_queue: driver internal queue for source buffers
373 * @dst_queue: driver internal queue for destination buffers
374 * @src_queue_cnt: number of buffers queued on the source internal queue
375 * @dst_queue_cnt: number of buffers queued on the dest internal queue
376 * @type: type of the instance - decoder or encoder
377 * @state: state of the context
378 * @inst_no: number of hw instance associated with the context
379 * @img_width: width of the image that is decoded or encoded
380 * @img_height: height of the image that is decoded or encoded
381 * @buf_width: width of the buffer for processed image
382 * @buf_height: height of the buffer for processed image
383 * @luma_size: size of a luma plane
384 * @chroma_size: size of a chroma plane
385 * @mv_size: size of a motion vectors buffer
386 * @consumed_stream: number of bytes that have been used so far from the
387 * decoding buffer
388 * @dpb_flush_flag: flag used to indicate that a DPB buffers are being
389 * flushed
390 * @bank1_buf: handle to memory allocated for temporary buffers from
391 * memory bank 1
392 * @bank1_phys: address of the temporary buffers from memory bank 1
393 * @bank1_size: size of the memory allocated for temporary buffers from
394 * memory bank 1
395 * @bank2_buf: handle to memory allocated for temporary buffers from
396 * memory bank 2
397 * @bank2_phys: address of the temporary buffers from memory bank 2
398 * @bank2_size: size of the memory allocated for temporary buffers from
399 * memory bank 2
400 * @capture_state: state of the capture buffers queue
401 * @output_state: state of the output buffers queue
402 * @src_bufs: information on allocated source buffers
403 * @dst_bufs: information on allocated destination buffers
404 * @sequence: counter for the sequence number for v4l2
405 * @dec_dst_flag: flags for buffers queued in the hardware
406 * @dec_src_buf_size: size of the buffer for source buffers in decoding
407 * @codec_mode: number of codec mode used by MFC hw
408 * @slice_interface: slice interface flag
409 * @loop_filter_mpeg4: loop filter for MPEG4 flag
410 * @display_delay: value of the display delay for H264
411 * @display_delay_enable: display delay for H264 enable flag
412 * @after_packed_pb: flag used to track buffer when stream is in
413 * Packed PB format
414 * @dpb_count: count of the DPB buffers required by MFC hw
415 * @total_dpb_count: count of DPB buffers with additional buffers
416 * requested by the application
417 * @ctx_buf: handle to the memory associated with this context
418 * @ctx_phys: address of the memory associated with this context
419 * @ctx_size: size of the memory associated with this context
420 * @desc_buf: description buffer for decoding handle
421 * @desc_phys: description buffer for decoding address
422 * @shm_alloc: handle for the shared memory buffer
423 * @shm: virtual address for the shared memory buffer
424 * @shm_ofs: address offset for shared memory
425 * @enc_params: encoding parameters for MFC
426 * @enc_dst_buf_size: size of the buffers for encoder output
427 * @frame_type: used to force the type of the next encoded frame
428 * @ref_queue: list of the reference buffers for encoding
429 * @ref_queue_cnt: number of the buffers in the reference list
430 * @c_ops: ops for encoding
431 * @ctrls: array of controls, used when adding controls to the
432 * v4l2 control framework
433 * @ctrl_handler: handler for v4l2 framework
434 */
435 struct s5p_mfc_ctx {
436 struct s5p_mfc_dev *dev;
437 struct v4l2_fh fh;
438
439 int num;
440
441 int int_cond;
442 int int_type;
443 unsigned int int_err;
444 wait_queue_head_t queue;
445
446 struct s5p_mfc_fmt *src_fmt;
447 struct s5p_mfc_fmt *dst_fmt;
448
449 struct vb2_queue vq_src;
450 struct vb2_queue vq_dst;
451
452 struct list_head src_queue;
453 struct list_head dst_queue;
454
455 unsigned int src_queue_cnt;
456 unsigned int dst_queue_cnt;
457
458 enum s5p_mfc_inst_type type;
459 enum s5p_mfc_inst_state state;
460 int inst_no;
461
462 /* Image parameters */
463 int img_width;
464 int img_height;
465 int buf_width;
466 int buf_height;
467
468 int luma_size;
469 int chroma_size;
470 int mv_size;
471
472 unsigned long consumed_stream;
473
474 unsigned int dpb_flush_flag;
475
476 /* Buffers */
477 void *bank1_buf;
478 size_t bank1_phys;
479 size_t bank1_size;
480
481 void *bank2_buf;
482 size_t bank2_phys;
483 size_t bank2_size;
484
485 enum s5p_mfc_queue_state capture_state;
486 enum s5p_mfc_queue_state output_state;
487
488 struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
489 int src_bufs_cnt;
490 struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
491 int dst_bufs_cnt;
492
493 unsigned int sequence;
494 unsigned long dec_dst_flag;
495 size_t dec_src_buf_size;
496
497 /* Control values */
498 int codec_mode;
499 int slice_interface;
500 int loop_filter_mpeg4;
501 int display_delay;
502 int display_delay_enable;
503 int after_packed_pb;
504
505 int dpb_count;
506 int total_dpb_count;
507
508 /* Buffers */
509 void *ctx_buf;
510 size_t ctx_phys;
511 size_t ctx_ofs;
512 size_t ctx_size;
513
514 void *desc_buf;
515 size_t desc_phys;
516
517
518 void *shm_alloc;
519 void *shm;
520 size_t shm_ofs;
521
522 struct s5p_mfc_enc_params enc_params;
523
524 size_t enc_dst_buf_size;
525
526 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
527
528 struct list_head ref_queue;
529 unsigned int ref_queue_cnt;
530
531 struct s5p_mfc_codec_ops *c_ops;
532
533 struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
534 struct v4l2_ctrl_handler ctrl_handler;
535 };
536
537 /*
538 * struct s5p_mfc_fmt - structure used to store information about pixelformats
539 * used by the MFC
540 */
541 struct s5p_mfc_fmt {
542 char *name;
543 u32 fourcc;
544 u32 codec_mode;
545 enum s5p_mfc_fmt_type type;
546 u32 num_planes;
547 };
548
549 /**
550 * struct mfc_control - structure used to store information about MFC controls
551 * it is used to initialize the control framework.
552 */
553 struct mfc_control {
554 __u32 id;
555 enum v4l2_ctrl_type type;
556 __u8 name[32]; /* Whatever */
557 __s32 minimum; /* Note signedness */
558 __s32 maximum;
559 __s32 step;
560 __u32 menu_skip_mask;
561 __s32 default_value;
562 __u32 flags;
563 __u32 reserved[2];
564 __u8 is_volatile;
565 };
566
567
568 #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
569 #define ctrl_to_ctx(__ctrl) \
570 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
571
572 #endif /* S5P_MFC_COMMON_H_ */
573