1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
3 */
4
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
7
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
12 #include <net/dsa.h>
13
14 /* Port Group IDs (PGID) are masks of destination ports.
15 *
16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
17 * frame, and forwards the frame to the ports that are present in the logical
18 * AND of all 3 PGIDs.
19 *
20 * These PGID lookups are:
21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
22 * which the switch selects a destination PGID:
23 * - The {DMAC, VID} is present in the MAC table. In that case, the
24 * destination PGID is given by the DEST_IDX field of the MAC table entry
25 * that matched.
26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
27 * frame is disseminated as being either unicast, multicast or broadcast,
28 * and according to that, the destination PGID is chosen as being the
29 * value contained by ANA_FLOODING_FLD_UNICAST,
30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
31 * The destination PGID can be an unicast set: the first PGIDs, 0 to
32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
34 * a physical port and has a single bit set in the destination ports mask:
35 * that corresponding to the port number itself. In contrast, a multicast
36 * PGID will have potentially more than one single bit set in the destination
37 * ports mask.
38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
39 * dissects each frame and generates a 4-bit Link Aggregation Code which is
40 * used for this second PGID table lookup. The goal of link aggregation is to
41 * hash multiple flows within the same LAG on to different destination ports.
42 * The first lookup will result in a PGID with all the LAG members present in
43 * the destination ports mask, and the second lookup, by Link Aggregation
44 * Code, will ensure that each flow gets forwarded only to a single port out
45 * of that mask (there are no duplicates).
46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
47 * is indexed with the ingress port (plus 80). These PGIDs answer the
48 * question "is port i allowed to forward traffic to port j?" If yes, then
49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
51 */
52
53 /* Reserve some destination PGIDs at the end of the range:
54 * PGID_BLACKHOLE: used for not forwarding the frames
55 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
56 * of the switch port net devices, towards the CPU port module.
57 * PGID_UC: the flooding destinations for unknown unicast traffic.
58 * PGID_MC: the flooding destinations for non-IP multicast traffic.
59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
61 * PGID_BC: the flooding destinations for broadcast traffic.
62 */
63 #define PGID_BLACKHOLE 57
64 #define PGID_CPU 58
65 #define PGID_UC 59
66 #define PGID_MC 60
67 #define PGID_MCIPV4 61
68 #define PGID_MCIPV6 62
69 #define PGID_BC 63
70
71 #define for_each_unicast_dest_pgid(ocelot, pgid) \
72 for ((pgid) = 0; \
73 (pgid) < (ocelot)->num_phys_ports; \
74 (pgid)++)
75
76 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \
77 for ((pgid) = (ocelot)->num_phys_ports + 1; \
78 (pgid) < PGID_BLACKHOLE; \
79 (pgid)++)
80
81 #define for_each_aggr_pgid(ocelot, pgid) \
82 for ((pgid) = PGID_AGGR; \
83 (pgid) < PGID_SRC; \
84 (pgid)++)
85
86 /* Aggregation PGIDs, one per Link Aggregation Code */
87 #define PGID_AGGR 64
88
89 /* Source PGIDs, one per physical port */
90 #define PGID_SRC 80
91
92 #define OCELOT_NUM_TC 8
93
94 #define OCELOT_SPEED_2500 0
95 #define OCELOT_SPEED_1000 1
96 #define OCELOT_SPEED_100 2
97 #define OCELOT_SPEED_10 3
98
99 #define OCELOT_PTP_PINS_NUM 4
100
101 #define TARGET_OFFSET 24
102 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
103 #define REG(reg, offset) [reg & REG_MASK] = offset
104
105 #define REG_RESERVED_ADDR 0xffffffff
106 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
107
108 enum ocelot_target {
109 ANA = 1,
110 QS,
111 QSYS,
112 REW,
113 SYS,
114 S0,
115 S1,
116 S2,
117 HSIO,
118 PTP,
119 FDMA,
120 GCB,
121 DEV_GMII,
122 TARGET_MAX,
123 };
124
125 enum ocelot_reg {
126 ANA_ADVLEARN = ANA << TARGET_OFFSET,
127 ANA_VLANMASK,
128 ANA_PORT_B_DOMAIN,
129 ANA_ANAGEFIL,
130 ANA_ANEVENTS,
131 ANA_STORMLIMIT_BURST,
132 ANA_STORMLIMIT_CFG,
133 ANA_ISOLATED_PORTS,
134 ANA_COMMUNITY_PORTS,
135 ANA_AUTOAGE,
136 ANA_MACTOPTIONS,
137 ANA_LEARNDISC,
138 ANA_AGENCTRL,
139 ANA_MIRRORPORTS,
140 ANA_EMIRRORPORTS,
141 ANA_FLOODING,
142 ANA_FLOODING_IPMC,
143 ANA_SFLOW_CFG,
144 ANA_PORT_MODE,
145 ANA_CUT_THRU_CFG,
146 ANA_PGID_PGID,
147 ANA_TABLES_ANMOVED,
148 ANA_TABLES_MACHDATA,
149 ANA_TABLES_MACLDATA,
150 ANA_TABLES_STREAMDATA,
151 ANA_TABLES_MACACCESS,
152 ANA_TABLES_MACTINDX,
153 ANA_TABLES_VLANACCESS,
154 ANA_TABLES_VLANTIDX,
155 ANA_TABLES_ISDXACCESS,
156 ANA_TABLES_ISDXTIDX,
157 ANA_TABLES_ENTRYLIM,
158 ANA_TABLES_PTP_ID_HIGH,
159 ANA_TABLES_PTP_ID_LOW,
160 ANA_TABLES_STREAMACCESS,
161 ANA_TABLES_STREAMTIDX,
162 ANA_TABLES_SEQ_HISTORY,
163 ANA_TABLES_SEQ_MASK,
164 ANA_TABLES_SFID_MASK,
165 ANA_TABLES_SFIDACCESS,
166 ANA_TABLES_SFIDTIDX,
167 ANA_MSTI_STATE,
168 ANA_OAM_UPM_LM_CNT,
169 ANA_SG_ACCESS_CTRL,
170 ANA_SG_CONFIG_REG_1,
171 ANA_SG_CONFIG_REG_2,
172 ANA_SG_CONFIG_REG_3,
173 ANA_SG_CONFIG_REG_4,
174 ANA_SG_CONFIG_REG_5,
175 ANA_SG_GCL_GS_CONFIG,
176 ANA_SG_GCL_TI_CONFIG,
177 ANA_SG_STATUS_REG_1,
178 ANA_SG_STATUS_REG_2,
179 ANA_SG_STATUS_REG_3,
180 ANA_PORT_VLAN_CFG,
181 ANA_PORT_DROP_CFG,
182 ANA_PORT_QOS_CFG,
183 ANA_PORT_VCAP_CFG,
184 ANA_PORT_VCAP_S1_KEY_CFG,
185 ANA_PORT_VCAP_S2_CFG,
186 ANA_PORT_PCP_DEI_MAP,
187 ANA_PORT_CPU_FWD_CFG,
188 ANA_PORT_CPU_FWD_BPDU_CFG,
189 ANA_PORT_CPU_FWD_GARP_CFG,
190 ANA_PORT_CPU_FWD_CCM_CFG,
191 ANA_PORT_PORT_CFG,
192 ANA_PORT_POL_CFG,
193 ANA_PORT_PTP_CFG,
194 ANA_PORT_PTP_DLY1_CFG,
195 ANA_PORT_PTP_DLY2_CFG,
196 ANA_PORT_SFID_CFG,
197 ANA_PFC_PFC_CFG,
198 ANA_PFC_PFC_TIMER,
199 ANA_IPT_OAM_MEP_CFG,
200 ANA_IPT_IPT,
201 ANA_PPT_PPT,
202 ANA_FID_MAP_FID_MAP,
203 ANA_AGGR_CFG,
204 ANA_CPUQ_CFG,
205 ANA_CPUQ_CFG2,
206 ANA_CPUQ_8021_CFG,
207 ANA_DSCP_CFG,
208 ANA_DSCP_REWR_CFG,
209 ANA_VCAP_RNG_TYPE_CFG,
210 ANA_VCAP_RNG_VAL_CFG,
211 ANA_VRAP_CFG,
212 ANA_VRAP_HDR_DATA,
213 ANA_VRAP_HDR_MASK,
214 ANA_DISCARD_CFG,
215 ANA_FID_CFG,
216 ANA_POL_PIR_CFG,
217 ANA_POL_CIR_CFG,
218 ANA_POL_MODE_CFG,
219 ANA_POL_PIR_STATE,
220 ANA_POL_CIR_STATE,
221 ANA_POL_STATE,
222 ANA_POL_FLOWC,
223 ANA_POL_HYST,
224 ANA_POL_MISC_CFG,
225 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
226 QS_XTR_RD,
227 QS_XTR_FRM_PRUNING,
228 QS_XTR_FLUSH,
229 QS_XTR_DATA_PRESENT,
230 QS_XTR_CFG,
231 QS_INJ_GRP_CFG,
232 QS_INJ_WR,
233 QS_INJ_CTRL,
234 QS_INJ_STATUS,
235 QS_INJ_ERR,
236 QS_INH_DBG,
237 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
238 QSYS_SWITCH_PORT_MODE,
239 QSYS_STAT_CNT_CFG,
240 QSYS_EEE_CFG,
241 QSYS_EEE_THRES,
242 QSYS_IGR_NO_SHARING,
243 QSYS_EGR_NO_SHARING,
244 QSYS_SW_STATUS,
245 QSYS_EXT_CPU_CFG,
246 QSYS_PAD_CFG,
247 QSYS_CPU_GROUP_MAP,
248 QSYS_QMAP,
249 QSYS_ISDX_SGRP,
250 QSYS_TIMED_FRAME_ENTRY,
251 QSYS_TFRM_MISC,
252 QSYS_TFRM_PORT_DLY,
253 QSYS_TFRM_TIMER_CFG_1,
254 QSYS_TFRM_TIMER_CFG_2,
255 QSYS_TFRM_TIMER_CFG_3,
256 QSYS_TFRM_TIMER_CFG_4,
257 QSYS_TFRM_TIMER_CFG_5,
258 QSYS_TFRM_TIMER_CFG_6,
259 QSYS_TFRM_TIMER_CFG_7,
260 QSYS_TFRM_TIMER_CFG_8,
261 QSYS_RED_PROFILE,
262 QSYS_RES_QOS_MODE,
263 QSYS_RES_CFG,
264 QSYS_RES_STAT,
265 QSYS_EGR_DROP_MODE,
266 QSYS_EQ_CTRL,
267 QSYS_EVENTS_CORE,
268 QSYS_QMAXSDU_CFG_0,
269 QSYS_QMAXSDU_CFG_1,
270 QSYS_QMAXSDU_CFG_2,
271 QSYS_QMAXSDU_CFG_3,
272 QSYS_QMAXSDU_CFG_4,
273 QSYS_QMAXSDU_CFG_5,
274 QSYS_QMAXSDU_CFG_6,
275 QSYS_QMAXSDU_CFG_7,
276 QSYS_PREEMPTION_CFG,
277 QSYS_CIR_CFG,
278 QSYS_EIR_CFG,
279 QSYS_SE_CFG,
280 QSYS_SE_DWRR_CFG,
281 QSYS_SE_CONNECT,
282 QSYS_SE_DLB_SENSE,
283 QSYS_CIR_STATE,
284 QSYS_EIR_STATE,
285 QSYS_SE_STATE,
286 QSYS_HSCH_MISC_CFG,
287 QSYS_TAG_CONFIG,
288 QSYS_TAS_PARAM_CFG_CTRL,
289 QSYS_PORT_MAX_SDU,
290 QSYS_PARAM_CFG_REG_1,
291 QSYS_PARAM_CFG_REG_2,
292 QSYS_PARAM_CFG_REG_3,
293 QSYS_PARAM_CFG_REG_4,
294 QSYS_PARAM_CFG_REG_5,
295 QSYS_GCL_CFG_REG_1,
296 QSYS_GCL_CFG_REG_2,
297 QSYS_PARAM_STATUS_REG_1,
298 QSYS_PARAM_STATUS_REG_2,
299 QSYS_PARAM_STATUS_REG_3,
300 QSYS_PARAM_STATUS_REG_4,
301 QSYS_PARAM_STATUS_REG_5,
302 QSYS_PARAM_STATUS_REG_6,
303 QSYS_PARAM_STATUS_REG_7,
304 QSYS_PARAM_STATUS_REG_8,
305 QSYS_PARAM_STATUS_REG_9,
306 QSYS_GCL_STATUS_REG_1,
307 QSYS_GCL_STATUS_REG_2,
308 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
309 REW_TAG_CFG,
310 REW_PORT_CFG,
311 REW_DSCP_CFG,
312 REW_PCP_DEI_QOS_MAP_CFG,
313 REW_PTP_CFG,
314 REW_PTP_DLY1_CFG,
315 REW_RED_TAG_CFG,
316 REW_DSCP_REMAP_DP1_CFG,
317 REW_DSCP_REMAP_CFG,
318 REW_STAT_CFG,
319 REW_REW_STICKY,
320 REW_PPT,
321 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
322 SYS_COUNT_RX_UNICAST,
323 SYS_COUNT_RX_MULTICAST,
324 SYS_COUNT_RX_BROADCAST,
325 SYS_COUNT_RX_SHORTS,
326 SYS_COUNT_RX_FRAGMENTS,
327 SYS_COUNT_RX_JABBERS,
328 SYS_COUNT_RX_CRC_ALIGN_ERRS,
329 SYS_COUNT_RX_SYM_ERRS,
330 SYS_COUNT_RX_64,
331 SYS_COUNT_RX_65_127,
332 SYS_COUNT_RX_128_255,
333 SYS_COUNT_RX_256_511,
334 SYS_COUNT_RX_512_1023,
335 SYS_COUNT_RX_1024_1526,
336 SYS_COUNT_RX_1527_MAX,
337 SYS_COUNT_RX_PAUSE,
338 SYS_COUNT_RX_CONTROL,
339 SYS_COUNT_RX_LONGS,
340 SYS_COUNT_RX_CLASSIFIED_DROPS,
341 SYS_COUNT_TX_OCTETS,
342 SYS_COUNT_TX_UNICAST,
343 SYS_COUNT_TX_MULTICAST,
344 SYS_COUNT_TX_BROADCAST,
345 SYS_COUNT_TX_COLLISION,
346 SYS_COUNT_TX_DROPS,
347 SYS_COUNT_TX_PAUSE,
348 SYS_COUNT_TX_64,
349 SYS_COUNT_TX_65_127,
350 SYS_COUNT_TX_128_255,
351 SYS_COUNT_TX_256_511,
352 SYS_COUNT_TX_512_1023,
353 SYS_COUNT_TX_1024_1526,
354 SYS_COUNT_TX_1527_MAX,
355 SYS_COUNT_TX_AGING,
356 SYS_RESET_CFG,
357 SYS_SR_ETYPE_CFG,
358 SYS_VLAN_ETYPE_CFG,
359 SYS_PORT_MODE,
360 SYS_FRONT_PORT_MODE,
361 SYS_FRM_AGING,
362 SYS_STAT_CFG,
363 SYS_SW_STATUS,
364 SYS_MISC_CFG,
365 SYS_REW_MAC_HIGH_CFG,
366 SYS_REW_MAC_LOW_CFG,
367 SYS_TIMESTAMP_OFFSET,
368 SYS_CMID,
369 SYS_PAUSE_CFG,
370 SYS_PAUSE_TOT_CFG,
371 SYS_ATOP,
372 SYS_ATOP_TOT_CFG,
373 SYS_MAC_FC_CFG,
374 SYS_MMGT,
375 SYS_MMGT_FAST,
376 SYS_EVENTS_DIF,
377 SYS_EVENTS_CORE,
378 SYS_CNT,
379 SYS_PTP_STATUS,
380 SYS_PTP_TXSTAMP,
381 SYS_PTP_NXT,
382 SYS_PTP_CFG,
383 SYS_RAM_INIT,
384 SYS_CM_ADDR,
385 SYS_CM_DATA_WR,
386 SYS_CM_DATA_RD,
387 SYS_CM_OP,
388 SYS_CM_DATA,
389 PTP_PIN_CFG = PTP << TARGET_OFFSET,
390 PTP_PIN_TOD_SEC_MSB,
391 PTP_PIN_TOD_SEC_LSB,
392 PTP_PIN_TOD_NSEC,
393 PTP_PIN_WF_HIGH_PERIOD,
394 PTP_PIN_WF_LOW_PERIOD,
395 PTP_CFG_MISC,
396 PTP_CLK_CFG_ADJ_CFG,
397 PTP_CLK_CFG_ADJ_FREQ,
398 GCB_SOFT_RST = GCB << TARGET_OFFSET,
399 GCB_MIIM_MII_STATUS,
400 GCB_MIIM_MII_CMD,
401 GCB_MIIM_MII_DATA,
402 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
403 DEV_PORT_MISC,
404 DEV_EVENTS,
405 DEV_EEE_CFG,
406 DEV_RX_PATH_DELAY,
407 DEV_TX_PATH_DELAY,
408 DEV_PTP_PREDICT_CFG,
409 DEV_MAC_ENA_CFG,
410 DEV_MAC_MODE_CFG,
411 DEV_MAC_MAXLEN_CFG,
412 DEV_MAC_TAGS_CFG,
413 DEV_MAC_ADV_CHK_CFG,
414 DEV_MAC_IFG_CFG,
415 DEV_MAC_HDX_CFG,
416 DEV_MAC_DBG_CFG,
417 DEV_MAC_FC_MAC_LOW_CFG,
418 DEV_MAC_FC_MAC_HIGH_CFG,
419 DEV_MAC_STICKY,
420 PCS1G_CFG,
421 PCS1G_MODE_CFG,
422 PCS1G_SD_CFG,
423 PCS1G_ANEG_CFG,
424 PCS1G_ANEG_NP_CFG,
425 PCS1G_LB_CFG,
426 PCS1G_DBG_CFG,
427 PCS1G_CDET_CFG,
428 PCS1G_ANEG_STATUS,
429 PCS1G_ANEG_NP_STATUS,
430 PCS1G_LINK_STATUS,
431 PCS1G_LINK_DOWN_CNT,
432 PCS1G_STICKY,
433 PCS1G_DEBUG_STATUS,
434 PCS1G_LPI_CFG,
435 PCS1G_LPI_WAKE_ERROR_CNT,
436 PCS1G_LPI_STATUS,
437 PCS1G_TSTPAT_MODE_CFG,
438 PCS1G_TSTPAT_STATUS,
439 DEV_PCS_FX100_CFG,
440 DEV_PCS_FX100_STATUS,
441 };
442
443 enum ocelot_regfield {
444 ANA_ADVLEARN_VLAN_CHK,
445 ANA_ADVLEARN_LEARN_MIRROR,
446 ANA_ANEVENTS_FLOOD_DISCARD,
447 ANA_ANEVENTS_MSTI_DROP,
448 ANA_ANEVENTS_ACLKILL,
449 ANA_ANEVENTS_ACLUSED,
450 ANA_ANEVENTS_AUTOAGE,
451 ANA_ANEVENTS_VS2TTL1,
452 ANA_ANEVENTS_STORM_DROP,
453 ANA_ANEVENTS_LEARN_DROP,
454 ANA_ANEVENTS_AGED_ENTRY,
455 ANA_ANEVENTS_CPU_LEARN_FAILED,
456 ANA_ANEVENTS_AUTO_LEARN_FAILED,
457 ANA_ANEVENTS_LEARN_REMOVE,
458 ANA_ANEVENTS_AUTO_LEARNED,
459 ANA_ANEVENTS_AUTO_MOVED,
460 ANA_ANEVENTS_DROPPED,
461 ANA_ANEVENTS_CLASSIFIED_DROP,
462 ANA_ANEVENTS_CLASSIFIED_COPY,
463 ANA_ANEVENTS_VLAN_DISCARD,
464 ANA_ANEVENTS_FWD_DISCARD,
465 ANA_ANEVENTS_MULTICAST_FLOOD,
466 ANA_ANEVENTS_UNICAST_FLOOD,
467 ANA_ANEVENTS_DEST_KNOWN,
468 ANA_ANEVENTS_BUCKET3_MATCH,
469 ANA_ANEVENTS_BUCKET2_MATCH,
470 ANA_ANEVENTS_BUCKET1_MATCH,
471 ANA_ANEVENTS_BUCKET0_MATCH,
472 ANA_ANEVENTS_CPU_OPERATION,
473 ANA_ANEVENTS_DMAC_LOOKUP,
474 ANA_ANEVENTS_SMAC_LOOKUP,
475 ANA_ANEVENTS_SEQ_GEN_ERR_0,
476 ANA_ANEVENTS_SEQ_GEN_ERR_1,
477 ANA_TABLES_MACACCESS_B_DOM,
478 ANA_TABLES_MACTINDX_BUCKET,
479 ANA_TABLES_MACTINDX_M_INDEX,
480 QSYS_SWITCH_PORT_MODE_PORT_ENA,
481 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG,
482 QSYS_SWITCH_PORT_MODE_YEL_RSRVD,
483 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,
484 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA,
485 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE,
486 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
487 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
488 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
489 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
490 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
491 SYS_PORT_MODE_DATA_WO_TS,
492 SYS_PORT_MODE_INCL_INJ_HDR,
493 SYS_PORT_MODE_INCL_XTR_HDR,
494 SYS_PORT_MODE_INCL_HDR_ERR,
495 SYS_RESET_CFG_CORE_ENA,
496 SYS_RESET_CFG_MEM_ENA,
497 SYS_RESET_CFG_MEM_INIT,
498 GCB_SOFT_RST_SWC_RST,
499 GCB_MIIM_MII_STATUS_PENDING,
500 GCB_MIIM_MII_STATUS_BUSY,
501 SYS_PAUSE_CFG_PAUSE_START,
502 SYS_PAUSE_CFG_PAUSE_STOP,
503 SYS_PAUSE_CFG_PAUSE_ENA,
504 REGFIELD_MAX
505 };
506
507 enum {
508 /* VCAP_CORE_CFG */
509 VCAP_CORE_UPDATE_CTRL,
510 VCAP_CORE_MV_CFG,
511 /* VCAP_CORE_CACHE */
512 VCAP_CACHE_ENTRY_DAT,
513 VCAP_CACHE_MASK_DAT,
514 VCAP_CACHE_ACTION_DAT,
515 VCAP_CACHE_CNT_DAT,
516 VCAP_CACHE_TG_DAT,
517 /* VCAP_CONST */
518 VCAP_CONST_VCAP_VER,
519 VCAP_CONST_ENTRY_WIDTH,
520 VCAP_CONST_ENTRY_CNT,
521 VCAP_CONST_ENTRY_SWCNT,
522 VCAP_CONST_ENTRY_TG_WIDTH,
523 VCAP_CONST_ACTION_DEF_CNT,
524 VCAP_CONST_ACTION_WIDTH,
525 VCAP_CONST_CNT_WIDTH,
526 VCAP_CONST_CORE_CNT,
527 VCAP_CONST_IF_CNT,
528 };
529
530 enum ocelot_ptp_pins {
531 PTP_PIN_0,
532 PTP_PIN_1,
533 PTP_PIN_2,
534 PTP_PIN_3,
535 TOD_ACC_PIN
536 };
537
538 enum ocelot_stat {
539 OCELOT_STAT_RX_OCTETS,
540 OCELOT_STAT_RX_UNICAST,
541 OCELOT_STAT_RX_MULTICAST,
542 OCELOT_STAT_RX_BROADCAST,
543 OCELOT_STAT_RX_SHORTS,
544 OCELOT_STAT_RX_FRAGMENTS,
545 OCELOT_STAT_RX_JABBERS,
546 OCELOT_STAT_RX_CRC_ALIGN_ERRS,
547 OCELOT_STAT_RX_SYM_ERRS,
548 OCELOT_STAT_RX_64,
549 OCELOT_STAT_RX_65_127,
550 OCELOT_STAT_RX_128_255,
551 OCELOT_STAT_RX_256_511,
552 OCELOT_STAT_RX_512_1023,
553 OCELOT_STAT_RX_1024_1526,
554 OCELOT_STAT_RX_1527_MAX,
555 OCELOT_STAT_RX_PAUSE,
556 OCELOT_STAT_RX_CONTROL,
557 OCELOT_STAT_RX_LONGS,
558 OCELOT_STAT_RX_CLASSIFIED_DROPS,
559 OCELOT_STAT_RX_RED_PRIO_0,
560 OCELOT_STAT_RX_RED_PRIO_1,
561 OCELOT_STAT_RX_RED_PRIO_2,
562 OCELOT_STAT_RX_RED_PRIO_3,
563 OCELOT_STAT_RX_RED_PRIO_4,
564 OCELOT_STAT_RX_RED_PRIO_5,
565 OCELOT_STAT_RX_RED_PRIO_6,
566 OCELOT_STAT_RX_RED_PRIO_7,
567 OCELOT_STAT_RX_YELLOW_PRIO_0,
568 OCELOT_STAT_RX_YELLOW_PRIO_1,
569 OCELOT_STAT_RX_YELLOW_PRIO_2,
570 OCELOT_STAT_RX_YELLOW_PRIO_3,
571 OCELOT_STAT_RX_YELLOW_PRIO_4,
572 OCELOT_STAT_RX_YELLOW_PRIO_5,
573 OCELOT_STAT_RX_YELLOW_PRIO_6,
574 OCELOT_STAT_RX_YELLOW_PRIO_7,
575 OCELOT_STAT_RX_GREEN_PRIO_0,
576 OCELOT_STAT_RX_GREEN_PRIO_1,
577 OCELOT_STAT_RX_GREEN_PRIO_2,
578 OCELOT_STAT_RX_GREEN_PRIO_3,
579 OCELOT_STAT_RX_GREEN_PRIO_4,
580 OCELOT_STAT_RX_GREEN_PRIO_5,
581 OCELOT_STAT_RX_GREEN_PRIO_6,
582 OCELOT_STAT_RX_GREEN_PRIO_7,
583 OCELOT_STAT_TX_OCTETS,
584 OCELOT_STAT_TX_UNICAST,
585 OCELOT_STAT_TX_MULTICAST,
586 OCELOT_STAT_TX_BROADCAST,
587 OCELOT_STAT_TX_COLLISION,
588 OCELOT_STAT_TX_DROPS,
589 OCELOT_STAT_TX_PAUSE,
590 OCELOT_STAT_TX_64,
591 OCELOT_STAT_TX_65_127,
592 OCELOT_STAT_TX_128_255,
593 OCELOT_STAT_TX_256_511,
594 OCELOT_STAT_TX_512_1023,
595 OCELOT_STAT_TX_1024_1526,
596 OCELOT_STAT_TX_1527_MAX,
597 OCELOT_STAT_TX_YELLOW_PRIO_0,
598 OCELOT_STAT_TX_YELLOW_PRIO_1,
599 OCELOT_STAT_TX_YELLOW_PRIO_2,
600 OCELOT_STAT_TX_YELLOW_PRIO_3,
601 OCELOT_STAT_TX_YELLOW_PRIO_4,
602 OCELOT_STAT_TX_YELLOW_PRIO_5,
603 OCELOT_STAT_TX_YELLOW_PRIO_6,
604 OCELOT_STAT_TX_YELLOW_PRIO_7,
605 OCELOT_STAT_TX_GREEN_PRIO_0,
606 OCELOT_STAT_TX_GREEN_PRIO_1,
607 OCELOT_STAT_TX_GREEN_PRIO_2,
608 OCELOT_STAT_TX_GREEN_PRIO_3,
609 OCELOT_STAT_TX_GREEN_PRIO_4,
610 OCELOT_STAT_TX_GREEN_PRIO_5,
611 OCELOT_STAT_TX_GREEN_PRIO_6,
612 OCELOT_STAT_TX_GREEN_PRIO_7,
613 OCELOT_STAT_TX_AGED,
614 OCELOT_STAT_DROP_LOCAL,
615 OCELOT_STAT_DROP_TAIL,
616 OCELOT_STAT_DROP_YELLOW_PRIO_0,
617 OCELOT_STAT_DROP_YELLOW_PRIO_1,
618 OCELOT_STAT_DROP_YELLOW_PRIO_2,
619 OCELOT_STAT_DROP_YELLOW_PRIO_3,
620 OCELOT_STAT_DROP_YELLOW_PRIO_4,
621 OCELOT_STAT_DROP_YELLOW_PRIO_5,
622 OCELOT_STAT_DROP_YELLOW_PRIO_6,
623 OCELOT_STAT_DROP_YELLOW_PRIO_7,
624 OCELOT_STAT_DROP_GREEN_PRIO_0,
625 OCELOT_STAT_DROP_GREEN_PRIO_1,
626 OCELOT_STAT_DROP_GREEN_PRIO_2,
627 OCELOT_STAT_DROP_GREEN_PRIO_3,
628 OCELOT_STAT_DROP_GREEN_PRIO_4,
629 OCELOT_STAT_DROP_GREEN_PRIO_5,
630 OCELOT_STAT_DROP_GREEN_PRIO_6,
631 OCELOT_STAT_DROP_GREEN_PRIO_7,
632 OCELOT_NUM_STATS,
633 };
634
635 struct ocelot_stat_layout {
636 u32 offset;
637 char name[ETH_GSTRING_LEN];
638 };
639
640 struct ocelot_stats_region {
641 struct list_head node;
642 u32 offset;
643 int count;
644 u32 *buf;
645 };
646
647 enum ocelot_tag_prefix {
648 OCELOT_TAG_PREFIX_DISABLED = 0,
649 OCELOT_TAG_PREFIX_NONE,
650 OCELOT_TAG_PREFIX_SHORT,
651 OCELOT_TAG_PREFIX_LONG,
652 };
653
654 struct ocelot;
655
656 struct ocelot_ops {
657 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
658 int (*netdev_to_port)(struct net_device *dev);
659 int (*reset)(struct ocelot *ocelot);
660 u16 (*wm_enc)(u16 value);
661 u16 (*wm_dec)(u16 value);
662 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse);
663 void (*psfp_init)(struct ocelot *ocelot);
664 int (*psfp_filter_add)(struct ocelot *ocelot, int port,
665 struct flow_cls_offload *f);
666 int (*psfp_filter_del)(struct ocelot *ocelot, struct flow_cls_offload *f);
667 int (*psfp_stats_get)(struct ocelot *ocelot, struct flow_cls_offload *f,
668 struct flow_stats *stats);
669 void (*cut_through_fwd)(struct ocelot *ocelot);
670 void (*tas_clock_adjust)(struct ocelot *ocelot);
671 };
672
673 struct ocelot_vcap_policer {
674 struct list_head pol_list;
675 u16 base;
676 u16 max;
677 u16 base2;
678 u16 max2;
679 };
680
681 struct ocelot_vcap_block {
682 struct list_head rules;
683 int count;
684 };
685
686 struct ocelot_bridge_vlan {
687 u16 vid;
688 unsigned long portmask;
689 unsigned long untagged;
690 struct list_head list;
691 };
692
693 enum ocelot_port_tag_config {
694 /* all VLANs are egress-untagged */
695 OCELOT_PORT_TAG_DISABLED = 0,
696 /* all VLANs except the native VLAN and VID 0 are egress-tagged */
697 OCELOT_PORT_TAG_NATIVE = 1,
698 /* all VLANs except VID 0 are egress-tagged */
699 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2,
700 /* all VLANs are egress-tagged */
701 OCELOT_PORT_TAG_TRUNK = 3,
702 };
703
704 struct ocelot_psfp_list {
705 struct list_head stream_list;
706 struct list_head sfi_list;
707 struct list_head sgi_list;
708 };
709
710 enum ocelot_sb {
711 OCELOT_SB_BUF,
712 OCELOT_SB_REF,
713 OCELOT_SB_NUM,
714 };
715
716 enum ocelot_sb_pool {
717 OCELOT_SB_POOL_ING,
718 OCELOT_SB_POOL_EGR,
719 OCELOT_SB_POOL_NUM,
720 };
721
722 /* MAC table entry types.
723 * ENTRYTYPE_NORMAL is subject to aging.
724 * ENTRYTYPE_LOCKED is not subject to aging.
725 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
726 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
727 */
728 enum macaccess_entry_type {
729 ENTRYTYPE_NORMAL = 0,
730 ENTRYTYPE_LOCKED,
731 ENTRYTYPE_MACv4,
732 ENTRYTYPE_MACv6,
733 };
734
735 #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0)
736 #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1)
737
738 struct ocelot_lag_fdb {
739 unsigned char addr[ETH_ALEN];
740 u16 vid;
741 struct net_device *bond;
742 struct list_head list;
743 };
744
745 struct ocelot_mirror {
746 refcount_t refcount;
747 int to;
748 };
749
750 struct ocelot_port;
751
752 struct ocelot_port {
753 struct ocelot *ocelot;
754
755 struct regmap *target;
756
757 struct net_device *bond;
758 struct net_device *bridge;
759
760 struct ocelot_port *dsa_8021q_cpu;
761
762 /* VLAN that untagged frames are classified to, on ingress */
763 const struct ocelot_bridge_vlan *pvid_vlan;
764
765 struct tc_taprio_qopt_offload *taprio;
766
767 phy_interface_t phy_mode;
768
769 unsigned int ptp_skbs_in_flight;
770 struct sk_buff_head tx_skbs;
771
772 u16 mrp_ring_id;
773
774 u8 ptp_cmd;
775 u8 ts_id;
776
777 u8 index;
778
779 u8 stp_state;
780 bool vlan_aware;
781 bool is_dsa_8021q_cpu;
782 bool learn_ena;
783
784 bool lag_tx_active;
785
786 int bridge_num;
787
788 int speed;
789 };
790
791 struct ocelot {
792 struct device *dev;
793 struct devlink *devlink;
794 struct devlink_port *devlink_ports;
795
796 const struct ocelot_ops *ops;
797 struct regmap *targets[TARGET_MAX];
798 struct regmap_field *regfields[REGFIELD_MAX];
799 const u32 *const *map;
800 const struct ocelot_stat_layout *stats_layout;
801 struct list_head stats_regions;
802
803 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM];
804 int packet_buffer_size;
805 int num_frame_refs;
806 int num_mact_rows;
807
808 struct ocelot_port **ports;
809
810 u8 base_mac[ETH_ALEN];
811
812 struct list_head vlans;
813 struct list_head traps;
814 struct list_head lag_fdbs;
815
816 /* Switches like VSC9959 have flooding per traffic class */
817 int num_flooding_pgids;
818
819 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
820 * the CPU is located after the physical ports (at the
821 * num_phys_ports index).
822 */
823 u8 num_phys_ports;
824
825 int npi;
826
827 enum ocelot_tag_prefix npi_inj_prefix;
828 enum ocelot_tag_prefix npi_xtr_prefix;
829
830 unsigned long bridges;
831
832 struct list_head multicast;
833 struct list_head pgids;
834
835 struct list_head dummy_rules;
836 struct ocelot_vcap_block block[3];
837 struct ocelot_vcap_policer vcap_pol;
838 struct vcap_props *vcap;
839 struct ocelot_mirror *mirror;
840
841 struct ocelot_psfp_list psfp;
842
843 /* Workqueue to check statistics for overflow with its lock */
844 spinlock_t stats_lock;
845 u64 *stats;
846 struct delayed_work stats_work;
847 struct workqueue_struct *stats_queue;
848
849 /* Lock for serializing access to the MAC table */
850 struct mutex mact_lock;
851 /* Lock for serializing forwarding domain changes */
852 struct mutex fwd_domain_lock;
853
854 /* Lock for serializing Time-Aware Shaper changes */
855 struct mutex tas_lock;
856
857 struct workqueue_struct *owq;
858
859 u8 ptp:1;
860 struct ptp_clock *ptp_clock;
861 struct ptp_clock_info ptp_info;
862 struct hwtstamp_config hwtstamp_config;
863 unsigned int ptp_skbs_in_flight;
864 /* Protects the 2-step TX timestamp ID logic */
865 spinlock_t ts_id_lock;
866 /* Protects the PTP interface state */
867 struct mutex ptp_lock;
868 /* Protects the PTP clock */
869 spinlock_t ptp_clock_lock;
870 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM];
871
872 struct ocelot_fdma *fdma;
873 };
874
875 struct ocelot_policer {
876 u32 rate; /* kilobit per second */
877 u32 burst; /* bytes */
878 };
879
880 #define ocelot_bulk_read_rix(ocelot, reg, ri, buf, count) \
881 __ocelot_bulk_read_ix(ocelot, reg, reg##_RSZ * (ri), buf, count)
882
883 #define ocelot_read_ix(ocelot, reg, gi, ri) \
884 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
885 #define ocelot_read_gix(ocelot, reg, gi) \
886 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
887 #define ocelot_read_rix(ocelot, reg, ri) \
888 __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
889 #define ocelot_read(ocelot, reg) \
890 __ocelot_read_ix(ocelot, reg, 0)
891
892 #define ocelot_write_ix(ocelot, val, reg, gi, ri) \
893 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
894 #define ocelot_write_gix(ocelot, val, reg, gi) \
895 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
896 #define ocelot_write_rix(ocelot, val, reg, ri) \
897 __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
898 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
899
900 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) \
901 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
902 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) \
903 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
904 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) \
905 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
906 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
907
908 #define ocelot_field_write(ocelot, reg, val) \
909 regmap_field_write((ocelot)->regfields[(reg)], (val))
910 #define ocelot_field_read(ocelot, reg, val) \
911 regmap_field_read((ocelot)->regfields[(reg)], (val))
912 #define ocelot_fields_write(ocelot, id, reg, val) \
913 regmap_fields_write((ocelot)->regfields[(reg)], (id), (val))
914 #define ocelot_fields_read(ocelot, id, reg, val) \
915 regmap_fields_read((ocelot)->regfields[(reg)], (id), (val))
916
917 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \
918 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
919 #define ocelot_target_read_gix(ocelot, target, reg, gi) \
920 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi))
921 #define ocelot_target_read_rix(ocelot, target, reg, ri) \
922 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri))
923 #define ocelot_target_read(ocelot, target, reg) \
924 __ocelot_target_read_ix(ocelot, target, reg, 0)
925
926 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \
927 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
928 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \
929 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi))
930 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \
931 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri))
932 #define ocelot_target_write(ocelot, target, val, reg) \
933 __ocelot_target_write_ix(ocelot, target, val, reg, 0)
934
935 /* I/O */
936 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
937 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
938 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg);
939 int __ocelot_bulk_read_ix(struct ocelot *ocelot, u32 reg, u32 offset, void *buf,
940 int count);
941 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
942 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
943 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
944 u32 offset);
945 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
946 u32 reg, u32 offset);
947 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
948 u32 val, u32 reg, u32 offset);
949
950 /* Packet I/O */
951 bool ocelot_can_inject(struct ocelot *ocelot, int grp);
952 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
953 u32 rew_op, struct sk_buff *skb);
954 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag);
955 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb);
956 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp);
957 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
958 u64 timestamp);
959
960 /* Hardware initialization */
961 int ocelot_regfields_init(struct ocelot *ocelot,
962 const struct reg_field *const regfields);
963 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
964 int ocelot_init(struct ocelot *ocelot);
965 void ocelot_deinit(struct ocelot *ocelot);
966 void ocelot_init_port(struct ocelot *ocelot, int port);
967 void ocelot_deinit_port(struct ocelot *ocelot, int port);
968
969 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu);
970 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port);
971 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port);
972
973 /* DSA callbacks */
974 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
975 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
976 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
977 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
978 struct ethtool_ts_info *info);
979 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
980 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled,
981 struct netlink_ext_ack *extack);
982 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
983 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port);
984 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
985 struct switchdev_brport_flags val);
986 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
987 struct switchdev_brport_flags val);
988 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port);
989 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio);
990 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp);
991 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
992 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
993 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
994 struct net_device *bridge, int bridge_num,
995 struct netlink_ext_ack *extack);
996 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
997 struct net_device *bridge);
998 int ocelot_mact_flush(struct ocelot *ocelot, int port);
999 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1000 dsa_fdb_dump_cb_t *cb, void *data);
1001 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1002 u16 vid, const struct net_device *bridge);
1003 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1004 u16 vid, const struct net_device *bridge);
1005 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
1006 const unsigned char *addr, u16 vid,
1007 const struct net_device *bridge);
1008 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
1009 const unsigned char *addr, u16 vid,
1010 const struct net_device *bridge);
1011 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
1012 bool untagged, struct netlink_ext_ack *extack);
1013 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
1014 bool untagged);
1015 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
1016 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
1017 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
1018 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
1019 struct sk_buff *skb,
1020 struct sk_buff **clone);
1021 void ocelot_get_txtstamp(struct ocelot *ocelot);
1022 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
1023 int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
1024 int ocelot_port_policer_add(struct ocelot *ocelot, int port,
1025 struct ocelot_policer *pol);
1026 int ocelot_port_policer_del(struct ocelot *ocelot, int port);
1027 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
1028 bool ingress, struct netlink_ext_ack *extack);
1029 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress);
1030 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
1031 struct flow_cls_offload *f, bool ingress);
1032 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
1033 struct flow_cls_offload *f, bool ingress);
1034 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
1035 struct flow_cls_offload *f, bool ingress);
1036 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1037 const struct switchdev_obj_port_mdb *mdb,
1038 const struct net_device *bridge);
1039 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1040 const struct switchdev_obj_port_mdb *mdb,
1041 const struct net_device *bridge);
1042 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1043 struct net_device *bond,
1044 struct netdev_lag_upper_info *info);
1045 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1046 struct net_device *bond);
1047 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active);
1048
1049 int ocelot_devlink_sb_register(struct ocelot *ocelot);
1050 void ocelot_devlink_sb_unregister(struct ocelot *ocelot);
1051 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index,
1052 u16 pool_index,
1053 struct devlink_sb_pool_info *pool_info);
1054 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index,
1055 u16 pool_index, u32 size,
1056 enum devlink_sb_threshold_type threshold_type,
1057 struct netlink_ext_ack *extack);
1058 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port,
1059 unsigned int sb_index, u16 pool_index,
1060 u32 *p_threshold);
1061 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port,
1062 unsigned int sb_index, u16 pool_index,
1063 u32 threshold, struct netlink_ext_ack *extack);
1064 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port,
1065 unsigned int sb_index, u16 tc_index,
1066 enum devlink_sb_pool_type pool_type,
1067 u16 *p_pool_index, u32 *p_threshold);
1068 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port,
1069 unsigned int sb_index, u16 tc_index,
1070 enum devlink_sb_pool_type pool_type,
1071 u16 pool_index, u32 threshold,
1072 struct netlink_ext_ack *extack);
1073 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index);
1074 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index);
1075 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port,
1076 unsigned int sb_index, u16 pool_index,
1077 u32 *p_cur, u32 *p_max);
1078 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port,
1079 unsigned int sb_index, u16 tc_index,
1080 enum devlink_sb_pool_type pool_type,
1081 u32 *p_cur, u32 *p_max);
1082
1083 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
1084 unsigned int link_an_mode,
1085 phy_interface_t interface,
1086 unsigned long quirks);
1087 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
1088 struct phy_device *phydev,
1089 unsigned int link_an_mode,
1090 phy_interface_t interface,
1091 int speed, int duplex,
1092 bool tx_pause, bool rx_pause,
1093 unsigned long quirks);
1094
1095 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
1096 const unsigned char mac[ETH_ALEN],
1097 unsigned int vid, enum macaccess_entry_type *type);
1098 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
1099 const unsigned char mac[ETH_ALEN],
1100 unsigned int vid,
1101 enum macaccess_entry_type type,
1102 int sfid, int ssid);
1103
1104 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
1105 unsigned long to_mask);
1106
1107 int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix,
1108 struct ocelot_policer *pol);
1109 int ocelot_vcap_policer_del(struct ocelot *ocelot, u32 pol_ix);
1110
1111 #if IS_ENABLED(CONFIG_BRIDGE_MRP)
1112 int ocelot_mrp_add(struct ocelot *ocelot, int port,
1113 const struct switchdev_obj_mrp *mrp);
1114 int ocelot_mrp_del(struct ocelot *ocelot, int port,
1115 const struct switchdev_obj_mrp *mrp);
1116 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1117 const struct switchdev_obj_ring_role_mrp *mrp);
1118 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1119 const struct switchdev_obj_ring_role_mrp *mrp);
1120 #else
ocelot_mrp_add(struct ocelot * ocelot,int port,const struct switchdev_obj_mrp * mrp)1121 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port,
1122 const struct switchdev_obj_mrp *mrp)
1123 {
1124 return -EOPNOTSUPP;
1125 }
1126
ocelot_mrp_del(struct ocelot * ocelot,int port,const struct switchdev_obj_mrp * mrp)1127 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port,
1128 const struct switchdev_obj_mrp *mrp)
1129 {
1130 return -EOPNOTSUPP;
1131 }
1132
1133 static inline int
ocelot_mrp_add_ring_role(struct ocelot * ocelot,int port,const struct switchdev_obj_ring_role_mrp * mrp)1134 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1135 const struct switchdev_obj_ring_role_mrp *mrp)
1136 {
1137 return -EOPNOTSUPP;
1138 }
1139
1140 static inline int
ocelot_mrp_del_ring_role(struct ocelot * ocelot,int port,const struct switchdev_obj_ring_role_mrp * mrp)1141 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1142 const struct switchdev_obj_ring_role_mrp *mrp)
1143 {
1144 return -EOPNOTSUPP;
1145 }
1146 #endif
1147
1148 #endif
1149