1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * QLogic iSCSI HBA Driver
4  * Copyright (c)  2003-2013 QLogic Corporation
5  */
6 
7 #ifndef __QL483XX_H
8 #define __QL483XX_H
9 
10 /* Indirectly Mapped Registers */
11 #define QLA83XX_FLASH_SPI_STATUS	0x2808E010
12 #define QLA83XX_FLASH_SPI_CONTROL	0x2808E014
13 #define QLA83XX_FLASH_STATUS		0x42100004
14 #define QLA83XX_FLASH_CONTROL		0x42110004
15 #define QLA83XX_FLASH_ADDR		0x42110008
16 #define QLA83XX_FLASH_WRDATA		0x4211000C
17 #define QLA83XX_FLASH_RDDATA		0x42110018
18 #define QLA83XX_FLASH_DIRECT_WINDOW	0x42110030
19 #define QLA83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
20 
21 /* Directly Mapped Registers in 83xx register table */
22 
23 /* Flash access regs */
24 #define QLA83XX_FLASH_LOCK		0x3850
25 #define QLA83XX_FLASH_UNLOCK		0x3854
26 #define QLA83XX_FLASH_LOCK_ID		0x3500
27 
28 /* Driver Lock regs */
29 #define QLA83XX_DRV_LOCK		0x3868
30 #define QLA83XX_DRV_UNLOCK		0x386C
31 #define QLA83XX_DRV_LOCK_ID		0x3504
32 #define QLA83XX_DRV_LOCKRECOVERY	0x379C
33 
34 /* IDC version */
35 #define QLA83XX_IDC_VER_MAJ_VALUE       0x1
36 #define QLA83XX_IDC_VER_MIN_VALUE       0x0
37 
38 /* IDC Registers : Driver Coexistence Defines */
39 #define QLA83XX_CRB_IDC_VER_MAJOR	0x3780
40 #define QLA83XX_CRB_IDC_VER_MINOR	0x3798
41 #define QLA83XX_IDC_DRV_CTRL		0x3790
42 #define QLA83XX_IDC_DRV_AUDIT		0x3794
43 #define QLA83XX_SRE_SHIM_CONTROL	0x0D200284
44 #define QLA83XX_PORT0_RXB_PAUSE_THRS	0x0B2003A4
45 #define QLA83XX_PORT1_RXB_PAUSE_THRS	0x0B2013A4
46 #define QLA83XX_PORT0_RXB_TC_MAX_CELL	0x0B200388
47 #define QLA83XX_PORT1_RXB_TC_MAX_CELL	0x0B201388
48 #define QLA83XX_PORT0_RXB_TC_STATS	0x0B20039C
49 #define QLA83XX_PORT1_RXB_TC_STATS	0x0B20139C
50 #define QLA83XX_PORT2_IFB_PAUSE_THRS	0x0B200704
51 #define QLA83XX_PORT3_IFB_PAUSE_THRS	0x0B201704
52 
53 /* set value to pause threshold value */
54 #define QLA83XX_SET_PAUSE_VAL		0x0
55 #define QLA83XX_SET_TC_MAX_CELL_VAL	0x03FF03FF
56 
57 #define QLA83XX_RESET_CONTROL		0x28084E50
58 #define QLA83XX_RESET_REG		0x28084E60
59 #define QLA83XX_RESET_PORT0		0x28084E70
60 #define QLA83XX_RESET_PORT1		0x28084E80
61 #define QLA83XX_RESET_PORT2		0x28084E90
62 #define QLA83XX_RESET_PORT3		0x28084EA0
63 #define QLA83XX_RESET_SRE_SHIM		0x28084EB0
64 #define QLA83XX_RESET_EPG_SHIM		0x28084EC0
65 #define QLA83XX_RESET_ETHER_PCS		0x28084ED0
66 
67 /* qla_83xx_reg_tbl registers */
68 #define QLA83XX_PEG_HALT_STATUS1	0x34A8
69 #define QLA83XX_PEG_HALT_STATUS2	0x34AC
70 #define QLA83XX_PEG_ALIVE_COUNTER	0x34B0 /* FW_HEARTBEAT */
71 #define QLA83XX_FW_CAPABILITIES		0x3528
72 #define QLA83XX_CRB_DRV_ACTIVE		0x3788 /* IDC_DRV_PRESENCE */
73 #define QLA83XX_CRB_DEV_STATE		0x3784 /* IDC_DEV_STATE */
74 #define QLA83XX_CRB_DRV_STATE		0x378C /* IDC_DRV_ACK */
75 #define QLA83XX_CRB_DRV_SCRATCH		0x3548
76 #define QLA83XX_CRB_DEV_PART_INFO1	0x37E0
77 #define QLA83XX_CRB_DEV_PART_INFO2	0x37E4
78 
79 #define QLA83XX_FW_VER_MAJOR		0x3550
80 #define QLA83XX_FW_VER_MINOR		0x3554
81 #define QLA83XX_FW_VER_SUB		0x3558
82 #define QLA83XX_NPAR_STATE		0x359C
83 #define QLA83XX_FW_IMAGE_VALID		0x35FC
84 #define QLA83XX_CMDPEG_STATE		0x3650
85 #define QLA83XX_ASIC_TEMP		0x37B4
86 #define QLA83XX_FW_API			0x356C
87 #define QLA83XX_DRV_OP_MODE		0x3570
88 
89 #define QLA83XX_CRB_WIN_BASE		0x3800
90 #define QLA83XX_CRB_WIN_FUNC(f)		(QLA83XX_CRB_WIN_BASE+((f)*4))
91 #define QLA83XX_SEM_LOCK_BASE		0x3840
92 #define QLA83XX_SEM_UNLOCK_BASE		0x3844
93 #define QLA83XX_SEM_LOCK_FUNC(f)	(QLA83XX_SEM_LOCK_BASE+((f)*8))
94 #define QLA83XX_SEM_UNLOCK_FUNC(f)	(QLA83XX_SEM_UNLOCK_BASE+((f)*8))
95 #define QLA83XX_LINK_STATE(f)		(0x3698+((f) > 7 ? 4 : 0))
96 #define QLA83XX_LINK_SPEED(f)		(0x36E0+(((f) >> 2) * 4))
97 #define QLA83XX_MAX_LINK_SPEED(f)       (0x36F0+(((f) / 4) * 4))
98 #define QLA83XX_LINK_SPEED_FACTOR	10
99 
100 /* FLASH API Defines */
101 #define QLA83xx_FLASH_MAX_WAIT_USEC	100
102 #define QLA83XX_FLASH_LOCK_TIMEOUT	10000
103 #define QLA83XX_FLASH_SECTOR_SIZE	65536
104 #define QLA83XX_DRV_LOCK_TIMEOUT	2000
105 #define QLA83XX_FLASH_SECTOR_ERASE_CMD	0xdeadbeef
106 #define QLA83XX_FLASH_WRITE_CMD		0xdacdacda
107 #define QLA83XX_FLASH_BUFFER_WRITE_CMD	0xcadcadca
108 #define QLA83XX_FLASH_READ_RETRY_COUNT	2000
109 #define QLA83XX_FLASH_STATUS_READY	0x6
110 #define QLA83XX_FLASH_BUFFER_WRITE_MIN	2
111 #define QLA83XX_FLASH_BUFFER_WRITE_MAX	64
112 #define QLA83XX_FLASH_STATUS_REG_POLL_DELAY 1
113 #define QLA83XX_ERASE_MODE		1
114 #define QLA83XX_WRITE_MODE		2
115 #define QLA83XX_DWORD_WRITE_MODE	3
116 
117 #define QLA83XX_GLOBAL_RESET		0x38CC
118 #define QLA83XX_WILDCARD		0x38F0
119 #define QLA83XX_INFORMANT		0x38FC
120 #define QLA83XX_HOST_MBX_CTRL		0x3038
121 #define QLA83XX_FW_MBX_CTRL		0x303C
122 #define QLA83XX_BOOTLOADER_ADDR		0x355C
123 #define QLA83XX_BOOTLOADER_SIZE		0x3560
124 #define QLA83XX_FW_IMAGE_ADDR		0x3564
125 #define QLA83XX_MBX_INTR_ENABLE		0x1000
126 #define QLA83XX_MBX_INTR_MASK		0x1200
127 
128 /* IDC Control Register bit defines */
129 #define DONTRESET_BIT0		0x1
130 #define GRACEFUL_RESET_BIT1	0x2
131 
132 #define QLA83XX_HALT_STATUS_INFORMATIONAL	(0x1 << 29)
133 #define QLA83XX_HALT_STATUS_FW_RESET		(0x2 << 29)
134 #define QLA83XX_HALT_STATUS_UNRECOVERABLE	(0x4 << 29)
135 
136 /* Firmware image definitions */
137 #define QLA83XX_BOOTLOADER_FLASH_ADDR	0x10000
138 #define QLA83XX_BOOT_FROM_FLASH		0
139 
140 #define QLA83XX_IDC_PARAM_ADDR		0x3e8020
141 /* Reset template definitions */
142 #define QLA83XX_MAX_RESET_SEQ_ENTRIES	16
143 #define QLA83XX_RESTART_TEMPLATE_SIZE	0x2000
144 #define QLA83XX_RESET_TEMPLATE_ADDR	0x4F0000
145 #define QLA83XX_RESET_SEQ_VERSION	0x0101
146 
147 /* Reset template entry opcodes */
148 #define OPCODE_NOP			0x0000
149 #define OPCODE_WRITE_LIST		0x0001
150 #define OPCODE_READ_WRITE_LIST		0x0002
151 #define OPCODE_POLL_LIST		0x0004
152 #define OPCODE_POLL_WRITE_LIST		0x0008
153 #define OPCODE_READ_MODIFY_WRITE	0x0010
154 #define OPCODE_SEQ_PAUSE		0x0020
155 #define OPCODE_SEQ_END			0x0040
156 #define OPCODE_TMPL_END			0x0080
157 #define OPCODE_POLL_READ_LIST		0x0100
158 
159 /* Template Header */
160 #define RESET_TMPLT_HDR_SIGNATURE	0xCAFE
161 struct qla4_83xx_reset_template_hdr {
162 	__le16	version;
163 	__le16	signature;
164 	__le16	size;
165 	__le16	entries;
166 	__le16	hdr_size;
167 	__le16	checksum;
168 	__le16	init_seq_offset;
169 	__le16	start_seq_offset;
170 } __packed;
171 
172 /* Common Entry Header. */
173 struct qla4_83xx_reset_entry_hdr {
174 	__le16 cmd;
175 	__le16 size;
176 	__le16 count;
177 	__le16 delay;
178 } __packed;
179 
180 /* Generic poll entry type. */
181 struct qla4_83xx_poll {
182 	__le32  test_mask;
183 	__le32  test_value;
184 } __packed;
185 
186 /* Read modify write entry type. */
187 struct qla4_83xx_rmw {
188 	__le32  test_mask;
189 	__le32  xor_value;
190 	__le32  or_value;
191 	uint8_t shl;
192 	uint8_t shr;
193 	uint8_t index_a;
194 	uint8_t rsvd;
195 } __packed;
196 
197 /* Generic Entry Item with 2 DWords. */
198 struct qla4_83xx_entry {
199 	__le32 arg1;
200 	__le32 arg2;
201 } __packed;
202 
203 /* Generic Entry Item with 4 DWords.*/
204 struct qla4_83xx_quad_entry {
205 	__le32 dr_addr;
206 	__le32 dr_value;
207 	__le32 ar_addr;
208 	__le32 ar_value;
209 } __packed;
210 
211 struct qla4_83xx_reset_template {
212 	int seq_index;
213 	int seq_error;
214 	int array_index;
215 	uint32_t array[QLA83XX_MAX_RESET_SEQ_ENTRIES];
216 	uint8_t *buff;
217 	uint8_t *stop_offset;
218 	uint8_t *start_offset;
219 	uint8_t *init_offset;
220 	struct qla4_83xx_reset_template_hdr *hdr;
221 	uint8_t seq_end;
222 	uint8_t template_end;
223 };
224 
225 /* POLLRD Entry */
226 struct qla83xx_minidump_entry_pollrd {
227 	struct qla8xxx_minidump_entry_hdr h;
228 	uint32_t select_addr;
229 	uint32_t read_addr;
230 	uint32_t select_value;
231 	uint16_t select_value_stride;
232 	uint16_t op_count;
233 	uint32_t poll_wait;
234 	uint32_t poll_mask;
235 	uint32_t data_size;
236 	uint32_t rsvd_1;
237 };
238 
239 struct qla8044_minidump_entry_rddfe {
240 	struct qla8xxx_minidump_entry_hdr h;
241 	uint32_t addr_1;
242 	uint32_t value;
243 	uint8_t stride;
244 	uint8_t stride2;
245 	uint16_t count;
246 	uint32_t poll;
247 	uint32_t mask;
248 	uint32_t modify_mask;
249 	uint32_t data_size;
250 	uint32_t rsvd;
251 
252 } __packed;
253 
254 struct qla8044_minidump_entry_rdmdio {
255 	struct qla8xxx_minidump_entry_hdr h;
256 
257 	uint32_t addr_1;
258 	uint32_t addr_2;
259 	uint32_t value_1;
260 	uint8_t stride_1;
261 	uint8_t stride_2;
262 	uint16_t count;
263 	uint32_t poll;
264 	uint32_t mask;
265 	uint32_t value_2;
266 	uint32_t data_size;
267 
268 } __packed;
269 
270 struct qla8044_minidump_entry_pollwr {
271 	struct qla8xxx_minidump_entry_hdr h;
272 	uint32_t addr_1;
273 	uint32_t addr_2;
274 	uint32_t value_1;
275 	uint32_t value_2;
276 	uint32_t poll;
277 	uint32_t mask;
278 	uint32_t data_size;
279 	uint32_t rsvd;
280 
281 } __packed;
282 
283 /* RDMUX2 Entry */
284 struct qla83xx_minidump_entry_rdmux2 {
285 	struct qla8xxx_minidump_entry_hdr h;
286 	uint32_t select_addr_1;
287 	uint32_t select_addr_2;
288 	uint32_t select_value_1;
289 	uint32_t select_value_2;
290 	uint32_t op_count;
291 	uint32_t select_value_mask;
292 	uint32_t read_addr;
293 	uint8_t select_value_stride;
294 	uint8_t data_size;
295 	uint8_t rsvd[2];
296 };
297 
298 /* POLLRDMWR Entry */
299 struct qla83xx_minidump_entry_pollrdmwr {
300 	struct qla8xxx_minidump_entry_hdr h;
301 	uint32_t addr_1;
302 	uint32_t addr_2;
303 	uint32_t value_1;
304 	uint32_t value_2;
305 	uint32_t poll_wait;
306 	uint32_t poll_mask;
307 	uint32_t modify_mask;
308 	uint32_t data_size;
309 };
310 
311 /* IDC additional information */
312 struct qla4_83xx_idc_information {
313 	uint32_t request_desc;  /* IDC request descriptor */
314 	uint32_t info1; /* IDC additional info */
315 	uint32_t info2; /* IDC additional info */
316 	uint32_t info3; /* IDC additional info */
317 };
318 
319 #define QLA83XX_PEX_DMA_ENGINE_INDEX		8
320 #define QLA83XX_PEX_DMA_BASE_ADDRESS		0x77320000
321 #define QLA83XX_PEX_DMA_NUM_OFFSET		0x10000
322 #define QLA83XX_PEX_DMA_CMD_ADDR_LOW		0x0
323 #define QLA83XX_PEX_DMA_CMD_ADDR_HIGH		0x04
324 #define QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL	0x08
325 
326 #define QLA83XX_PEX_DMA_READ_SIZE	(16 * 1024)
327 #define QLA83XX_PEX_DMA_MAX_WAIT	(100 * 100) /* Max wait of 100 msecs */
328 
329 /* Read Memory: For Pex-DMA */
330 struct qla4_83xx_minidump_entry_rdmem_pex_dma {
331 	struct qla8xxx_minidump_entry_hdr h;
332 	uint32_t desc_card_addr;
333 	uint16_t dma_desc_cmd;
334 	uint8_t rsvd[2];
335 	uint32_t start_dma_cmd;
336 	uint8_t rsvd2[12];
337 	uint32_t read_addr;
338 	uint32_t read_data_size;
339 };
340 
341 struct qla4_83xx_pex_dma_descriptor {
342 	struct {
343 		uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
344 		uint8_t rsvd[2];
345 		uint16_t dma_desc_cmd;
346 	} cmd;
347 	uint64_t src_addr;
348 	uint64_t dma_bus_addr; /* 0-3: desc-cmd, 4-7: pci-func,
349 				* 8-15: desc-cmd */
350 	uint8_t rsvd[24];
351 } __packed;
352 
353 #endif
354