1 /*
2  * linux/drivers/video/neofb.h -- NeoMagic Framebuffer Driver
3  *
4  * Copyright (c) 2001  Denis Oliver Kropp <dok@convergence.de>
5  *
6  * This file is subject to the terms and conditions of the GNU General
7  * Public License.  See the file COPYING in the main directory of this
8  * archive for more details.
9  */
10 
11 
12 #ifdef NEOFB_DEBUG
13 # define DBG(x)		printk (KERN_DEBUG "neofb: %s\n", (x));
14 #else
15 # define DBG(x)
16 #endif
17 
18 
19 #define PCI_CHIP_NM2070 0x0001
20 #define PCI_CHIP_NM2090 0x0002
21 #define PCI_CHIP_NM2093 0x0003
22 #define PCI_CHIP_NM2097 0x0083
23 #define PCI_CHIP_NM2160 0x0004
24 #define PCI_CHIP_NM2200 0x0005
25 #define PCI_CHIP_NM2230 0x0025
26 #define PCI_CHIP_NM2360 0x0006
27 #define PCI_CHIP_NM2380 0x0016
28 
29 
30 struct xtimings {
31   unsigned int pixclock;
32   unsigned int HDisplay;
33   unsigned int HSyncStart;
34   unsigned int HSyncEnd;
35   unsigned int HTotal;
36   unsigned int VDisplay;
37   unsigned int VSyncStart;
38   unsigned int VSyncEnd;
39   unsigned int VTotal;
40   unsigned int sync;
41   int	       dblscan;
42   int	       interlaced;
43 };
44 
45 
46 /* --------------------------------------------------------------------- */
47 
48 typedef volatile struct {
49   __u32 bltStat;
50   __u32 bltCntl;
51   __u32 xpColor;
52   __u32 fgColor;
53   __u32 bgColor;
54   __u32 pitch;
55   __u32 clipLT;
56   __u32 clipRB;
57   __u32 srcBitOffset;
58   __u32 srcStart;
59   __u32 reserved0;
60   __u32 dstStart;
61   __u32 xyExt;
62 
63   __u32 reserved1[19];
64 
65   __u32 pageCntl;
66   __u32 pageBase;
67   __u32 postBase;
68   __u32 postPtr;
69   __u32 dataPtr;
70 } Neo2200;
71 
72 #define NR_PALETTE	256
73 
74 #define MMIO_SIZE 0x200000
75 
76 #define NEO_EXT_CR_MAX 0x85
77 #define NEO_EXT_GR_MAX 0xC7
78 
79 struct neofb_par {
80 
81   int depth;
82 
83   unsigned char MiscOutReg;     /* Misc */
84   unsigned char CRTC[25];       /* Crtc Controller */
85   unsigned char Sequencer[5];   /* Video Sequencer */
86   unsigned char Graphics[9];    /* Video Graphics */
87   unsigned char Attribute[21];  /* Video Atribute */
88 
89   unsigned char GeneralLockReg;
90   unsigned char ExtCRTDispAddr;
91   unsigned char ExtCRTOffset;
92   unsigned char SysIfaceCntl1;
93   unsigned char SysIfaceCntl2;
94   unsigned char ExtColorModeSelect;
95   unsigned char biosMode;
96 
97   unsigned char PanelDispCntlReg1;
98   unsigned char PanelDispCntlReg2;
99   unsigned char PanelDispCntlReg3;
100   unsigned char PanelVertCenterReg1;
101   unsigned char PanelVertCenterReg2;
102   unsigned char PanelVertCenterReg3;
103   unsigned char PanelVertCenterReg4;
104   unsigned char PanelVertCenterReg5;
105   unsigned char PanelHorizCenterReg1;
106   unsigned char PanelHorizCenterReg2;
107   unsigned char PanelHorizCenterReg3;
108   unsigned char PanelHorizCenterReg4;
109   unsigned char PanelHorizCenterReg5;
110 
111   int           ProgramVCLK;
112   unsigned char VCLK3NumeratorLow;
113   unsigned char VCLK3NumeratorHigh;
114   unsigned char VCLK3Denominator;
115   unsigned char VerticalExt;
116 };
117 
118 struct neofb_info {
119 
120   struct fb_info  fb;
121   struct display_switch	*dispsw;
122 
123   struct pci_dev *pcidev;
124 
125   int   currcon;
126 
127   int   accel;
128   char *name;
129 
130   struct {
131     u8    *vbase;
132     u32    pbase;
133     u32    len;
134 #ifdef CONFIG_MTRR
135     int    mtrr;
136 #endif
137   } video;
138 
139   struct {
140     u8    *vbase;
141     u32    pbase;
142     u32    len;
143   } mmio;
144 
145   Neo2200 *neo2200;
146 
147   /* Panels size */
148   int NeoPanelWidth;
149   int NeoPanelHeight;
150 
151   int maxClock;
152 
153   int pci_burst;
154   int lcd_stretch;
155   int internal_display;
156   int external_display;
157 
158   struct {
159     u16 red, green, blue, transp;
160   } palette[NR_PALETTE];
161 };
162 
163 
164 typedef struct {
165     int x_res;
166     int y_res;
167     int mode;
168 } biosMode;
169 
170 
171 /* vga IO functions */
VGArCR(u8 index)172 static inline u8 VGArCR (u8 index)
173 {
174   outb (index, 0x3d4);
175   return inb (0x3d5);
176 }
177 
VGAwCR(u8 index,u8 val)178 static inline void VGAwCR (u8 index, u8 val)
179 {
180   outb (index, 0x3d4);
181   outb (val, 0x3d5);
182 }
183 
VGArGR(u8 index)184 static inline u8 VGArGR (u8 index)
185 {
186   outb (index, 0x3ce);
187   return inb (0x3cf);
188 }
189 
VGAwGR(u8 index,u8 val)190 static inline void VGAwGR (u8 index, u8 val)
191 {
192   outb (index, 0x3ce);
193   outb (val, 0x3cf);
194 }
195 
VGArSEQ(u8 index)196 static inline u8 VGArSEQ (u8 index)
197 {
198   outb (index, 0x3c4);
199   return inb (0x3c5);
200 }
201 
VGAwSEQ(u8 index,u8 val)202 static inline void VGAwSEQ (u8 index, u8 val)
203 {
204   outb (index, 0x3c4);
205   outb (val, 0x3c5);
206 }
207 
208 
209 static int paletteEnabled = 0;
210 
VGAenablePalette(void)211 static inline void VGAenablePalette (void)
212 {
213   u8 tmp;
214 
215   tmp = inb (0x3da);
216   outb (0x00, 0x3c0);
217   paletteEnabled = 1;
218 }
219 
VGAdisablePalette(void)220 static inline void VGAdisablePalette (void)
221 {
222   u8 tmp;
223 
224   tmp = inb (0x3da);
225   outb (0x20, 0x3c0);
226   paletteEnabled = 0;
227 }
228 
VGAwATTR(u8 index,u8 value)229 static inline void VGAwATTR (u8 index, u8 value)
230 {
231   u8 tmp;
232 
233   if (paletteEnabled)
234     index &= ~0x20;
235   else
236     index |= 0x20;
237 
238   tmp = inb (0x3da);
239   outb (index, 0x3c0);
240   outb (value, 0x3c0);
241 }
242 
VGAwMISC(u8 value)243 static inline void VGAwMISC (u8 value)
244 {
245   outb (value, 0x3c2);
246 }
247 
248 
249 #define NEO_BS0_BLT_BUSY        0x00000001
250 #define NEO_BS0_FIFO_AVAIL      0x00000002
251 #define NEO_BS0_FIFO_PEND       0x00000004
252 
253 #define NEO_BC0_DST_Y_DEC       0x00000001
254 #define NEO_BC0_X_DEC           0x00000002
255 #define NEO_BC0_SRC_TRANS       0x00000004
256 #define NEO_BC0_SRC_IS_FG       0x00000008
257 #define NEO_BC0_SRC_Y_DEC       0x00000010
258 #define NEO_BC0_FILL_PAT        0x00000020
259 #define NEO_BC0_SRC_MONO        0x00000040
260 #define NEO_BC0_SYS_TO_VID      0x00000080
261 
262 #define NEO_BC1_DEPTH8          0x00000100
263 #define NEO_BC1_DEPTH16         0x00000200
264 #define NEO_BC1_X_320           0x00000400
265 #define NEO_BC1_X_640           0x00000800
266 #define NEO_BC1_X_800           0x00000c00
267 #define NEO_BC1_X_1024          0x00001000
268 #define NEO_BC1_X_1152          0x00001400
269 #define NEO_BC1_X_1280          0x00001800
270 #define NEO_BC1_X_1600          0x00001c00
271 #define NEO_BC1_DST_TRANS       0x00002000
272 #define NEO_BC1_MSTR_BLT        0x00004000
273 #define NEO_BC1_FILTER_Z        0x00008000
274 
275 #define NEO_BC2_WR_TR_DST       0x00800000
276 
277 #define NEO_BC3_SRC_XY_ADDR     0x01000000
278 #define NEO_BC3_DST_XY_ADDR     0x02000000
279 #define NEO_BC3_CLIP_ON         0x04000000
280 #define NEO_BC3_FIFO_EN         0x08000000
281 #define NEO_BC3_BLT_ON_ADDR     0x10000000
282 #define NEO_BC3_SKIP_MAPPING    0x80000000
283 
284 #define NEO_MODE1_DEPTH8        0x0100
285 #define NEO_MODE1_DEPTH16       0x0200
286 #define NEO_MODE1_DEPTH24       0x0300
287 #define NEO_MODE1_X_320         0x0400
288 #define NEO_MODE1_X_640         0x0800
289 #define NEO_MODE1_X_800         0x0c00
290 #define NEO_MODE1_X_1024        0x1000
291 #define NEO_MODE1_X_1152        0x1400
292 #define NEO_MODE1_X_1280        0x1800
293 #define NEO_MODE1_X_1600        0x1c00
294 #define NEO_MODE1_BLT_ON_ADDR   0x2000
295