1 /* 2 * OMAP2/3/4 powerdomain control 3 * 4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc. 5 * Copyright (C) 2007-2011 Nokia Corporation 6 * 7 * Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * XXX This should be moved to the mach-omap2/ directory at the earliest 14 * opportunity. 15 */ 16 17 #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H 18 #define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H 19 20 #include <linux/types.h> 21 #include <linux/list.h> 22 23 #include <linux/atomic.h> 24 25 #include <plat/cpu.h> 26 27 /* Powerdomain basic power states */ 28 #define PWRDM_POWER_OFF 0x0 29 #define PWRDM_POWER_RET 0x1 30 #define PWRDM_POWER_INACTIVE 0x2 31 #define PWRDM_POWER_ON 0x3 32 33 #define PWRDM_MAX_PWRSTS 4 34 35 /* Powerdomain allowable state bitfields */ 36 #define PWRSTS_ON (1 << PWRDM_POWER_ON) 37 #define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE) 38 #define PWRSTS_RET (1 << PWRDM_POWER_RET) 39 #define PWRSTS_OFF (1 << PWRDM_POWER_OFF) 40 41 #define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) 42 #define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET) 43 #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) 44 #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON) 45 46 47 /* Powerdomain flags */ 48 #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ 49 #define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits 50 * in MEM bank 1 position. This is 51 * true for OMAP3430 52 */ 53 #define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* 54 * support to transition from a 55 * sleep state to a lower sleep 56 * state without waking up the 57 * powerdomain 58 */ 59 60 /* 61 * Number of memory banks that are power-controllable. On OMAP4430, the 62 * maximum is 5. 63 */ 64 #define PWRDM_MAX_MEM_BANKS 5 65 66 /* 67 * Maximum number of clockdomains that can be associated with a powerdomain. 68 * CORE powerdomain on OMAP4 is the worst case 69 */ 70 #define PWRDM_MAX_CLKDMS 9 71 72 /* XXX A completely arbitrary number. What is reasonable here? */ 73 #define PWRDM_TRANSITION_BAILOUT 100000 74 75 struct clockdomain; 76 struct powerdomain; 77 78 /** 79 * struct powerdomain - OMAP powerdomain 80 * @name: Powerdomain name 81 * @omap_chip: represents the OMAP chip types containing this pwrdm 82 * @prcm_offs: the address offset from CM_BASE/PRM_BASE 83 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs 84 * @pwrsts: Possible powerdomain power states 85 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION 86 * @flags: Powerdomain flags 87 * @banks: Number of software-controllable memory banks in this powerdomain 88 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION 89 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON 90 * @pwrdm_clkdms: Clockdomains in this powerdomain 91 * @node: list_head linking all powerdomains 92 * @state: 93 * @state_counter: 94 * @timer: 95 * @state_timer: 96 * 97 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. 98 */ 99 struct powerdomain { 100 const char *name; 101 const struct omap_chip_id omap_chip; 102 const s16 prcm_offs; 103 const u8 pwrsts; 104 const u8 pwrsts_logic_ret; 105 const u8 flags; 106 const u8 banks; 107 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; 108 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; 109 const u8 prcm_partition; 110 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; 111 struct list_head node; 112 int state; 113 unsigned state_counter[PWRDM_MAX_PWRSTS]; 114 unsigned ret_logic_off_counter; 115 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; 116 117 #ifdef CONFIG_PM_DEBUG 118 s64 timer; 119 s64 state_timer[PWRDM_MAX_PWRSTS]; 120 #endif 121 }; 122 123 /** 124 * struct pwrdm_ops - Arch specific function implementations 125 * @pwrdm_set_next_pwrst: Set the target power state for a pd 126 * @pwrdm_read_next_pwrst: Read the target power state set for a pd 127 * @pwrdm_read_pwrst: Read the current power state of a pd 128 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd 129 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd 130 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd 131 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd 132 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd 133 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd 134 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd 135 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd 136 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd 137 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd 138 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd 139 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd 140 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd 141 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep 142 * @pwrdm_wait_transition: Wait for a pd state transition to complete 143 */ 144 struct pwrdm_ops { 145 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); 146 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); 147 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); 148 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); 149 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); 150 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 151 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 152 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); 153 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); 154 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); 155 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); 156 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); 157 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); 158 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); 159 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); 160 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); 161 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); 162 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); 163 }; 164 165 void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); 166 167 struct powerdomain *pwrdm_lookup(const char *name); 168 169 int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), 170 void *user); 171 int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), 172 void *user); 173 174 int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); 175 int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); 176 int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, 177 int (*fn)(struct powerdomain *pwrdm, 178 struct clockdomain *clkdm)); 179 180 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); 181 182 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); 183 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); 184 int pwrdm_read_pwrst(struct powerdomain *pwrdm); 185 int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); 186 int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); 187 188 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); 189 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 190 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); 191 192 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); 193 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); 194 int pwrdm_read_logic_retst(struct powerdomain *pwrdm); 195 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); 196 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); 197 int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); 198 199 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); 200 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); 201 bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); 202 203 int pwrdm_wait_transition(struct powerdomain *pwrdm); 204 205 int pwrdm_state_switch(struct powerdomain *pwrdm); 206 int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); 207 int pwrdm_pre_transition(void); 208 int pwrdm_post_transition(void); 209 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); 210 u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm); 211 bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); 212 213 extern void omap2xxx_powerdomains_init(void); 214 extern void omap3xxx_powerdomains_init(void); 215 extern void omap44xx_powerdomains_init(void); 216 217 extern struct pwrdm_ops omap2_pwrdm_operations; 218 extern struct pwrdm_ops omap3_pwrdm_operations; 219 extern struct pwrdm_ops omap4_pwrdm_operations; 220 221 /* Common Internal functions used across OMAP rev's */ 222 extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); 223 extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); 224 extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); 225 226 extern struct powerdomain wkup_omap2_pwrdm; 227 extern struct powerdomain gfx_omap2_pwrdm; 228 229 230 #endif 231