1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4  * Author: Joerg Roedel <jroedel@suse.de>
5  *         Leo Duran <leo.duran@amd.com>
6  */
7 
8 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
9 #define _ASM_X86_AMD_IOMMU_TYPES_H
10 
11 #include <linux/types.h>
12 #include <linux/mutex.h>
13 #include <linux/msi.h>
14 #include <linux/list.h>
15 #include <linux/spinlock.h>
16 #include <linux/pci.h>
17 #include <linux/irqreturn.h>
18 #include <linux/io-pgtable.h>
19 
20 /*
21  * Maximum number of IOMMUs supported
22  */
23 #define MAX_IOMMUS	32
24 
25 /*
26  * some size calculation constants
27  */
28 #define DEV_TABLE_ENTRY_SIZE		32
29 #define ALIAS_TABLE_ENTRY_SIZE		2
30 #define RLOOKUP_TABLE_ENTRY_SIZE	(sizeof(void *))
31 
32 /* Capability offsets used by the driver */
33 #define MMIO_CAP_HDR_OFFSET	0x00
34 #define MMIO_RANGE_OFFSET	0x0c
35 #define MMIO_MISC_OFFSET	0x10
36 
37 /* Masks, shifts and macros to parse the device range capability */
38 #define MMIO_RANGE_LD_MASK	0xff000000
39 #define MMIO_RANGE_FD_MASK	0x00ff0000
40 #define MMIO_RANGE_BUS_MASK	0x0000ff00
41 #define MMIO_RANGE_LD_SHIFT	24
42 #define MMIO_RANGE_FD_SHIFT	16
43 #define MMIO_RANGE_BUS_SHIFT	8
44 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
45 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
46 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
47 #define MMIO_MSI_NUM(x)	((x) & 0x1f)
48 
49 /* Flag masks for the AMD IOMMU exclusion range */
50 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
51 #define MMIO_EXCL_ALLOW_MASK  0x02ULL
52 
53 /* Used offsets into the MMIO space */
54 #define MMIO_DEV_TABLE_OFFSET   0x0000
55 #define MMIO_CMD_BUF_OFFSET     0x0008
56 #define MMIO_EVT_BUF_OFFSET     0x0010
57 #define MMIO_CONTROL_OFFSET     0x0018
58 #define MMIO_EXCL_BASE_OFFSET   0x0020
59 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
60 #define MMIO_EXT_FEATURES	0x0030
61 #define MMIO_PPR_LOG_OFFSET	0x0038
62 #define MMIO_GA_LOG_BASE_OFFSET	0x00e0
63 #define MMIO_GA_LOG_TAIL_OFFSET	0x00e8
64 #define MMIO_MSI_ADDR_LO_OFFSET	0x015C
65 #define MMIO_MSI_ADDR_HI_OFFSET	0x0160
66 #define MMIO_MSI_DATA_OFFSET	0x0164
67 #define MMIO_INTCAPXT_EVT_OFFSET	0x0170
68 #define MMIO_INTCAPXT_PPR_OFFSET	0x0178
69 #define MMIO_INTCAPXT_GALOG_OFFSET	0x0180
70 #define MMIO_EXT_FEATURES2	0x01A0
71 #define MMIO_CMD_HEAD_OFFSET	0x2000
72 #define MMIO_CMD_TAIL_OFFSET	0x2008
73 #define MMIO_EVT_HEAD_OFFSET	0x2010
74 #define MMIO_EVT_TAIL_OFFSET	0x2018
75 #define MMIO_STATUS_OFFSET	0x2020
76 #define MMIO_PPR_HEAD_OFFSET	0x2030
77 #define MMIO_PPR_TAIL_OFFSET	0x2038
78 #define MMIO_GA_HEAD_OFFSET	0x2040
79 #define MMIO_GA_TAIL_OFFSET	0x2048
80 #define MMIO_CNTR_CONF_OFFSET	0x4000
81 #define MMIO_CNTR_REG_OFFSET	0x40000
82 #define MMIO_REG_END_OFFSET	0x80000
83 
84 
85 
86 /* Extended Feature Bits */
87 #define FEATURE_PREFETCH	(1ULL<<0)
88 #define FEATURE_PPR		(1ULL<<1)
89 #define FEATURE_X2APIC		(1ULL<<2)
90 #define FEATURE_NX		(1ULL<<3)
91 #define FEATURE_GT		(1ULL<<4)
92 #define FEATURE_IA		(1ULL<<6)
93 #define FEATURE_GA		(1ULL<<7)
94 #define FEATURE_HE		(1ULL<<8)
95 #define FEATURE_PC		(1ULL<<9)
96 #define FEATURE_GAM_VAPIC	(1ULL<<21)
97 #define FEATURE_GIOSUP		(1ULL<<48)
98 #define FEATURE_EPHSUP		(1ULL<<50)
99 #define FEATURE_SNP		(1ULL<<63)
100 
101 #define FEATURE_PASID_SHIFT	32
102 #define FEATURE_PASID_MASK	(0x1fULL << FEATURE_PASID_SHIFT)
103 
104 #define FEATURE_GLXVAL_SHIFT	14
105 #define FEATURE_GLXVAL_MASK	(0x03ULL << FEATURE_GLXVAL_SHIFT)
106 
107 /* Extended Feature 2 Bits */
108 #define FEATURE_SNPAVICSUP_SHIFT	5
109 #define FEATURE_SNPAVICSUP_MASK		(0x07ULL << FEATURE_SNPAVICSUP_SHIFT)
110 #define FEATURE_SNPAVICSUP_GAM(x) \
111 	((x & FEATURE_SNPAVICSUP_MASK) >> FEATURE_SNPAVICSUP_SHIFT == 0x1)
112 
113 /* Note:
114  * The current driver only support 16-bit PASID.
115  * Currently, hardware only implement upto 16-bit PASID
116  * even though the spec says it could have upto 20 bits.
117  */
118 #define PASID_MASK		0x0000ffff
119 
120 /* MMIO status bits */
121 #define MMIO_STATUS_EVT_OVERFLOW_INT_MASK	(1 << 0)
122 #define MMIO_STATUS_EVT_INT_MASK	(1 << 1)
123 #define MMIO_STATUS_COM_WAIT_INT_MASK	(1 << 2)
124 #define MMIO_STATUS_PPR_INT_MASK	(1 << 6)
125 #define MMIO_STATUS_GALOG_RUN_MASK	(1 << 8)
126 #define MMIO_STATUS_GALOG_OVERFLOW_MASK	(1 << 9)
127 #define MMIO_STATUS_GALOG_INT_MASK	(1 << 10)
128 
129 /* event logging constants */
130 #define EVENT_ENTRY_SIZE	0x10
131 #define EVENT_TYPE_SHIFT	28
132 #define EVENT_TYPE_MASK		0xf
133 #define EVENT_TYPE_ILL_DEV	0x1
134 #define EVENT_TYPE_IO_FAULT	0x2
135 #define EVENT_TYPE_DEV_TAB_ERR	0x3
136 #define EVENT_TYPE_PAGE_TAB_ERR	0x4
137 #define EVENT_TYPE_ILL_CMD	0x5
138 #define EVENT_TYPE_CMD_HARD_ERR	0x6
139 #define EVENT_TYPE_IOTLB_INV_TO	0x7
140 #define EVENT_TYPE_INV_DEV_REQ	0x8
141 #define EVENT_TYPE_INV_PPR_REQ	0x9
142 #define EVENT_TYPE_RMP_FAULT	0xd
143 #define EVENT_TYPE_RMP_HW_ERR	0xe
144 #define EVENT_DEVID_MASK	0xffff
145 #define EVENT_DEVID_SHIFT	0
146 #define EVENT_DOMID_MASK_LO	0xffff
147 #define EVENT_DOMID_MASK_HI	0xf0000
148 #define EVENT_FLAGS_MASK	0xfff
149 #define EVENT_FLAGS_SHIFT	0x10
150 #define EVENT_FLAG_RW		0x020
151 #define EVENT_FLAG_I		0x008
152 
153 /* feature control bits */
154 #define CONTROL_IOMMU_EN	0
155 #define CONTROL_HT_TUN_EN	1
156 #define CONTROL_EVT_LOG_EN	2
157 #define CONTROL_EVT_INT_EN	3
158 #define CONTROL_COMWAIT_EN	4
159 #define CONTROL_INV_TIMEOUT	5
160 #define CONTROL_PASSPW_EN	8
161 #define CONTROL_RESPASSPW_EN	9
162 #define CONTROL_COHERENT_EN	10
163 #define CONTROL_ISOC_EN		11
164 #define CONTROL_CMDBUF_EN	12
165 #define CONTROL_PPRLOG_EN	13
166 #define CONTROL_PPRINT_EN	14
167 #define CONTROL_PPR_EN		15
168 #define CONTROL_GT_EN		16
169 #define CONTROL_GA_EN		17
170 #define CONTROL_GAM_EN		25
171 #define CONTROL_GALOG_EN	28
172 #define CONTROL_GAINT_EN	29
173 #define CONTROL_XT_EN		50
174 #define CONTROL_INTCAPXT_EN	51
175 #define CONTROL_SNPAVIC_EN	61
176 
177 #define CTRL_INV_TO_MASK	(7 << CONTROL_INV_TIMEOUT)
178 #define CTRL_INV_TO_NONE	0
179 #define CTRL_INV_TO_1MS		1
180 #define CTRL_INV_TO_10MS	2
181 #define CTRL_INV_TO_100MS	3
182 #define CTRL_INV_TO_1S		4
183 #define CTRL_INV_TO_10S		5
184 #define CTRL_INV_TO_100S	6
185 
186 /* command specific defines */
187 #define CMD_COMPL_WAIT          0x01
188 #define CMD_INV_DEV_ENTRY       0x02
189 #define CMD_INV_IOMMU_PAGES	0x03
190 #define CMD_INV_IOTLB_PAGES	0x04
191 #define CMD_INV_IRT		0x05
192 #define CMD_COMPLETE_PPR	0x07
193 #define CMD_INV_ALL		0x08
194 
195 #define CMD_COMPL_WAIT_STORE_MASK	0x01
196 #define CMD_COMPL_WAIT_INT_MASK		0x02
197 #define CMD_INV_IOMMU_PAGES_SIZE_MASK	0x01
198 #define CMD_INV_IOMMU_PAGES_PDE_MASK	0x02
199 #define CMD_INV_IOMMU_PAGES_GN_MASK	0x04
200 
201 #define PPR_STATUS_MASK			0xf
202 #define PPR_STATUS_SHIFT		12
203 
204 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS	0x7fffffffffffffffULL
205 
206 /* macros and definitions for device table entries */
207 #define DEV_ENTRY_VALID         0x00
208 #define DEV_ENTRY_TRANSLATION   0x01
209 #define DEV_ENTRY_PPR           0x34
210 #define DEV_ENTRY_IR            0x3d
211 #define DEV_ENTRY_IW            0x3e
212 #define DEV_ENTRY_NO_PAGE_FAULT	0x62
213 #define DEV_ENTRY_EX            0x67
214 #define DEV_ENTRY_SYSMGT1       0x68
215 #define DEV_ENTRY_SYSMGT2       0x69
216 #define DEV_ENTRY_IRQ_TBL_EN	0x80
217 #define DEV_ENTRY_INIT_PASS     0xb8
218 #define DEV_ENTRY_EINT_PASS     0xb9
219 #define DEV_ENTRY_NMI_PASS      0xba
220 #define DEV_ENTRY_LINT0_PASS    0xbe
221 #define DEV_ENTRY_LINT1_PASS    0xbf
222 #define DEV_ENTRY_MODE_MASK	0x07
223 #define DEV_ENTRY_MODE_SHIFT	0x09
224 
225 #define MAX_DEV_TABLE_ENTRIES	0xffff
226 
227 /* constants to configure the command buffer */
228 #define CMD_BUFFER_SIZE    8192
229 #define CMD_BUFFER_UNINITIALIZED 1
230 #define CMD_BUFFER_ENTRIES 512
231 #define MMIO_CMD_SIZE_SHIFT 56
232 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
233 
234 /* constants for event buffer handling */
235 #define EVT_BUFFER_SIZE		8192 /* 512 entries */
236 #define EVT_LEN_MASK		(0x9ULL << 56)
237 
238 /* Constants for PPR Log handling */
239 #define PPR_LOG_ENTRIES		512
240 #define PPR_LOG_SIZE_SHIFT	56
241 #define PPR_LOG_SIZE_512	(0x9ULL << PPR_LOG_SIZE_SHIFT)
242 #define PPR_ENTRY_SIZE		16
243 #define PPR_LOG_SIZE		(PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
244 
245 #define PPR_REQ_TYPE(x)		(((x) >> 60) & 0xfULL)
246 #define PPR_FLAGS(x)		(((x) >> 48) & 0xfffULL)
247 #define PPR_DEVID(x)		((x) & 0xffffULL)
248 #define PPR_TAG(x)		(((x) >> 32) & 0x3ffULL)
249 #define PPR_PASID1(x)		(((x) >> 16) & 0xffffULL)
250 #define PPR_PASID2(x)		(((x) >> 42) & 0xfULL)
251 #define PPR_PASID(x)		((PPR_PASID2(x) << 16) | PPR_PASID1(x))
252 
253 #define PPR_REQ_FAULT		0x01
254 
255 /* Constants for GA Log handling */
256 #define GA_LOG_ENTRIES		512
257 #define GA_LOG_SIZE_SHIFT	56
258 #define GA_LOG_SIZE_512		(0x8ULL << GA_LOG_SIZE_SHIFT)
259 #define GA_ENTRY_SIZE		8
260 #define GA_LOG_SIZE		(GA_ENTRY_SIZE * GA_LOG_ENTRIES)
261 
262 #define GA_TAG(x)		(u32)(x & 0xffffffffULL)
263 #define GA_DEVID(x)		(u16)(((x) >> 32) & 0xffffULL)
264 #define GA_REQ_TYPE(x)		(((x) >> 60) & 0xfULL)
265 
266 #define GA_GUEST_NR		0x1
267 
268 #define IOMMU_IN_ADDR_BIT_SIZE  52
269 #define IOMMU_OUT_ADDR_BIT_SIZE 52
270 
271 /*
272  * This bitmap is used to advertise the page sizes our hardware support
273  * to the IOMMU core, which will then use this information to split
274  * physically contiguous memory regions it is mapping into page sizes
275  * that we support.
276  *
277  * 512GB Pages are not supported due to a hardware bug
278  */
279 #define AMD_IOMMU_PGSIZES	((~0xFFFUL) & ~(2ULL << 38))
280 /* 4K, 2MB, 1G page sizes are supported */
281 #define AMD_IOMMU_PGSIZES_V2	(PAGE_SIZE | (1ULL << 21) | (1ULL << 30))
282 
283 /* Bit value definition for dte irq remapping fields*/
284 #define DTE_IRQ_PHYS_ADDR_MASK	(((1ULL << 45)-1) << 6)
285 #define DTE_IRQ_REMAP_INTCTL_MASK	(0x3ULL << 60)
286 #define DTE_IRQ_REMAP_INTCTL    (2ULL << 60)
287 #define DTE_IRQ_REMAP_ENABLE    1ULL
288 
289 /*
290  * AMD IOMMU hardware only support 512 IRTEs despite
291  * the architectural limitation of 2048 entries.
292  */
293 #define DTE_INTTAB_ALIGNMENT    128
294 #define DTE_INTTABLEN_VALUE     9ULL
295 #define DTE_INTTABLEN           (DTE_INTTABLEN_VALUE << 1)
296 #define DTE_INTTABLEN_MASK      (0xfULL << 1)
297 #define MAX_IRQS_PER_TABLE      (1 << DTE_INTTABLEN_VALUE)
298 
299 #define PAGE_MODE_NONE    0x00
300 #define PAGE_MODE_1_LEVEL 0x01
301 #define PAGE_MODE_2_LEVEL 0x02
302 #define PAGE_MODE_3_LEVEL 0x03
303 #define PAGE_MODE_4_LEVEL 0x04
304 #define PAGE_MODE_5_LEVEL 0x05
305 #define PAGE_MODE_6_LEVEL 0x06
306 #define PAGE_MODE_7_LEVEL 0x07
307 
308 #define PM_LEVEL_SHIFT(x)	(12 + ((x) * 9))
309 #define PM_LEVEL_SIZE(x)	(((x) < 6) ? \
310 				  ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
311 				   (0xffffffffffffffffULL))
312 #define PM_LEVEL_INDEX(x, a)	(((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
313 #define PM_LEVEL_ENC(x)		(((x) << 9) & 0xe00ULL)
314 #define PM_LEVEL_PDE(x, a)	((a) | PM_LEVEL_ENC((x)) | \
315 				 IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW)
316 #define PM_PTE_LEVEL(pte)	(((pte) >> 9) & 0x7ULL)
317 
318 #define PM_MAP_4k		0
319 #define PM_ADDR_MASK		0x000ffffffffff000ULL
320 #define PM_MAP_MASK(lvl)	(PM_ADDR_MASK & \
321 				(~((1ULL << (12 + ((lvl) * 9))) - 1)))
322 #define PM_ALIGNED(lvl, addr)	((PM_MAP_MASK(lvl) & (addr)) == (addr))
323 
324 /*
325  * Returns the page table level to use for a given page size
326  * Pagesize is expected to be a power-of-two
327  */
328 #define PAGE_SIZE_LEVEL(pagesize) \
329 		((__ffs(pagesize) - 12) / 9)
330 /*
331  * Returns the number of ptes to use for a given page size
332  * Pagesize is expected to be a power-of-two
333  */
334 #define PAGE_SIZE_PTE_COUNT(pagesize) \
335 		(1ULL << ((__ffs(pagesize) - 12) % 9))
336 
337 /*
338  * Aligns a given io-virtual address to a given page size
339  * Pagesize is expected to be a power-of-two
340  */
341 #define PAGE_SIZE_ALIGN(address, pagesize) \
342 		((address) & ~((pagesize) - 1))
343 /*
344  * Creates an IOMMU PTE for an address and a given pagesize
345  * The PTE has no permission bits set
346  * Pagesize is expected to be a power-of-two larger than 4096
347  */
348 #define PAGE_SIZE_PTE(address, pagesize)		\
349 		(((address) | ((pagesize) - 1)) &	\
350 		 (~(pagesize >> 1)) & PM_ADDR_MASK)
351 
352 /*
353  * Takes a PTE value with mode=0x07 and returns the page size it maps
354  */
355 #define PTE_PAGE_SIZE(pte) \
356 	(1ULL << (1 + ffz(((pte) | 0xfffULL))))
357 
358 /*
359  * Takes a page-table level and returns the default page-size for this level
360  */
361 #define PTE_LEVEL_PAGE_SIZE(level)			\
362 	(1ULL << (12 + (9 * (level))))
363 
364 /*
365  * Bit value definition for I/O PTE fields
366  */
367 #define IOMMU_PTE_PR (1ULL << 0)
368 #define IOMMU_PTE_U  (1ULL << 59)
369 #define IOMMU_PTE_FC (1ULL << 60)
370 #define IOMMU_PTE_IR (1ULL << 61)
371 #define IOMMU_PTE_IW (1ULL << 62)
372 
373 /*
374  * Bit value definition for DTE fields
375  */
376 #define DTE_FLAG_V  (1ULL << 0)
377 #define DTE_FLAG_TV (1ULL << 1)
378 #define DTE_FLAG_IR (1ULL << 61)
379 #define DTE_FLAG_IW (1ULL << 62)
380 
381 #define DTE_FLAG_IOTLB	(1ULL << 32)
382 #define DTE_FLAG_GIOV	(1ULL << 54)
383 #define DTE_FLAG_GV	(1ULL << 55)
384 #define DTE_FLAG_MASK	(0x3ffULL << 32)
385 #define DTE_GLX_SHIFT	(56)
386 #define DTE_GLX_MASK	(3)
387 #define DEV_DOMID_MASK	0xffffULL
388 
389 #define DTE_GCR3_VAL_A(x)	(((x) >> 12) & 0x00007ULL)
390 #define DTE_GCR3_VAL_B(x)	(((x) >> 15) & 0x0ffffULL)
391 #define DTE_GCR3_VAL_C(x)	(((x) >> 31) & 0x1fffffULL)
392 
393 #define DTE_GCR3_INDEX_A	0
394 #define DTE_GCR3_INDEX_B	1
395 #define DTE_GCR3_INDEX_C	1
396 
397 #define DTE_GCR3_SHIFT_A	58
398 #define DTE_GCR3_SHIFT_B	16
399 #define DTE_GCR3_SHIFT_C	43
400 
401 #define GCR3_VALID		0x01ULL
402 
403 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
404 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR)
405 #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK))
406 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
407 
408 #define IOMMU_PROT_MASK 0x03
409 #define IOMMU_PROT_IR 0x01
410 #define IOMMU_PROT_IW 0x02
411 
412 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE	(1 << 2)
413 
414 /* IOMMU capabilities */
415 #define IOMMU_CAP_IOTLB   24
416 #define IOMMU_CAP_NPCACHE 26
417 #define IOMMU_CAP_EFR     27
418 
419 /* IOMMU IVINFO */
420 #define IOMMU_IVINFO_OFFSET     36
421 #define IOMMU_IVINFO_EFRSUP     BIT(0)
422 #define IOMMU_IVINFO_DMA_REMAP  BIT(1)
423 
424 /* IOMMU Feature Reporting Field (for IVHD type 10h */
425 #define IOMMU_FEAT_GASUP_SHIFT	6
426 
427 /* IOMMU Extended Feature Register (EFR) */
428 #define IOMMU_EFR_XTSUP_SHIFT	2
429 #define IOMMU_EFR_GASUP_SHIFT	7
430 #define IOMMU_EFR_MSICAPMMIOSUP_SHIFT	46
431 
432 #define MAX_DOMAIN_ID 65536
433 
434 /* Protection domain flags */
435 #define PD_DMA_OPS_MASK		(1UL << 0) /* domain used for dma_ops */
436 #define PD_DEFAULT_MASK		(1UL << 1) /* domain is a default dma_ops
437 					      domain for an IOMMU */
438 #define PD_PASSTHROUGH_MASK	(1UL << 2) /* domain has no page
439 					      translation */
440 #define PD_IOMMUV2_MASK		(1UL << 3) /* domain has gcr3 table */
441 #define PD_GIOV_MASK		(1UL << 4) /* domain enable GIOV support */
442 
443 extern bool amd_iommu_dump;
444 #define DUMP_printk(format, arg...)				\
445 	do {							\
446 		if (amd_iommu_dump)				\
447 			pr_info("AMD-Vi: " format, ## arg);	\
448 	} while(0);
449 
450 /* global flag if IOMMUs cache non-present entries */
451 extern bool amd_iommu_np_cache;
452 /* Only true if all IOMMUs support device IOTLBs */
453 extern bool amd_iommu_iotlb_sup;
454 
455 struct irq_remap_table {
456 	raw_spinlock_t lock;
457 	unsigned min_index;
458 	u32 *table;
459 };
460 
461 /* Interrupt remapping feature used? */
462 extern bool amd_iommu_irq_remap;
463 
464 extern const struct iommu_ops amd_iommu_ops;
465 
466 /* IVRS indicates that pre-boot remapping was enabled */
467 extern bool amdr_ivrs_remap_support;
468 
469 /* kmem_cache to get tables with 128 byte alignement */
470 extern struct kmem_cache *amd_iommu_irq_cache;
471 
472 #define PCI_SBDF_TO_SEGID(sbdf)		(((sbdf) >> 16) & 0xffff)
473 #define PCI_SBDF_TO_DEVID(sbdf)		((sbdf) & 0xffff)
474 #define PCI_SEG_DEVID_TO_SBDF(seg, devid)	((((u32)(seg) & 0xffff) << 16) | \
475 						 ((devid) & 0xffff))
476 
477 /* Make iterating over all pci segment easier */
478 #define for_each_pci_segment(pci_seg) \
479 	list_for_each_entry((pci_seg), &amd_iommu_pci_seg_list, list)
480 #define for_each_pci_segment_safe(pci_seg, next) \
481 	list_for_each_entry_safe((pci_seg), (next), &amd_iommu_pci_seg_list, list)
482 /*
483  * Make iterating over all IOMMUs easier
484  */
485 #define for_each_iommu(iommu) \
486 	list_for_each_entry((iommu), &amd_iommu_list, list)
487 #define for_each_iommu_safe(iommu, next) \
488 	list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
489 
490 #define APERTURE_RANGE_SHIFT	27	/* 128 MB */
491 #define APERTURE_RANGE_SIZE	(1ULL << APERTURE_RANGE_SHIFT)
492 #define APERTURE_RANGE_PAGES	(APERTURE_RANGE_SIZE >> PAGE_SHIFT)
493 #define APERTURE_MAX_RANGES	32	/* allows 4GB of DMA address space */
494 #define APERTURE_RANGE_INDEX(a)	((a) >> APERTURE_RANGE_SHIFT)
495 #define APERTURE_PAGE_INDEX(a)	(((a) >> 21) & 0x3fULL)
496 
497 /*
498  * This struct is used to pass information about
499  * incoming PPR faults around.
500  */
501 struct amd_iommu_fault {
502 	u64 address;    /* IO virtual address of the fault*/
503 	u32 pasid;      /* Address space identifier */
504 	u32 sbdf;	/* Originating PCI device id */
505 	u16 tag;        /* PPR tag */
506 	u16 flags;      /* Fault flags */
507 
508 };
509 
510 
511 struct amd_iommu;
512 struct iommu_domain;
513 struct irq_domain;
514 struct amd_irte_ops;
515 
516 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED      (1 << 0)
517 
518 #define io_pgtable_to_data(x) \
519 	container_of((x), struct amd_io_pgtable, iop)
520 
521 #define io_pgtable_ops_to_data(x) \
522 	io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
523 
524 #define io_pgtable_ops_to_domain(x) \
525 	container_of(io_pgtable_ops_to_data(x), \
526 		     struct protection_domain, iop)
527 
528 #define io_pgtable_cfg_to_data(x) \
529 	container_of((x), struct amd_io_pgtable, pgtbl_cfg)
530 
531 struct amd_io_pgtable {
532 	struct io_pgtable_cfg	pgtbl_cfg;
533 	struct io_pgtable	iop;
534 	int			mode;
535 	u64			*root;
536 	atomic64_t		pt_root;	/* pgtable root and pgtable mode */
537 	u64			*pgd;		/* v2 pgtable pgd pointer */
538 };
539 
540 /*
541  * This structure contains generic data for  IOMMU protection domains
542  * independent of their use.
543  */
544 struct protection_domain {
545 	struct list_head dev_list; /* List of all devices in this domain */
546 	struct iommu_domain domain; /* generic domain handle used by
547 				       iommu core code */
548 	struct amd_io_pgtable iop;
549 	spinlock_t lock;	/* mostly used to lock the page table*/
550 	u16 id;			/* the domain id written to the device table */
551 	int glx;		/* Number of levels for GCR3 table */
552 	u64 *gcr3_tbl;		/* Guest CR3 table */
553 	unsigned long flags;	/* flags to find out type of domain */
554 	unsigned dev_cnt;	/* devices assigned to this domain */
555 	unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
556 };
557 
558 /*
559  * This structure contains information about one PCI segment in the system.
560  */
561 struct amd_iommu_pci_seg {
562 	/* List with all PCI segments in the system */
563 	struct list_head list;
564 
565 	/* List of all available dev_data structures */
566 	struct llist_head dev_data_list;
567 
568 	/* PCI segment number */
569 	u16 id;
570 
571 	/* Largest PCI device id we expect translation requests for */
572 	u16 last_bdf;
573 
574 	/* Size of the device table */
575 	u32 dev_table_size;
576 
577 	/* Size of the alias table */
578 	u32 alias_table_size;
579 
580 	/* Size of the rlookup table */
581 	u32 rlookup_table_size;
582 
583 	/*
584 	 * device table virtual address
585 	 *
586 	 * Pointer to the per PCI segment device table.
587 	 * It is indexed by the PCI device id or the HT unit id and contains
588 	 * information about the domain the device belongs to as well as the
589 	 * page table root pointer.
590 	 */
591 	struct dev_table_entry *dev_table;
592 
593 	/*
594 	 * The rlookup iommu table is used to find the IOMMU which is
595 	 * responsible for a specific device. It is indexed by the PCI
596 	 * device id.
597 	 */
598 	struct amd_iommu **rlookup_table;
599 
600 	/*
601 	 * This table is used to find the irq remapping table for a given
602 	 * device id quickly.
603 	 */
604 	struct irq_remap_table **irq_lookup_table;
605 
606 	/*
607 	 * Pointer to a device table which the content of old device table
608 	 * will be copied to. It's only be used in kdump kernel.
609 	 */
610 	struct dev_table_entry *old_dev_tbl_cpy;
611 
612 	/*
613 	 * The alias table is a driver specific data structure which contains the
614 	 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
615 	 * More than one device can share the same requestor id.
616 	 */
617 	u16 *alias_table;
618 
619 	/*
620 	 * A list of required unity mappings we find in ACPI. It is not locked
621 	 * because as runtime it is only read. It is created at ACPI table
622 	 * parsing time.
623 	 */
624 	struct list_head unity_map;
625 };
626 
627 /*
628  * Structure where we save information about one hardware AMD IOMMU in the
629  * system.
630  */
631 struct amd_iommu {
632 	struct list_head list;
633 
634 	/* Index within the IOMMU array */
635 	int index;
636 
637 	/* locks the accesses to the hardware */
638 	raw_spinlock_t lock;
639 
640 	/* Pointer to PCI device of this IOMMU */
641 	struct pci_dev *dev;
642 
643 	/* Cache pdev to root device for resume quirks */
644 	struct pci_dev *root_pdev;
645 
646 	/* physical address of MMIO space */
647 	u64 mmio_phys;
648 
649 	/* physical end address of MMIO space */
650 	u64 mmio_phys_end;
651 
652 	/* virtual address of MMIO space */
653 	u8 __iomem *mmio_base;
654 
655 	/* capabilities of that IOMMU read from ACPI */
656 	u32 cap;
657 
658 	/* flags read from acpi table */
659 	u8 acpi_flags;
660 
661 	/* Extended features */
662 	u64 features;
663 
664 	/* Extended features 2 */
665 	u64 features2;
666 
667 	/* IOMMUv2 */
668 	bool is_iommu_v2;
669 
670 	/* PCI device id of the IOMMU device */
671 	u16 devid;
672 
673 	/*
674 	 * Capability pointer. There could be more than one IOMMU per PCI
675 	 * device function if there are more than one AMD IOMMU capability
676 	 * pointers.
677 	 */
678 	u16 cap_ptr;
679 
680 	/* pci domain of this IOMMU */
681 	struct amd_iommu_pci_seg *pci_seg;
682 
683 	/* start of exclusion range of that IOMMU */
684 	u64 exclusion_start;
685 	/* length of exclusion range of that IOMMU */
686 	u64 exclusion_length;
687 
688 	/* command buffer virtual address */
689 	u8 *cmd_buf;
690 	u32 cmd_buf_head;
691 	u32 cmd_buf_tail;
692 
693 	/* event buffer virtual address */
694 	u8 *evt_buf;
695 
696 	/* Base of the PPR log, if present */
697 	u8 *ppr_log;
698 
699 	/* Base of the GA log, if present */
700 	u8 *ga_log;
701 
702 	/* Tail of the GA log, if present */
703 	u8 *ga_log_tail;
704 
705 	/* true if interrupts for this IOMMU are already enabled */
706 	bool int_enabled;
707 
708 	/* if one, we need to send a completion wait command */
709 	bool need_sync;
710 
711 	/* Handle for IOMMU core code */
712 	struct iommu_device iommu;
713 
714 	/*
715 	 * We can't rely on the BIOS to restore all values on reinit, so we
716 	 * need to stash them
717 	 */
718 
719 	/* The iommu BAR */
720 	u32 stored_addr_lo;
721 	u32 stored_addr_hi;
722 
723 	/*
724 	 * Each iommu has 6 l1s, each of which is documented as having 0x12
725 	 * registers
726 	 */
727 	u32 stored_l1[6][0x12];
728 
729 	/* The l2 indirect registers */
730 	u32 stored_l2[0x83];
731 
732 	/* The maximum PC banks and counters/bank (PCSup=1) */
733 	u8 max_banks;
734 	u8 max_counters;
735 #ifdef CONFIG_IRQ_REMAP
736 	struct irq_domain *ir_domain;
737 	struct irq_domain *msi_domain;
738 
739 	struct amd_irte_ops *irte_ops;
740 #endif
741 
742 	u32 flags;
743 	volatile u64 *cmd_sem;
744 	u64 cmd_sem_val;
745 
746 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
747 	/* DebugFS Info */
748 	struct dentry *debugfs;
749 #endif
750 };
751 
dev_to_amd_iommu(struct device * dev)752 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
753 {
754 	struct iommu_device *iommu = dev_to_iommu_device(dev);
755 
756 	return container_of(iommu, struct amd_iommu, iommu);
757 }
758 
759 #define ACPIHID_UID_LEN 256
760 #define ACPIHID_HID_LEN 9
761 
762 struct acpihid_map_entry {
763 	struct list_head list;
764 	u8 uid[ACPIHID_UID_LEN];
765 	u8 hid[ACPIHID_HID_LEN];
766 	u32 devid;
767 	u32 root_devid;
768 	bool cmd_line;
769 	struct iommu_group *group;
770 };
771 
772 struct devid_map {
773 	struct list_head list;
774 	u8 id;
775 	u32 devid;
776 	bool cmd_line;
777 };
778 
779 /*
780  * This struct contains device specific data for the IOMMU
781  */
782 struct iommu_dev_data {
783 	/*Protect against attach/detach races */
784 	spinlock_t lock;
785 
786 	struct list_head list;		  /* For domain->dev_list */
787 	struct llist_node dev_data_list;  /* For global dev_data_list */
788 	struct protection_domain *domain; /* Domain the device is bound to */
789 	struct device *dev;
790 	u16 devid;			  /* PCI Device ID */
791 	bool iommu_v2;			  /* Device can make use of IOMMUv2 */
792 	struct {
793 		bool enabled;
794 		int qdep;
795 	} ats;				  /* ATS state */
796 	bool pri_tlp;			  /* PASID TLB required for
797 					     PPR completions */
798 	bool use_vapic;			  /* Enable device to use vapic mode */
799 	bool defer_attach;
800 
801 	struct ratelimit_state rs;        /* Ratelimit IOPF messages */
802 };
803 
804 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
805 extern struct list_head ioapic_map;
806 extern struct list_head hpet_map;
807 extern struct list_head acpihid_map;
808 
809 /*
810  * List with all PCI segments in the system. This list is not locked because
811  * it is only written at driver initialization time
812  */
813 extern struct list_head amd_iommu_pci_seg_list;
814 
815 /*
816  * List with all IOMMUs in the system. This list is not locked because it is
817  * only written and read at driver initialization or suspend time
818  */
819 extern struct list_head amd_iommu_list;
820 
821 /*
822  * Array with pointers to each IOMMU struct
823  * The indices are referenced in the protection domains
824  */
825 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
826 
827 /*
828  * Structure defining one entry in the device table
829  */
830 struct dev_table_entry {
831 	u64 data[4];
832 };
833 
834 /*
835  * One entry for unity mappings parsed out of the ACPI table.
836  */
837 struct unity_map_entry {
838 	struct list_head list;
839 
840 	/* starting device id this entry is used for (including) */
841 	u16 devid_start;
842 	/* end device id this entry is used for (including) */
843 	u16 devid_end;
844 
845 	/* start address to unity map (including) */
846 	u64 address_start;
847 	/* end address to unity map (including) */
848 	u64 address_end;
849 
850 	/* required protection */
851 	int prot;
852 };
853 
854 /*
855  * Data structures for device handling
856  */
857 
858 /* size of the dma_ops aperture as power of 2 */
859 extern unsigned amd_iommu_aperture_order;
860 
861 /* allocation bitmap for domain ids */
862 extern unsigned long *amd_iommu_pd_alloc_bitmap;
863 
864 /* Smallest max PASID supported by any IOMMU in the system */
865 extern u32 amd_iommu_max_pasid;
866 
867 extern bool amd_iommu_v2_present;
868 
869 extern bool amd_iommu_force_isolation;
870 
871 /* Max levels of glxval supported */
872 extern int amd_iommu_max_glx_val;
873 
874 /*
875  * This function flushes all internal caches of
876  * the IOMMU used by this driver.
877  */
878 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
879 
get_ioapic_devid(int id)880 static inline int get_ioapic_devid(int id)
881 {
882 	struct devid_map *entry;
883 
884 	list_for_each_entry(entry, &ioapic_map, list) {
885 		if (entry->id == id)
886 			return entry->devid;
887 	}
888 
889 	return -EINVAL;
890 }
891 
get_hpet_devid(int id)892 static inline int get_hpet_devid(int id)
893 {
894 	struct devid_map *entry;
895 
896 	list_for_each_entry(entry, &hpet_map, list) {
897 		if (entry->id == id)
898 			return entry->devid;
899 	}
900 
901 	return -EINVAL;
902 }
903 
904 enum amd_iommu_intr_mode_type {
905 	AMD_IOMMU_GUEST_IR_LEGACY,
906 
907 	/* This mode is not visible to users. It is used when
908 	 * we cannot fully enable vAPIC and fallback to only support
909 	 * legacy interrupt remapping via 128-bit IRTE.
910 	 */
911 	AMD_IOMMU_GUEST_IR_LEGACY_GA,
912 	AMD_IOMMU_GUEST_IR_VAPIC,
913 };
914 
915 #define AMD_IOMMU_GUEST_IR_GA(x)	(x == AMD_IOMMU_GUEST_IR_VAPIC || \
916 					 x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
917 
918 #define AMD_IOMMU_GUEST_IR_VAPIC(x)	(x == AMD_IOMMU_GUEST_IR_VAPIC)
919 
920 union irte {
921 	u32 val;
922 	struct {
923 		u32 valid	: 1,
924 		    no_fault	: 1,
925 		    int_type	: 3,
926 		    rq_eoi	: 1,
927 		    dm		: 1,
928 		    rsvd_1	: 1,
929 		    destination	: 8,
930 		    vector	: 8,
931 		    rsvd_2	: 8;
932 	} fields;
933 };
934 
935 #define APICID_TO_IRTE_DEST_LO(x)    (x & 0xffffff)
936 #define APICID_TO_IRTE_DEST_HI(x)    ((x >> 24) & 0xff)
937 
938 union irte_ga_lo {
939 	u64 val;
940 
941 	/* For int remapping */
942 	struct {
943 		u64 valid	: 1,
944 		    no_fault	: 1,
945 		    /* ------ */
946 		    int_type	: 3,
947 		    rq_eoi	: 1,
948 		    dm		: 1,
949 		    /* ------ */
950 		    guest_mode	: 1,
951 		    destination	: 24,
952 		    ga_tag	: 32;
953 	} fields_remap;
954 
955 	/* For guest vAPIC */
956 	struct {
957 		u64 valid	: 1,
958 		    no_fault	: 1,
959 		    /* ------ */
960 		    ga_log_intr	: 1,
961 		    rsvd1	: 3,
962 		    is_run	: 1,
963 		    /* ------ */
964 		    guest_mode	: 1,
965 		    destination	: 24,
966 		    ga_tag	: 32;
967 	} fields_vapic;
968 };
969 
970 union irte_ga_hi {
971 	u64 val;
972 	struct {
973 		u64 vector	: 8,
974 		    rsvd_1	: 4,
975 		    ga_root_ptr	: 40,
976 		    rsvd_2	: 4,
977 		    destination : 8;
978 	} fields;
979 };
980 
981 struct irte_ga {
982 	union irte_ga_lo lo;
983 	union irte_ga_hi hi;
984 };
985 
986 struct irq_2_irte {
987 	u16 devid; /* Device ID for IRTE table */
988 	u16 index; /* Index into IRTE table*/
989 };
990 
991 struct amd_ir_data {
992 	u32 cached_ga_tag;
993 	struct amd_iommu *iommu;
994 	struct irq_2_irte irq_2_irte;
995 	struct msi_msg msi_entry;
996 	void *entry;    /* Pointer to union irte or struct irte_ga */
997 	void *ref;      /* Pointer to the actual irte */
998 
999 	/**
1000 	 * Store information for activate/de-activate
1001 	 * Guest virtual APIC mode during runtime.
1002 	 */
1003 	struct irq_cfg *cfg;
1004 	int ga_vector;
1005 	int ga_root_ptr;
1006 	int ga_tag;
1007 };
1008 
1009 struct amd_irte_ops {
1010 	void (*prepare)(void *, u32, bool, u8, u32, int);
1011 	void (*activate)(struct amd_iommu *iommu, void *, u16, u16);
1012 	void (*deactivate)(struct amd_iommu *iommu, void *, u16, u16);
1013 	void (*set_affinity)(struct amd_iommu *iommu, void *, u16, u16, u8, u32);
1014 	void *(*get)(struct irq_remap_table *, int);
1015 	void (*set_allocated)(struct irq_remap_table *, int);
1016 	bool (*is_allocated)(struct irq_remap_table *, int);
1017 	void (*clear_allocated)(struct irq_remap_table *, int);
1018 };
1019 
1020 #ifdef CONFIG_IRQ_REMAP
1021 extern struct amd_irte_ops irte_32_ops;
1022 extern struct amd_irte_ops irte_128_ops;
1023 #endif
1024 
1025 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
1026