1 #ifndef _ASM_POWERPC_PTRACE_H
2 #define _ASM_POWERPC_PTRACE_H
3
4 /*
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
6 *
7 * This struct defines the way the registers are stored on the
8 * kernel stack during a system call or other kernel entry.
9 *
10 * this should only contain volatile regs
11 * since we can keep non-volatile in the thread_struct
12 * should set this up when only volatiles are saved
13 * by intr code.
14 *
15 * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
16 * that the overall structure is a multiple of 16 bytes in length.
17 *
18 * Note that the offsets of the fields in this struct correspond with
19 * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c.
20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License
23 * as published by the Free Software Foundation; either version
24 * 2 of the License, or (at your option) any later version.
25 */
26
27 #include <linux/types.h>
28
29 #ifndef __ASSEMBLY__
30
31 struct pt_regs {
32 unsigned long gpr[32];
33 unsigned long nip;
34 unsigned long msr;
35 unsigned long orig_gpr3; /* Used for restarting system calls */
36 unsigned long ctr;
37 unsigned long link;
38 unsigned long xer;
39 unsigned long ccr;
40 #ifdef __powerpc64__
41 unsigned long softe; /* Soft enabled/disabled */
42 #else
43 unsigned long mq; /* 601 only (not used at present) */
44 /* Used on APUS to hold IPL value. */
45 #endif
46 unsigned long trap; /* Reason for being here */
47 /* N.B. for critical exceptions on 4xx, the dar and dsisr
48 fields are overloaded to hold srr0 and srr1. */
49 unsigned long dar; /* Fault registers */
50 unsigned long dsisr; /* on 4xx/Book-E used for ESR */
51 unsigned long result; /* Result of a system call */
52 };
53
54 #endif /* __ASSEMBLY__ */
55
56 #ifdef __KERNEL__
57
58 #ifdef __powerpc64__
59
60 #define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
61 #define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */
62 #define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265)
63 #define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \
64 STACK_FRAME_OVERHEAD + 288)
65 #define STACK_FRAME_MARKER 12
66
67 /* Size of dummy stack frame allocated when calling signal handler. */
68 #define __SIGNAL_FRAMESIZE 128
69 #define __SIGNAL_FRAMESIZE32 64
70
71 #else /* __powerpc64__ */
72
73 #define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
74 #define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */
75 #define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773)
76 #define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
77 #define STACK_FRAME_MARKER 2
78
79 /* Size of stack frame allocated when calling signal handler. */
80 #define __SIGNAL_FRAMESIZE 64
81
82 #endif /* __powerpc64__ */
83
84 #ifndef __ASSEMBLY__
85
86 #define GET_IP(regs) ((regs)->nip)
87 #define GET_USP(regs) ((regs)->gpr[1])
88 #define GET_FP(regs) (0)
89 #define SET_FP(regs, val)
90
91 #ifdef CONFIG_SMP
92 extern unsigned long profile_pc(struct pt_regs *regs);
93 #define profile_pc profile_pc
94 #endif
95
96 #include <asm-generic/ptrace.h>
97
98 #define kernel_stack_pointer(regs) ((regs)->gpr[1])
is_syscall_success(struct pt_regs * regs)99 static inline int is_syscall_success(struct pt_regs *regs)
100 {
101 return !(regs->ccr & 0x10000000);
102 }
103
regs_return_value(struct pt_regs * regs)104 static inline long regs_return_value(struct pt_regs *regs)
105 {
106 if (is_syscall_success(regs))
107 return regs->gpr[3];
108 else
109 return -regs->gpr[3];
110 }
111
112 #ifdef __powerpc64__
113 #define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
114 #else
115 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
116 #endif
117
118 #define force_successful_syscall_return() \
119 do { \
120 set_thread_flag(TIF_NOERROR); \
121 } while(0)
122
123 struct task_struct;
124 extern unsigned long ptrace_get_reg(struct task_struct *task, int regno);
125 extern int ptrace_put_reg(struct task_struct *task, int regno,
126 unsigned long data);
127
128 /*
129 * We use the least-significant bit of the trap field to indicate
130 * whether we have saved the full set of registers, or only a
131 * partial set. A 1 there means the partial set.
132 * On 4xx we use the next bit to indicate whether the exception
133 * is a critical exception (1 means it is).
134 */
135 #define FULL_REGS(regs) (((regs)->trap & 1) == 0)
136 #ifndef __powerpc64__
137 #define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0)
138 #define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0)
139 #define IS_DEBUG_EXC(regs) (((regs)->trap & 8) != 0)
140 #endif /* ! __powerpc64__ */
141 #define TRAP(regs) ((regs)->trap & ~0xF)
142 #ifdef __powerpc64__
143 #define NV_REG_POISON 0xdeadbeefdeadbeefUL
144 #define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1)
145 #else
146 #define NV_REG_POISON 0xdeadbeef
147 #define CHECK_FULL_REGS(regs) \
148 do { \
149 if ((regs)->trap & 1) \
150 printk(KERN_CRIT "%s: partial register set\n", __func__); \
151 } while (0)
152 #endif /* __powerpc64__ */
153
154 #define arch_has_single_step() (1)
155 #define arch_has_block_step() (!cpu_has_feature(CPU_FTR_601))
156 #define ARCH_HAS_USER_SINGLE_STEP_INFO
157
158 /*
159 * kprobe-based event tracer support
160 */
161
162 #include <linux/stddef.h>
163 #include <linux/thread_info.h>
164 extern int regs_query_register_offset(const char *name);
165 extern const char *regs_query_register_name(unsigned int offset);
166 #define MAX_REG_OFFSET (offsetof(struct pt_regs, dsisr))
167
168 /**
169 * regs_get_register() - get register value from its offset
170 * @regs: pt_regs from which register value is gotten
171 * @offset: offset number of the register.
172 *
173 * regs_get_register returns the value of a register whose offset from @regs.
174 * The @offset is the offset of the register in struct pt_regs.
175 * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
176 */
regs_get_register(struct pt_regs * regs,unsigned int offset)177 static inline unsigned long regs_get_register(struct pt_regs *regs,
178 unsigned int offset)
179 {
180 if (unlikely(offset > MAX_REG_OFFSET))
181 return 0;
182 return *(unsigned long *)((unsigned long)regs + offset);
183 }
184
185 /**
186 * regs_within_kernel_stack() - check the address in the stack
187 * @regs: pt_regs which contains kernel stack pointer.
188 * @addr: address which is checked.
189 *
190 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
191 * If @addr is within the kernel stack, it returns true. If not, returns false.
192 */
193
regs_within_kernel_stack(struct pt_regs * regs,unsigned long addr)194 static inline bool regs_within_kernel_stack(struct pt_regs *regs,
195 unsigned long addr)
196 {
197 return ((addr & ~(THREAD_SIZE - 1)) ==
198 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
199 }
200
201 /**
202 * regs_get_kernel_stack_nth() - get Nth entry of the stack
203 * @regs: pt_regs which contains kernel stack pointer.
204 * @n: stack entry number.
205 *
206 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
207 * is specified by @regs. If the @n th entry is NOT in the kernel stack,
208 * this returns 0.
209 */
regs_get_kernel_stack_nth(struct pt_regs * regs,unsigned int n)210 static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
211 unsigned int n)
212 {
213 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
214 addr += n;
215 if (regs_within_kernel_stack(regs, (unsigned long)addr))
216 return *addr;
217 else
218 return 0;
219 }
220
221 #endif /* __ASSEMBLY__ */
222
223 #endif /* __KERNEL__ */
224
225 /*
226 * Offsets used by 'ptrace' system call interface.
227 * These can't be changed without breaking binary compatibility
228 * with MkLinux, etc.
229 */
230 #define PT_R0 0
231 #define PT_R1 1
232 #define PT_R2 2
233 #define PT_R3 3
234 #define PT_R4 4
235 #define PT_R5 5
236 #define PT_R6 6
237 #define PT_R7 7
238 #define PT_R8 8
239 #define PT_R9 9
240 #define PT_R10 10
241 #define PT_R11 11
242 #define PT_R12 12
243 #define PT_R13 13
244 #define PT_R14 14
245 #define PT_R15 15
246 #define PT_R16 16
247 #define PT_R17 17
248 #define PT_R18 18
249 #define PT_R19 19
250 #define PT_R20 20
251 #define PT_R21 21
252 #define PT_R22 22
253 #define PT_R23 23
254 #define PT_R24 24
255 #define PT_R25 25
256 #define PT_R26 26
257 #define PT_R27 27
258 #define PT_R28 28
259 #define PT_R29 29
260 #define PT_R30 30
261 #define PT_R31 31
262
263 #define PT_NIP 32
264 #define PT_MSR 33
265 #define PT_ORIG_R3 34
266 #define PT_CTR 35
267 #define PT_LNK 36
268 #define PT_XER 37
269 #define PT_CCR 38
270 #ifndef __powerpc64__
271 #define PT_MQ 39
272 #else
273 #define PT_SOFTE 39
274 #endif
275 #define PT_TRAP 40
276 #define PT_DAR 41
277 #define PT_DSISR 42
278 #define PT_RESULT 43
279 #define PT_REGS_COUNT 44
280
281 #define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
282
283 #ifndef __powerpc64__
284
285 #define PT_FPR31 (PT_FPR0 + 2*31)
286 #define PT_FPSCR (PT_FPR0 + 2*32 + 1)
287
288 #else /* __powerpc64__ */
289
290 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
291
292 #ifdef __KERNEL__
293 #define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */
294 #endif
295
296 #define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
297 #define PT_VSCR (PT_VR0 + 32*2 + 1)
298 #define PT_VRSAVE (PT_VR0 + 33*2)
299
300 #ifdef __KERNEL__
301 #define PT_VR0_32 164 /* each Vector reg occupies 4 slots in 32-bit */
302 #define PT_VSCR_32 (PT_VR0 + 32*4 + 3)
303 #define PT_VRSAVE_32 (PT_VR0 + 33*4)
304 #endif
305
306 /*
307 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
308 */
309 #define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
310 #define PT_VSR31 (PT_VSR0 + 2*31)
311 #ifdef __KERNEL__
312 #define PT_VSR0_32 300 /* each VSR reg occupies 4 slots in 32-bit */
313 #endif
314 #endif /* __powerpc64__ */
315
316 /*
317 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
318 * The transfer totals 34 quadword. Quadwords 0-31 contain the
319 * corresponding vector registers. Quadword 32 contains the vscr as the
320 * last word (offset 12) within that quadword. Quadword 33 contains the
321 * vrsave as the first word (offset 0) within the quadword.
322 *
323 * This definition of the VMX state is compatible with the current PPC32
324 * ptrace interface. This allows signal handling and ptrace to use the same
325 * structures. This also simplifies the implementation of a bi-arch
326 * (combined (32- and 64-bit) gdb.
327 */
328 #define PTRACE_GETVRREGS 18
329 #define PTRACE_SETVRREGS 19
330
331 /* Get/set all the upper 32-bits of the SPE registers, accumulator, and
332 * spefscr, in one go */
333 #define PTRACE_GETEVRREGS 20
334 #define PTRACE_SETEVRREGS 21
335
336 /* Get the first 32 128bit VSX registers */
337 #define PTRACE_GETVSRREGS 27
338 #define PTRACE_SETVSRREGS 28
339
340 /*
341 * Get or set a debug register. The first 16 are DABR registers and the
342 * second 16 are IABR registers.
343 */
344 #define PTRACE_GET_DEBUGREG 25
345 #define PTRACE_SET_DEBUGREG 26
346
347 /* (new) PTRACE requests using the same numbers as x86 and the same
348 * argument ordering. Additionally, they support more registers too
349 */
350 #define PTRACE_GETREGS 12
351 #define PTRACE_SETREGS 13
352 #define PTRACE_GETFPREGS 14
353 #define PTRACE_SETFPREGS 15
354 #define PTRACE_GETREGS64 22
355 #define PTRACE_SETREGS64 23
356
357 /* (old) PTRACE requests with inverted arguments */
358 #define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */
359 #define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */
360 #define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */
361 #define PPC_PTRACE_SETFPREGS 0x96 /* Set FPRs 0 - 31 */
362
363 /* Calls to trace a 64bit program from a 32bit program */
364 #define PPC_PTRACE_PEEKTEXT_3264 0x95
365 #define PPC_PTRACE_PEEKDATA_3264 0x94
366 #define PPC_PTRACE_POKETEXT_3264 0x93
367 #define PPC_PTRACE_POKEDATA_3264 0x92
368 #define PPC_PTRACE_PEEKUSR_3264 0x91
369 #define PPC_PTRACE_POKEUSR_3264 0x90
370
371 #define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */
372
373 #define PPC_PTRACE_GETHWDBGINFO 0x89
374 #define PPC_PTRACE_SETHWDEBUG 0x88
375 #define PPC_PTRACE_DELHWDEBUG 0x87
376
377 #ifndef __ASSEMBLY__
378
379 struct ppc_debug_info {
380 __u32 version; /* Only version 1 exists to date */
381 __u32 num_instruction_bps;
382 __u32 num_data_bps;
383 __u32 num_condition_regs;
384 __u32 data_bp_alignment;
385 __u32 sizeof_condition; /* size of the DVC register */
386 __u64 features;
387 };
388
389 #endif /* __ASSEMBLY__ */
390
391 /*
392 * features will have bits indication whether there is support for:
393 */
394 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001
395 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002
396 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004
397 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008
398
399 #ifndef __ASSEMBLY__
400
401 struct ppc_hw_breakpoint {
402 __u32 version; /* currently, version must be 1 */
403 __u32 trigger_type; /* only some combinations allowed */
404 __u32 addr_mode; /* address match mode */
405 __u32 condition_mode; /* break/watchpoint condition flags */
406 __u64 addr; /* break/watchpoint address */
407 __u64 addr2; /* range end or mask */
408 __u64 condition_value; /* contents of the DVC register */
409 };
410
411 #endif /* __ASSEMBLY__ */
412
413 /*
414 * Trigger Type
415 */
416 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001
417 #define PPC_BREAKPOINT_TRIGGER_READ 0x00000002
418 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004
419 #define PPC_BREAKPOINT_TRIGGER_RW \
420 (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
421
422 /*
423 * Address Mode
424 */
425 #define PPC_BREAKPOINT_MODE_EXACT 0x00000000
426 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001
427 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002
428 #define PPC_BREAKPOINT_MODE_MASK 0x00000003
429
430 /*
431 * Condition Mode
432 */
433 #define PPC_BREAKPOINT_CONDITION_MODE 0x00000003
434 #define PPC_BREAKPOINT_CONDITION_NONE 0x00000000
435 #define PPC_BREAKPOINT_CONDITION_AND 0x00000001
436 #define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND
437 #define PPC_BREAKPOINT_CONDITION_OR 0x00000002
438 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
439 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
440 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
441 #define PPC_BREAKPOINT_CONDITION_BE(n) \
442 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
443
444 #endif /* _ASM_POWERPC_PTRACE_H */
445