1 /* 2 * include/asm-ppc/ibm44x.h 3 * 4 * PPC44x definitions 5 * 6 * Matt Porter <mporter@mvista.com> 7 * Copyright 2002-2003 MontaVista Software Inc. 8 * 9 * Eugene Surovegin <ebs@ebshome.net> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 17 #ifdef __KERNEL__ 18 #ifndef __ASM_IBM44x_H__ 19 #define __ASM_IBM44x_H__ 20 21 #include <linux/config.h> 22 23 #ifndef __ASSEMBLY__ 24 /* 25 * Data structure defining board information maintained by the boot 26 * ROM on IBM's "Ebony" evaluation board. An effort has been made to 27 * keep the field names consistent with the 8xx 'bd_t' board info 28 * structures. 29 * 30 * Ebony firmware stores MAC addresses in the F/W VPD area. The 31 * firmware must store the other dynamic values in NVRAM like on 32 * the previous 40x systems so they should be accessible if we 33 * really want them. 34 */ 35 typedef struct board_info { 36 unsigned char bi_enetaddr[2][6]; /* EMAC addresses */ 37 unsigned int bi_opb_busfreq; /* OPB clock in Hz */ 38 int bi_iic_fast[2]; /* Use fast i2c mode */ 39 } bd_t; 40 #endif /* __ASSEMBLY__ */ 41 42 #ifndef NR_BOARD_IRQS 43 #define NR_BOARD_IRQS 0 44 #endif 45 46 #define _IO_BASE isa_io_base 47 #define _ISA_MEM_BASE isa_mem_base 48 #define PCI_DRAM_OFFSET pci_dram_offset 49 50 /* TLB entry offset/size used for pinning kernel lowmem */ 51 #define PPC44x_PIN_SHIFT 28 52 #define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT) 53 54 /* Lowest TLB slot consumed by the default pinned TLBs */ 55 #define PPC44x_LOW_SLOT 62 56 57 /* 58 * Standard 4GB "page" definitions 59 */ 60 #define PPC44x_IO_PAGE 0x0000000100000000ULL 61 #define PPC44x_PCICFG_PAGE 0x0000000200000000ULL 62 #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE 63 #define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL 64 65 /* 66 * 36-bit trap ranges 67 */ 68 #define PPC44x_IO_LO 0x40000000 69 #define PPC44x_IO_HI 0x40001000 70 #define PPC44x_PCICFG_LO 0x0ec00000 71 #define PPC44x_PCICFG_HI 0x0ec7ffff 72 #define PPC44x_PCIMEM_LO 0x80002000 73 #define PPC44x_PCIMEM_HI 0xffffffff 74 75 /* 76 * The "residual" board information structure the boot loader passes 77 * into the kernel. 78 */ 79 #ifndef __ASSEMBLY__ 80 81 /* 82 * SPRN definitions 83 */ 84 #define SPRN_CPC0_GPIO 0xe5 85 86 /* 87 * DCRN definitions 88 */ 89 90 #ifdef CONFIG_440GX 91 /* CPRs */ 92 #define DCRN_CPR_CONFIG_ADDR 0xc 93 #define DCRN_CPR_CONFIG_DATA 0xd 94 95 #define DCRN_CPR_CLKUPD 0x0020 96 #define DCRN_CPR_PLLC 0x0040 97 #define DCRN_CPR_PLLD 0x0060 98 #define DCRN_CPR_PRIMAD 0x0080 99 #define DCRN_CPR_PRIMBD 0x00a0 100 #define DCRN_CPR_OPBD 0x00c0 101 #define DCRN_CPR_PERD 0x00e0 102 #define DCRN_CPR_MALD 0x0100 103 104 /* CPRs read/write helper macros */ 105 #define CPR_READ(offset) ({\ 106 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ 107 mfdcr(DCRN_CPR_CONFIG_DATA);}) 108 #define CPR_WRITE(offset, data) ({\ 109 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ 110 mtdcr(DCRN_CPR_CONFIG_DATA, data);}) 111 112 /* SDRs */ 113 #define DCRN_SDR_CONFIG_ADDR 0xe 114 #define DCRN_SDR_CONFIG_DATA 0xf 115 #define DCRN_SDR_PFC0 0x4100 116 #define DCRN_SDR_PFC1 0x4101 117 #define DCRN_SDR_MFR 0x4300 118 #define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */ 119 #define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */ 120 #define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */ 121 #define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */ 122 #define DCRN_SDR_MFR_T0TXFL 0x00080000 123 #define DCRN_SDR_MFR_T0TXFH 0x00040000 124 #define DCRN_SDR_MFR_T1TXFL 0x00020000 125 #define DCRN_SDR_MFR_T1TXFH 0x00010000 126 #define DCRN_SDR_MFR_E0TXFL 0x00008000 127 #define DCRN_SDR_MFR_E0TXFH 0x00004000 128 #define DCRN_SDR_MFR_E0RXFL 0x00002000 129 #define DCRN_SDR_MFR_E0RXFH 0x00001000 130 #define DCRN_SDR_MFR_E1TXFL 0x00000800 131 #define DCRN_SDR_MFR_E1TXFH 0x00000400 132 #define DCRN_SDR_MFR_E1RXFL 0x00000200 133 #define DCRN_SDR_MFR_E1RXFH 0x00000100 134 #define DCRN_SDR_MFR_E2TXFL 0x00000080 135 #define DCRN_SDR_MFR_E2TXFH 0x00000040 136 #define DCRN_SDR_MFR_E2RXFL 0x00000020 137 #define DCRN_SDR_MFR_E2RXFH 0x00000010 138 #define DCRN_SDR_MFR_E3TXFL 0x00000008 139 #define DCRN_SDR_MFR_E3TXFH 0x00000004 140 #define DCRN_SDR_MFR_E3RXFL 0x00000002 141 #define DCRN_SDR_MFR_E3RXFH 0x00000001 142 #define DCRN_SDR_UART0 0x0120 143 #define DCRN_SDR_UART1 0x0121 144 145 /* SDR read/write helper macros */ 146 #define SDR_READ(offset) ({\ 147 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ 148 mfdcr(DCRN_SDR_CONFIG_DATA);}) 149 #define SDR_WRITE(offset, data) ({\ 150 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ 151 mtdcr(DCRN_SDR_CONFIG_DATA,data);}) 152 #endif /* CONFIG_440GX */ 153 154 /* Base DCRNs */ 155 #define DCRN_DMA0_BASE 0x100 156 #define DCRN_DMA1_BASE 0x108 157 #define DCRN_DMA2_BASE 0x110 158 #define DCRN_DMA3_BASE 0x118 159 #define DCRN_DMASR_BASE 0x120 160 #define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ 161 #define DCRN_MAL_BASE 0x180 162 163 /* UIC */ 164 #define DCRN_UIC0_BASE 0xc0 165 #define DCRN_UIC1_BASE 0xd0 166 #define UIC0 DCRN_UIC0_BASE 167 #define UIC1 DCRN_UIC1_BASE 168 169 #define DCRN_UIC_SR(base) (base + 0x0) 170 #define DCRN_UIC_ER(base) (base + 0x2) 171 #define DCRN_UIC_CR(base) (base + 0x3) 172 #define DCRN_UIC_PR(base) (base + 0x4) 173 #define DCRN_UIC_TR(base) (base + 0x5) 174 #define DCRN_UIC_MSR(base) (base + 0x6) 175 #define DCRN_UIC_VR(base) (base + 0x7) 176 #define DCRN_UIC_VCR(base) (base + 0x8) 177 178 #define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */ 179 #define UIC0_UIC1CR 31 /* UIC1 critical interrupt */ 180 181 /* 440GP MAL DCRs */ 182 #define DCRN_MALCR(base) (base + 0x0) /* Configuration */ 183 #define DCRN_MALESR(base) (base + 0x1) /* Error Status */ 184 #define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */ 185 #define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */ 186 #define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */ 187 #define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */ 188 #define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */ 189 #define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */ 190 #define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */ 191 #define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */ 192 #define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */ 193 #define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */ 194 #define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */ 195 #define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */ 196 #define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */ 197 #define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */ 198 #define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */ 199 #define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */ 200 #define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */ 201 202 /* Compatibility DCRN's */ 203 #define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */ 204 #define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */ 205 #define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */ 206 #define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */ 207 #define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */ 208 #define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */ 209 #define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */ 210 #define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */ 211 212 213 #define MALCR_MMSR 0x80000000 /* MAL Software reset */ 214 #define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ 215 #define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ 216 #define MALCR_PLBP_3 0x00C00000 /* highest */ 217 #define MALCR_GA 0x00200000 /* Guarded Active Bit */ 218 #define MALCR_OA 0x00100000 /* Ordered Active Bit */ 219 #define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ 220 #define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ 221 #define MALCR_PLBLT_2 0x00020000 222 #define MALCR_PLBLT_3 0x00010000 223 #define MALCR_PLBLT_4 0x00008000 224 #ifdef CONFIG_440GP 225 #define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */ 226 #else 227 #define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */ 228 #endif 229 #define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ 230 #define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ 231 #define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ 232 #define MALCR_LEA 0x00000002 /* Locked Error Active */ 233 #define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ 234 /* DCRN_MALESR */ 235 #define MALESR_EVB 0x80000000 /* Error Valid Bit */ 236 #define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ 237 #define MALESR_DE 0x00100000 /* Descriptor Error */ 238 #define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ 239 #define MALESR_OTE 0x00040000 /* OPB Timeout Error */ 240 #define MALESR_OSE 0x00020000 /* OPB Slave Error */ 241 #define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ 242 #define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ 243 #define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ 244 #define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ 245 #define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ 246 #define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ 247 /* DCRN_MALIER */ 248 #define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ 249 #define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ 250 #define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ 251 #define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ 252 #define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ 253 /* DCRN_MALTXEOBISR */ 254 #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ 255 #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ 256 257 /* 440GP PLB Arbiter DCRs */ 258 #define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */ 259 #define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */ 260 #define DCRN_PLB0_BESR 0x084 /* PLB Error Status */ 261 #define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */ 262 #define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */ 263 #define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */ 264 265 /* 440GP Clock, PM, chip control */ 266 #define DCRN_CPC0_SR 0x0b0 267 #define DCRN_CPC0_ER 0x0b1 268 #define DCRN_CPC0_FR 0x0b2 269 #define DCRN_CPC0_SYS0 0x0e0 270 #define DCRN_CPC0_SYS1 0x0e1 271 #define DCRN_CPC0_CUST0 0x0e2 272 #define DCRN_CPC0_CUST1 0x0e3 273 #define DCRN_CPC0_STRP0 0x0e4 274 #define DCRN_CPC0_STRP1 0x0e5 275 #define DCRN_CPC0_STRP2 0x0e6 276 #define DCRN_CPC0_STRP3 0x0e7 277 #define DCRN_CPC0_GPIO 0x0e8 278 #define DCRN_CPC0_PLB 0x0e9 279 #define DCRN_CPC0_CR1 0x0ea 280 #define DCRN_CPC0_CR0 0x0eb 281 #define DCRN_CPC0_MIRQ0 0x0ec 282 #define DCRN_CPC0_MIRQ1 0x0ed 283 #define DCRN_CPC0_JTAGID 0x0ef 284 285 /* 440GP DMA controller DCRs */ 286 #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */ 287 #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */ 288 #define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */ 289 #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */ 290 #define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */ 291 #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */ 292 #define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */ 293 #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */ 294 295 #define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */ 296 #define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */ 297 #define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */ 298 #define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */ 299 #define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */ 300 #define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */ 301 #define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */ 302 #define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */ 303 304 #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */ 305 #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */ 306 #define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */ 307 #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */ 308 #define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */ 309 #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */ 310 #define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */ 311 #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */ 312 313 #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */ 314 #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */ 315 #define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */ 316 #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */ 317 #define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */ 318 #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */ 319 #define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */ 320 #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */ 321 322 #define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ 323 #define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ 324 #define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ 325 #define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ 326 327 /* 440GP DRAM controller DCRs */ 328 #define DCRN_SDRAM0_CFGADDR 0x010 329 #define DCRN_SDRAM0_CFGDATA 0x011 330 331 #define SDRAM0_B0CR 0x40 332 #define SDRAM0_B1CR 0x44 333 #define SDRAM0_B2CR 0x48 334 #define SDRAM0_B3CR 0x4c 335 336 #define SDRAM_CONFIG_BANK_ENABLE 0x00000001 337 #define SDRAM_CONFIG_SIZE_MASK 0x000e0000 338 #define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17) 339 #define SDRAM_CONFIG_SIZE_8M 0x00000001 340 #define SDRAM_CONFIG_SIZE_16M 0x00000002 341 #define SDRAM_CONFIG_SIZE_32M 0x00000003 342 #define SDRAM_CONFIG_SIZE_64M 0x00000004 343 #define SDRAM_CONFIG_SIZE_128M 0x00000005 344 #define SDRAM_CONFIG_SIZE_256M 0x00000006 345 #define SDRAM_CONFIG_SIZE_512M 0x00000007 346 #define PPC44x_MEM_SIZE_8M 0x00800000 347 #define PPC44x_MEM_SIZE_16M 0x01000000 348 #define PPC44x_MEM_SIZE_32M 0x02000000 349 #define PPC44x_MEM_SIZE_64M 0x04000000 350 #define PPC44x_MEM_SIZE_128M 0x08000000 351 #define PPC44x_MEM_SIZE_256M 0x10000000 352 #define PPC44x_MEM_SIZE_512M 0x20000000 353 354 #ifdef CONFIG_440GX 355 /* Internal SRAM Controller */ 356 #define DCRN_SRAM0_SB0CR 0x020 357 #define DCRN_SRAM0_SB1CR 0x021 358 #define DCRN_SRAM0_SB2CR 0x022 359 #define DCRN_SRAM0_SB3CR 0x023 360 #define SRAM_SBCR_BAS0 0x80000000 361 #define SRAM_SBCR_BAS1 0x80010000 362 #define SRAM_SBCR_BAS2 0x80020000 363 #define SRAM_SBCR_BAS3 0x80030000 364 #define SRAM_SBCR_BU_MASK 0x00000180 365 #define SRAM_SBCR_BS_64KB 0x00000800 366 #define SRAM_SBCR_BU_RO 0x00000080 367 #define SRAM_SBCR_BU_RW 0x00000180 368 #define DCRN_SRAM0_BEAR 0x024 369 #define DCRN_SRAM0_BESR0 0x025 370 #define DCRN_SRAM0_BESR1 0x026 371 #define DCRN_SRAM0_PMEG 0x027 372 #define DCRN_SRAM0_CID 0x028 373 #define DCRN_SRAM0_REVID 0x029 374 #define DCRN_SRAM0_DPC 0x02a 375 #define SRAM_DPC_ENABLE 0x80000000 376 377 /* L2 Cache Controller */ 378 #define DCRN_L2C0_CFG 0x030 379 #define L2C_CFG_L2M 0x80000000 380 #define L2C_CFG_ICU 0x40000000 381 #define L2C_CFG_DCU 0x20000000 382 #define L2C_CFG_DCW_MASK 0x1e000000 383 #define L2C_CFG_TPC 0x01000000 384 #define L2C_CFG_CPC 0x00800000 385 #define L2C_CFG_FRAN 0x00200000 386 #define L2C_CFG_SS_MASK 0x00180000 387 #define L2C_CFG_SS_256 0x00000000 388 #define L2C_CFG_CPIM 0x00040000 389 #define L2C_CFG_TPIM 0x00020000 390 #define L2C_CFG_LIM 0x00010000 391 #define L2C_CFG_PMUX_MASK 0x00007000 392 #define L2C_CFG_PMUX_SNP 0x00000000 393 #define L2C_CFG_PMUX_IF 0x00001000 394 #define L2C_CFG_PMUX_DF 0x00002000 395 #define L2C_CFG_PMUX_DS 0x00003000 396 #define L2C_CFG_PMIM 0x00000800 397 #define L2C_CFG_TPEI 0x00000400 398 #define L2C_CFG_CPEI 0x00000200 399 #define L2C_CFG_NAM 0x00000100 400 #define L2C_CFG_SMCM 0x00000080 401 #define L2C_CFG_NBRM 0x00000040 402 #define DCRN_L2C0_CMD 0x031 403 #define L2C_CMD_CLR 0x80000000 404 #define L2C_CMD_DIAG 0x40000000 405 #define L2C_CMD_INV 0x20000000 406 #define L2C_CMD_CCP 0x10000000 407 #define L2C_CMD_CTE 0x08000000 408 #define L2C_CMD_STRC 0x04000000 409 #define L2C_CMD_STPC 0x02000000 410 #define L2C_CMD_RPMC 0x01000000 411 #define L2C_CMD_HCC 0x00800000 412 #define DCRN_L2C0_ADDR 0x032 413 #define DCRN_L2C0_DATA 0x033 414 #define DCRN_L2C0_SR 0x034 415 #define L2C_SR_CC 0x80000000 416 #define L2C_SR_CPE 0x40000000 417 #define L2C_SR_TPE 0x20000000 418 #define L2C_SR_LRU 0x10000000 419 #define L2C_SR_PCS 0x08000000 420 #define DCRN_L2C0_REVID 0x035 421 #define DCRN_L2C0_SNP0 0x036 422 #define DCRN_L2C0_SNP1 0x037 423 #define L2C_SNP_BA_MASK 0xffff0000 424 #define L2C_SNP_SSR_MASK 0x0000f000 425 #define L2C_SNP_SSR_32G 0x0000f000 426 #define L2C_SNP_ESR 0x00000800 427 #endif /* CONFIG_440GX */ 428 429 /* 430 * PCI-X definitions 431 */ 432 #define PCIX0_REG_BASE 0x20ec80000ULL 433 #define PCIX0_REG_SIZE 0x200 434 435 #define PCIX0_VENDID 0x000 436 #define PCIX0_DEVID 0x002 437 #define PCIX0_COMMAND 0x004 438 #define PCIX0_STATUS 0x006 439 #define PCIX0_REVID 0x008 440 #define PCIX0_CLS 0x009 441 #define PCIX0_CACHELS 0x00c 442 #define PCIX0_LATTIM 0x00d 443 #define PCIX0_HDTYPE 0x00e 444 #define PCIX0_BIST 0x00f 445 #define PCIX0_BAR0L 0x010 446 #define PCIX0_BAR0H 0x014 447 #define PCIX0_BAR1 0x018 448 #define PCIX0_BAR2L 0x01c 449 #define PCIX0_BAR2H 0x020 450 #define PCIX0_BAR3 0x024 451 #define PCIX0_CISPTR 0x028 452 #define PCIX0_SBSYSVID 0x02c 453 #define PCIX0_SBSYSID 0x02e 454 #define PCIX0_EROMBA 0x030 455 #define PCIX0_CAP 0x034 456 #define PCIX0_RES0 0x035 457 #define PCIX0_RES1 0x036 458 #define PCIX0_RES2 0x038 459 #define PCIX0_INTLN 0x03c 460 #define PCIX0_INTPN 0x03d 461 #define PCIX0_MINGNT 0x03e 462 #define PCIX0_MAXLTNCY 0x03f 463 #define PCIX0_BRDGOPT1 0x040 464 #define PCIX0_BRDGOPT2 0x044 465 #define PCIX0_ERREN 0x050 466 #define PCIX0_ERRSTS 0x054 467 #define PCIX0_PLBBESR 0x058 468 #define PCIX0_PLBBEARL 0x05c 469 #define PCIX0_PLBBEARH 0x060 470 #define PCIX0_POM0LAL 0x068 471 #define PCIX0_POM0LAH 0x06c 472 #define PCIX0_POM0SA 0x070 473 #define PCIX0_POM0PCIAL 0x074 474 #define PCIX0_POM0PCIAH 0x078 475 #define PCIX0_POM1LAL 0x07c 476 #define PCIX0_POM1LAH 0x080 477 #define PCIX0_POM1SA 0x084 478 #define PCIX0_POM1PCIAL 0x088 479 #define PCIX0_POM1PCIAH 0x08c 480 #define PCIX0_POM2SA 0x090 481 #define PCIX0_PIM0SAL 0x098 482 #define PCIX0_PIM0SA PCIX0_PIM0SAL 483 #define PCIX0_PIM0LAL 0x09c 484 #define PCIX0_PIM0LAH 0x0a0 485 #define PCIX0_PIM1SA 0x0a4 486 #define PCIX0_PIM1LAL 0x0a8 487 #define PCIX0_PIM1LAH 0x0ac 488 #define PCIX0_PIM2SAL 0x0b0 489 #define PCIX0_PIM2SA PCIX0_PIM2SAL 490 #define PCIX0_PIM2LAL 0x0b4 491 #define PCIX0_PIM2LAH 0x0b8 492 #define PCIX0_OMCAPID 0x0c0 493 #define PCIX0_OMNIPTR 0x0c1 494 #define PCIX0_OMMC 0x0c2 495 #define PCIX0_OMMA 0x0c4 496 #define PCIX0_OMMUA 0x0c8 497 #define PCIX0_OMMDATA 0x0cc 498 #define PCIX0_OMMEOI 0x0ce 499 #define PCIX0_PMCAPID 0x0d0 500 #define PCIX0_PMNIPTR 0x0d1 501 #define PCIX0_PMC 0x0d2 502 #define PCIX0_PMCSR 0x0d4 503 #define PCIX0_PMCSRBSE 0x0d6 504 #define PCIX0_PMDATA 0x0d7 505 #define PCIX0_PMSCRR 0x0d8 506 #define PCIX0_CAPID 0x0dc 507 #define PCIX0_NIPTR 0x0dd 508 #define PCIX0_CMD 0x0de 509 #define PCIX0_STS 0x0e0 510 #define PCIX0_IDR 0x0e4 511 #define PCIX0_CID 0x0e8 512 #define PCIX0_RID 0x0ec 513 #define PCIX0_PIM0SAH 0x0f8 514 #define PCIX0_PIM2SAH 0x0fc 515 #define PCIX0_MSGIL 0x100 516 #define PCIX0_MSGIH 0x104 517 #define PCIX0_MSGOL 0x108 518 #define PCIX0_MSGOH 0x10c 519 #define PCIX0_IM 0x1f8 520 521 #define IIC_OWN 0x55 522 #define IIC_CLOCK 50 523 524 #undef NR_UICS 525 #define NR_UICS 2 526 #define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */ 527 528 #define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i] 529 530 #include <asm/ibm4xx.h> 531 532 #endif /* __ASSEMBLY__ */ 533 #endif /* __ASM_IBM44x_H__ */ 534 #endif /* __KERNEL__ */ 535