1 /* 2 * arch/ppc/platforms/ibm440gp.h 3 * 4 * PPC440GP definitions 5 * 6 * Roland Dreier <roland@digitalvampire.org> 7 * 8 * Copyright 2002 Roland Dreier 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 * This file contains code that was originally in the files ibm44x.h 16 * and ebony.h, which were written by Matt Porter of MontaVista Software Inc. 17 */ 18 19 #ifdef __KERNEL__ 20 #ifndef __PPC_PLATFORMS_IBM440GP_H 21 #define __PPC_PLATFORMS_IBM440GP_H 22 23 #include <linux/config.h> 24 25 #include <asm/ibm44x.h> 26 27 #define EMAC_NUMS 2 28 #define UART_NUMS 2 29 #define ZMII_NUMS 1 30 #define IIC_NUMS 2 31 #define IIC0_IRQ 2 32 #define IIC1_IRQ 3 33 #define GPIO_NUMS 1 34 35 /* UART location */ 36 #define PPC440GP_UART0_ADDR 0x0000000140000200ULL 37 #define PPC440GP_UART1_ADDR 0x0000000140000300ULL 38 #define UART0_INT 0 39 #define UART1_INT 1 40 41 /* EMAC location */ 42 #define PPC440GP_EMAC0_ADDR 0x0000000140000800ULL 43 #define PPC440GP_EMAC1_ADDR 0x0000000140000900ULL 44 #define PPC440GP_EMAC_SIZE 0x70 45 46 /* EMAC IRQ's */ 47 #define BL_MAC_WOL 61 /* WOL */ 48 #define BL_MAC_WOL1 63 /* WOL */ 49 #define BL_MAL_SERR 32 /* MAL SERR */ 50 #define BL_MAL_TXDE 33 /* MAL TXDE */ 51 #define BL_MAL_RXDE 34 /* MAL RXDE */ 52 #define BL_MAL_TXEOB 10 /* MAL TX EOB */ 53 #define BL_MAL_RXEOB 11 /* MAL RX EOB */ 54 #define BL_MAC_ETH0 60 /* MAC */ 55 #define BL_MAC_ETH1 62 /* MAC */ 56 57 /* ZMII location */ 58 #define PPC440GP_ZMII_ADDR 0x0000000140000780ULL 59 #define PPC440GP_ZMII_SIZE 0x0c 60 61 /* I2C location */ 62 #define PPC440GP_IIC0_ADDR 0x40000400 63 #define PPC440GP_IIC1_ADDR 0x40000500 64 65 /* GPIO location */ 66 #define PPC440GP_GPIO0_ADDR 0x0000000140000700ULL 67 68 /* Clock and Power Management */ 69 #define IBM_CPM_IIC0 0x80000000 /* IIC interface */ 70 #define IBM_CPM_IIC1 0x40000000 /* IIC interface */ 71 #define IBM_CPM_PCI 0x20000000 /* PCI bridge */ 72 #define IBM_CPM_CPU 0x02000000 /* processor core */ 73 #define IBM_CPM_DMA 0x01000000 /* DMA controller */ 74 #define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ 75 #define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ 76 #define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ 77 #define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ 78 #define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ 79 #define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ 80 #define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ 81 #define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ 82 #define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ 83 #define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ 84 #define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ 85 #define IBM_CPM_UART0 0x00000200 /* serial port 0 */ 86 #define IBM_CPM_UART1 0x00000100 /* serial port 1 */ 87 #define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ 88 #define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ 89 90 #define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ 91 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ 92 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ 93 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI) 94 95 #define PPC440GP_OPB_BASE_START 0x0000000140000000ULL 96 97 /* 98 * Serial port defines 99 */ 100 #define RS_TABLE_SIZE 2 101 102 #endif /* __PPC_PLATFORMS_IBM440GP_H */ 103 #endif /* __KERNEL__ */ 104