1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __INTEL_DISPLAY_POWER_H__
7 #define __INTEL_DISPLAY_POWER_H__
8 
9 #include "intel_runtime_pm.h"
10 
11 enum aux_ch;
12 enum dpio_channel;
13 enum dpio_phy;
14 enum port;
15 struct drm_i915_private;
16 struct i915_power_well;
17 struct intel_encoder;
18 
19 /*
20  * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
21  * consecutive, so that the pipe,transcoder,port -> power domain macros
22  * work correctly.
23  */
24 enum intel_display_power_domain {
25 	POWER_DOMAIN_DISPLAY_CORE,
26 	POWER_DOMAIN_PIPE_A,
27 	POWER_DOMAIN_PIPE_B,
28 	POWER_DOMAIN_PIPE_C,
29 	POWER_DOMAIN_PIPE_D,
30 	POWER_DOMAIN_PIPE_PANEL_FITTER_A,
31 	POWER_DOMAIN_PIPE_PANEL_FITTER_B,
32 	POWER_DOMAIN_PIPE_PANEL_FITTER_C,
33 	POWER_DOMAIN_PIPE_PANEL_FITTER_D,
34 	POWER_DOMAIN_TRANSCODER_A,
35 	POWER_DOMAIN_TRANSCODER_B,
36 	POWER_DOMAIN_TRANSCODER_C,
37 	POWER_DOMAIN_TRANSCODER_D,
38 	POWER_DOMAIN_TRANSCODER_EDP,
39 	POWER_DOMAIN_TRANSCODER_DSI_A,
40 	POWER_DOMAIN_TRANSCODER_DSI_C,
41 
42 	/* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
43 	POWER_DOMAIN_TRANSCODER_VDSC_PW2,
44 
45 	POWER_DOMAIN_PORT_DDI_LANES_A,
46 	POWER_DOMAIN_PORT_DDI_LANES_B,
47 	POWER_DOMAIN_PORT_DDI_LANES_C,
48 	POWER_DOMAIN_PORT_DDI_LANES_D,
49 	POWER_DOMAIN_PORT_DDI_LANES_E,
50 	POWER_DOMAIN_PORT_DDI_LANES_F,
51 
52 	POWER_DOMAIN_PORT_DDI_LANES_TC1,
53 	POWER_DOMAIN_PORT_DDI_LANES_TC2,
54 	POWER_DOMAIN_PORT_DDI_LANES_TC3,
55 	POWER_DOMAIN_PORT_DDI_LANES_TC4,
56 	POWER_DOMAIN_PORT_DDI_LANES_TC5,
57 	POWER_DOMAIN_PORT_DDI_LANES_TC6,
58 
59 	POWER_DOMAIN_PORT_DDI_IO_A,
60 	POWER_DOMAIN_PORT_DDI_IO_B,
61 	POWER_DOMAIN_PORT_DDI_IO_C,
62 	POWER_DOMAIN_PORT_DDI_IO_D,
63 	POWER_DOMAIN_PORT_DDI_IO_E,
64 	POWER_DOMAIN_PORT_DDI_IO_F,
65 
66 	POWER_DOMAIN_PORT_DDI_IO_TC1,
67 	POWER_DOMAIN_PORT_DDI_IO_TC2,
68 	POWER_DOMAIN_PORT_DDI_IO_TC3,
69 	POWER_DOMAIN_PORT_DDI_IO_TC4,
70 	POWER_DOMAIN_PORT_DDI_IO_TC5,
71 	POWER_DOMAIN_PORT_DDI_IO_TC6,
72 
73 	POWER_DOMAIN_PORT_DSI,
74 	POWER_DOMAIN_PORT_CRT,
75 	POWER_DOMAIN_PORT_OTHER,
76 	POWER_DOMAIN_VGA,
77 	POWER_DOMAIN_AUDIO_MMIO,
78 	POWER_DOMAIN_AUDIO_PLAYBACK,
79 	POWER_DOMAIN_AUX_A,
80 	POWER_DOMAIN_AUX_B,
81 	POWER_DOMAIN_AUX_C,
82 	POWER_DOMAIN_AUX_D,
83 	POWER_DOMAIN_AUX_E,
84 	POWER_DOMAIN_AUX_F,
85 
86 	POWER_DOMAIN_AUX_USBC1,
87 	POWER_DOMAIN_AUX_USBC2,
88 	POWER_DOMAIN_AUX_USBC3,
89 	POWER_DOMAIN_AUX_USBC4,
90 	POWER_DOMAIN_AUX_USBC5,
91 	POWER_DOMAIN_AUX_USBC6,
92 
93 	POWER_DOMAIN_AUX_IO_A,
94 
95 	POWER_DOMAIN_AUX_TBT1,
96 	POWER_DOMAIN_AUX_TBT2,
97 	POWER_DOMAIN_AUX_TBT3,
98 	POWER_DOMAIN_AUX_TBT4,
99 	POWER_DOMAIN_AUX_TBT5,
100 	POWER_DOMAIN_AUX_TBT6,
101 
102 	POWER_DOMAIN_GMBUS,
103 	POWER_DOMAIN_MODESET,
104 	POWER_DOMAIN_GT_IRQ,
105 	POWER_DOMAIN_DC_OFF,
106 	POWER_DOMAIN_TC_COLD_OFF,
107 	POWER_DOMAIN_INIT,
108 
109 	POWER_DOMAIN_NUM,
110 	POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,
111 };
112 
113 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
114 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
115 		((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
116 #define POWER_DOMAIN_TRANSCODER(tran) \
117 	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
118 	 (tran) + POWER_DOMAIN_TRANSCODER_A)
119 
120 struct intel_power_domain_mask {
121 	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
122 };
123 
124 struct i915_power_domains {
125 	/*
126 	 * Power wells needed for initialization at driver init and suspend
127 	 * time are on. They are kept on until after the first modeset.
128 	 */
129 	bool initializing;
130 	bool display_core_suspended;
131 	int power_well_count;
132 
133 	intel_wakeref_t init_wakeref;
134 	intel_wakeref_t disable_wakeref;
135 
136 	struct mutex lock;
137 	int domain_use_count[POWER_DOMAIN_NUM];
138 
139 	struct delayed_work async_put_work;
140 	intel_wakeref_t async_put_wakeref;
141 	struct intel_power_domain_mask async_put_domains[2];
142 
143 	struct i915_power_well *power_wells;
144 };
145 
146 struct intel_display_power_domain_set {
147 	struct intel_power_domain_mask mask;
148 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
149 	intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
150 #endif
151 };
152 
153 #define for_each_power_domain(__domain, __mask)				\
154 	for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++)	\
155 		for_each_if(test_bit((__domain), (__mask)->bits))
156 
157 int intel_power_domains_init(struct drm_i915_private *dev_priv);
158 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
159 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
160 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
161 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
162 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
163 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
164 				 enum i915_drm_suspend_mode);
165 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
166 void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);
167 
168 void intel_display_power_suspend_late(struct drm_i915_private *i915);
169 void intel_display_power_resume_early(struct drm_i915_private *i915);
170 void intel_display_power_suspend(struct drm_i915_private *i915);
171 void intel_display_power_resume(struct drm_i915_private *i915);
172 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
173 					     u32 state);
174 
175 const char *
176 intel_display_power_domain_str(enum intel_display_power_domain domain);
177 
178 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
179 				    enum intel_display_power_domain domain);
180 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
181 				      enum intel_display_power_domain domain);
182 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
183 					enum intel_display_power_domain domain);
184 intel_wakeref_t
185 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
186 				   enum intel_display_power_domain domain);
187 void __intel_display_power_put_async(struct drm_i915_private *i915,
188 				     enum intel_display_power_domain domain,
189 				     intel_wakeref_t wakeref);
190 void intel_display_power_flush_work(struct drm_i915_private *i915);
191 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
192 void intel_display_power_put(struct drm_i915_private *dev_priv,
193 			     enum intel_display_power_domain domain,
194 			     intel_wakeref_t wakeref);
195 static inline void
intel_display_power_put_async(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)196 intel_display_power_put_async(struct drm_i915_private *i915,
197 			      enum intel_display_power_domain domain,
198 			      intel_wakeref_t wakeref)
199 {
200 	__intel_display_power_put_async(i915, domain, wakeref);
201 }
202 #else
203 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
204 				       enum intel_display_power_domain domain);
205 
206 static inline void
intel_display_power_put(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)207 intel_display_power_put(struct drm_i915_private *i915,
208 			enum intel_display_power_domain domain,
209 			intel_wakeref_t wakeref)
210 {
211 	intel_display_power_put_unchecked(i915, domain);
212 }
213 
214 static inline void
intel_display_power_put_async(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)215 intel_display_power_put_async(struct drm_i915_private *i915,
216 			      enum intel_display_power_domain domain,
217 			      intel_wakeref_t wakeref)
218 {
219 	__intel_display_power_put_async(i915, domain, -1);
220 }
221 #endif
222 
223 void
224 intel_display_power_get_in_set(struct drm_i915_private *i915,
225 			       struct intel_display_power_domain_set *power_domain_set,
226 			       enum intel_display_power_domain domain);
227 
228 bool
229 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
230 					  struct intel_display_power_domain_set *power_domain_set,
231 					  enum intel_display_power_domain domain);
232 
233 void
234 intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
235 				    struct intel_display_power_domain_set *power_domain_set,
236 				    struct intel_power_domain_mask *mask);
237 
238 static inline void
intel_display_power_put_all_in_set(struct drm_i915_private * i915,struct intel_display_power_domain_set * power_domain_set)239 intel_display_power_put_all_in_set(struct drm_i915_private *i915,
240 				   struct intel_display_power_domain_set *power_domain_set)
241 {
242 	intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
243 }
244 
245 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
246 
247 enum intel_display_power_domain
248 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port);
249 enum intel_display_power_domain
250 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
251 enum intel_display_power_domain
252 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
253 enum intel_display_power_domain
254 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
255 
256 /*
257  * FIXME: We should probably switch this to a 0-based scheme to be consistent
258  * with how we now name/number DBUF_CTL instances.
259  */
260 enum dbuf_slice {
261 	DBUF_S1,
262 	DBUF_S2,
263 	DBUF_S3,
264 	DBUF_S4,
265 	I915_MAX_DBUF_SLICES
266 };
267 
268 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
269 			     u8 req_slices);
270 
271 #define with_intel_display_power(i915, domain, wf) \
272 	for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
273 	     intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
274 
275 #define with_intel_display_power_if_enabled(i915, domain, wf) \
276 	for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \
277 	     intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
278 
279 #endif /* __INTEL_DISPLAY_POWER_H__ */
280