1 /*
2  *  linux/include/asm-arm/arch-rpc/hardware.h
3  *
4  *  Copyright (C) 1996-1999 Russell King.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  *  This file contains the hardware definitions of the RiscPC series machines.
11  */
12 #ifndef __ASM_ARCH_HARDWARE_H
13 #define __ASM_ARCH_HARDWARE_H
14 
15 #include <asm/arch/memory.h>
16 
17 /*
18  * What hardware must be present
19  */
20 #define HAS_IOMD
21 #define HAS_VIDC20
22 
23 /* Hardware addresses of major areas.
24  *  *_START is the physical address
25  *  *_SIZE  is the size of the region
26  *  *_BASE  is the virtual address
27  */
28 #define RAM_SIZE		0x10000000
29 #define RAM_START		0x10000000
30 
31 #define EASI_SIZE		0x08000000	/* EASI I/O */
32 #define EASI_START		0x08000000
33 #define EASI_BASE		0xe5000000
34 
35 #define IO_START		0x03000000	/* I/O */
36 #define IO_SIZE			0x01000000
37 #define IO_BASE			0xe0000000
38 
39 #define SCREEN_START		0x02000000	/* VRAM */
40 #define SCREEN_END		0xdfc00000
41 #define SCREEN_BASE		0xdf800000
42 
43 #define FLUSH_BASE		0xdf000000
44 #define UNCACHEABLE_ADDR	0xdf010000
45 
46 /*
47  * IO Addresses
48  */
49 #define VIDC_BASE		0xe0400000
50 #define EXPMASK_BASE		0xe0360000
51 #define IOMD_BASE		0xe0200000
52 #define IOC_BASE		0xe0200000
53 #define PCIO_BASE		0xe0010000
54 #define FLOPPYDMA_BASE		0xe002a000
55 
56 #define FLUSH_BASE_PHYS		0x00000000	/* ROM */
57 
58 #define vidc_writel(val)	__raw_writel(val, VIDC_BASE)
59 
60 #define IO_EC_EASI_BASE		0x81400000
61 #define IO_EC_IOC4_BASE		0x8009c000
62 #define IO_EC_IOC_BASE		0x80090000
63 #define IO_EC_MEMC8_BASE	0x8000ac00
64 #define IO_EC_MEMC_BASE		0x80000000
65 
66 #define NETSLOT_BASE		0x0302b000
67 #define NETSLOT_SIZE		0x00001000
68 
69 #define PODSLOT_IOC0_BASE	0x03240000
70 #define PODSLOT_IOC4_BASE	0x03270000
71 #define PODSLOT_IOC_SIZE	(1 << 14)
72 #define PODSLOT_MEMC_BASE	0x03000000
73 #define PODSLOT_MEMC_SIZE	(1 << 14)
74 #define PODSLOT_EASI_BASE	0x08000000
75 #define PODSLOT_EASI_SIZE	(1 << 24)
76 
77 #define	EXPMASK_STATUS		(EXPMASK_BASE + 0x00)
78 #define EXPMASK_ENABLE		(EXPMASK_BASE + 0x04)
79 
80 #endif
81