1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2021 Xilinx
6 *
7 * Michal Simek <michal.simek@amd.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13 #ifndef __FIRMWARE_ZYNQMP_H__
14 #define __FIRMWARE_ZYNQMP_H__
15 #include <linux/types.h>
16
17 #include <linux/err.h>
18
19 #define ZYNQMP_PM_VERSION_MAJOR 1
20 #define ZYNQMP_PM_VERSION_MINOR 0
21
22 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
23 ZYNQMP_PM_VERSION_MINOR)
24
25 #define ZYNQMP_TZ_VERSION_MAJOR 1
26 #define ZYNQMP_TZ_VERSION_MINOR 0
27
28 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
29 ZYNQMP_TZ_VERSION_MINOR)
30
31 /* SMC SIP service Call Function Identifier Prefix */
32 #define PM_SIP_SVC 0xC2000000
33
34 /* PM API versions */
35 #define PM_API_VERSION_2 2
36
37 #define PM_PINCTRL_PARAM_SET_VERSION 2
38
39 #define ZYNQMP_FAMILY_CODE 0x23
40 #define VERSAL_FAMILY_CODE 0x26
41
42 /* When all subfamily of platform need to support */
43 #define ALL_SUB_FAMILY_CODE 0x00
44 #define VERSAL_SUB_FAMILY_CODE 0x01
45 #define VERSALNET_SUB_FAMILY_CODE 0x03
46
47 #define FAMILY_CODE_MASK GENMASK(27, 21)
48 #define SUB_FAMILY_CODE_MASK GENMASK(20, 19)
49
50 /* ATF only commands */
51 #define TF_A_PM_REGISTER_SGI 0xa04
52 #define PM_GET_TRUSTZONE_VERSION 0xa03
53 #define PM_SET_SUSPEND_MODE 0xa02
54 #define GET_CALLBACK_DATA 0xa01
55
56 /* Number of 32bits values in payload */
57 #define PAYLOAD_ARG_CNT 4U
58
59 /* Number of arguments for a callback */
60 #define CB_ARG_CNT 4
61
62 /* Payload size (consists of callback API ID + arguments) */
63 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
64
65 #define ZYNQMP_PM_MAX_QOS 100U
66
67 #define GSS_NUM_REGS (4)
68
69 /* Node capabilities */
70 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
71 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
72 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
73 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
74
75 /* Loader commands */
76 #define PM_LOAD_PDI 0x701
77 #define PDI_SRC_DDR 0xF
78
79 /*
80 * Firmware FPGA Manager flags
81 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
82 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
83 */
84 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
85 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
86
87 /* FPGA Status Reg */
88 #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U
89 #define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U
90
91 /*
92 * Node IDs for the Error Events.
93 */
94 #define EVENT_ERROR_PMC_ERR1 (0x28100000U)
95 #define EVENT_ERROR_PMC_ERR2 (0x28104000U)
96 #define EVENT_ERROR_PSM_ERR1 (0x28108000U)
97 #define EVENT_ERROR_PSM_ERR2 (0x2810C000U)
98
99 /* ZynqMP SD tap delay tuning */
100 #define SD_ITAPDLY 0xFF180314
101 #define SD_OTAPDLYSEL 0xFF180318
102
103 enum pm_api_cb_id {
104 PM_INIT_SUSPEND_CB = 30,
105 PM_ACKNOWLEDGE_CB = 31,
106 PM_NOTIFY_CB = 32,
107 };
108
109 enum pm_api_id {
110 PM_GET_API_VERSION = 1,
111 PM_REGISTER_NOTIFIER = 5,
112 PM_FORCE_POWERDOWN = 8,
113 PM_REQUEST_WAKEUP = 10,
114 PM_SYSTEM_SHUTDOWN = 12,
115 PM_REQUEST_NODE = 13,
116 PM_RELEASE_NODE = 14,
117 PM_SET_REQUIREMENT = 15,
118 PM_RESET_ASSERT = 17,
119 PM_RESET_GET_STATUS = 18,
120 PM_MMIO_WRITE = 19,
121 PM_MMIO_READ = 20,
122 PM_PM_INIT_FINALIZE = 21,
123 PM_FPGA_LOAD = 22,
124 PM_FPGA_GET_STATUS = 23,
125 PM_GET_CHIPID = 24,
126 PM_SECURE_SHA = 26,
127 PM_PINCTRL_REQUEST = 28,
128 PM_PINCTRL_RELEASE = 29,
129 PM_PINCTRL_GET_FUNCTION = 30,
130 PM_PINCTRL_SET_FUNCTION = 31,
131 PM_PINCTRL_CONFIG_PARAM_GET = 32,
132 PM_PINCTRL_CONFIG_PARAM_SET = 33,
133 PM_IOCTL = 34,
134 PM_QUERY_DATA = 35,
135 PM_CLOCK_ENABLE = 36,
136 PM_CLOCK_DISABLE = 37,
137 PM_CLOCK_GETSTATE = 38,
138 PM_CLOCK_SETDIVIDER = 39,
139 PM_CLOCK_GETDIVIDER = 40,
140 PM_CLOCK_SETRATE = 41,
141 PM_CLOCK_GETRATE = 42,
142 PM_CLOCK_SETPARENT = 43,
143 PM_CLOCK_GETPARENT = 44,
144 PM_FPGA_READ = 46,
145 PM_SECURE_AES = 47,
146 PM_FEATURE_CHECK = 63,
147 };
148
149 /* PMU-FW return status codes */
150 enum pm_ret_status {
151 XST_PM_SUCCESS = 0,
152 XST_PM_NO_FEATURE = 19,
153 XST_PM_INTERNAL = 2000,
154 XST_PM_CONFLICT = 2001,
155 XST_PM_NO_ACCESS = 2002,
156 XST_PM_INVALID_NODE = 2003,
157 XST_PM_DOUBLE_REQ = 2004,
158 XST_PM_ABORT_SUSPEND = 2005,
159 XST_PM_MULT_USER = 2008,
160 };
161
162 enum pm_ioctl_id {
163 IOCTL_GET_RPU_OPER_MODE = 0,
164 IOCTL_SET_RPU_OPER_MODE = 1,
165 IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
166 IOCTL_TCM_COMB_CONFIG = 3,
167 IOCTL_SET_TAPDELAY_BYPASS = 4,
168 IOCTL_SD_DLL_RESET = 6,
169 IOCTL_SET_SD_TAPDELAY = 7,
170 IOCTL_SET_PLL_FRAC_MODE = 8,
171 IOCTL_GET_PLL_FRAC_MODE = 9,
172 IOCTL_SET_PLL_FRAC_DATA = 10,
173 IOCTL_GET_PLL_FRAC_DATA = 11,
174 IOCTL_WRITE_GGS = 12,
175 IOCTL_READ_GGS = 13,
176 IOCTL_WRITE_PGGS = 14,
177 IOCTL_READ_PGGS = 15,
178 /* Set healthy bit value */
179 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
180 IOCTL_OSPI_MUX_SELECT = 21,
181 /* Register SGI to ATF */
182 IOCTL_REGISTER_SGI = 25,
183 /* Runtime feature configuration */
184 IOCTL_SET_FEATURE_CONFIG = 26,
185 IOCTL_GET_FEATURE_CONFIG = 27,
186 /* Dynamic SD/GEM configuration */
187 IOCTL_SET_SD_CONFIG = 30,
188 IOCTL_SET_GEM_CONFIG = 31,
189 };
190
191 enum pm_query_id {
192 PM_QID_INVALID = 0,
193 PM_QID_CLOCK_GET_NAME = 1,
194 PM_QID_CLOCK_GET_TOPOLOGY = 2,
195 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
196 PM_QID_CLOCK_GET_PARENTS = 4,
197 PM_QID_CLOCK_GET_ATTRIBUTES = 5,
198 PM_QID_PINCTRL_GET_NUM_PINS = 6,
199 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
200 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
201 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
202 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
203 PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
204 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
205 PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
206 };
207
208 enum rpu_oper_mode {
209 PM_RPU_MODE_LOCKSTEP = 0,
210 PM_RPU_MODE_SPLIT = 1,
211 };
212
213 enum rpu_boot_mem {
214 PM_RPU_BOOTMEM_LOVEC = 0,
215 PM_RPU_BOOTMEM_HIVEC = 1,
216 };
217
218 enum rpu_tcm_comb {
219 PM_RPU_TCM_SPLIT = 0,
220 PM_RPU_TCM_COMB = 1,
221 };
222
223 enum zynqmp_pm_reset_action {
224 PM_RESET_ACTION_RELEASE = 0,
225 PM_RESET_ACTION_ASSERT = 1,
226 PM_RESET_ACTION_PULSE = 2,
227 };
228
229 enum zynqmp_pm_reset {
230 ZYNQMP_PM_RESET_START = 1000,
231 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
232 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
233 ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
234 ZYNQMP_PM_RESET_DP = 1003,
235 ZYNQMP_PM_RESET_SWDT_CRF = 1004,
236 ZYNQMP_PM_RESET_AFI_FM5 = 1005,
237 ZYNQMP_PM_RESET_AFI_FM4 = 1006,
238 ZYNQMP_PM_RESET_AFI_FM3 = 1007,
239 ZYNQMP_PM_RESET_AFI_FM2 = 1008,
240 ZYNQMP_PM_RESET_AFI_FM1 = 1009,
241 ZYNQMP_PM_RESET_AFI_FM0 = 1010,
242 ZYNQMP_PM_RESET_GDMA = 1011,
243 ZYNQMP_PM_RESET_GPU_PP1 = 1012,
244 ZYNQMP_PM_RESET_GPU_PP0 = 1013,
245 ZYNQMP_PM_RESET_GPU = 1014,
246 ZYNQMP_PM_RESET_GT = 1015,
247 ZYNQMP_PM_RESET_SATA = 1016,
248 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
249 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
250 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
251 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
252 ZYNQMP_PM_RESET_APU_L2 = 1021,
253 ZYNQMP_PM_RESET_ACPU3 = 1022,
254 ZYNQMP_PM_RESET_ACPU2 = 1023,
255 ZYNQMP_PM_RESET_ACPU1 = 1024,
256 ZYNQMP_PM_RESET_ACPU0 = 1025,
257 ZYNQMP_PM_RESET_DDR = 1026,
258 ZYNQMP_PM_RESET_APM_FPD = 1027,
259 ZYNQMP_PM_RESET_SOFT = 1028,
260 ZYNQMP_PM_RESET_GEM0 = 1029,
261 ZYNQMP_PM_RESET_GEM1 = 1030,
262 ZYNQMP_PM_RESET_GEM2 = 1031,
263 ZYNQMP_PM_RESET_GEM3 = 1032,
264 ZYNQMP_PM_RESET_QSPI = 1033,
265 ZYNQMP_PM_RESET_UART0 = 1034,
266 ZYNQMP_PM_RESET_UART1 = 1035,
267 ZYNQMP_PM_RESET_SPI0 = 1036,
268 ZYNQMP_PM_RESET_SPI1 = 1037,
269 ZYNQMP_PM_RESET_SDIO0 = 1038,
270 ZYNQMP_PM_RESET_SDIO1 = 1039,
271 ZYNQMP_PM_RESET_CAN0 = 1040,
272 ZYNQMP_PM_RESET_CAN1 = 1041,
273 ZYNQMP_PM_RESET_I2C0 = 1042,
274 ZYNQMP_PM_RESET_I2C1 = 1043,
275 ZYNQMP_PM_RESET_TTC0 = 1044,
276 ZYNQMP_PM_RESET_TTC1 = 1045,
277 ZYNQMP_PM_RESET_TTC2 = 1046,
278 ZYNQMP_PM_RESET_TTC3 = 1047,
279 ZYNQMP_PM_RESET_SWDT_CRL = 1048,
280 ZYNQMP_PM_RESET_NAND = 1049,
281 ZYNQMP_PM_RESET_ADMA = 1050,
282 ZYNQMP_PM_RESET_GPIO = 1051,
283 ZYNQMP_PM_RESET_IOU_CC = 1052,
284 ZYNQMP_PM_RESET_TIMESTAMP = 1053,
285 ZYNQMP_PM_RESET_RPU_R50 = 1054,
286 ZYNQMP_PM_RESET_RPU_R51 = 1055,
287 ZYNQMP_PM_RESET_RPU_AMBA = 1056,
288 ZYNQMP_PM_RESET_OCM = 1057,
289 ZYNQMP_PM_RESET_RPU_PGE = 1058,
290 ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
291 ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
292 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
293 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
294 ZYNQMP_PM_RESET_USB0_APB = 1063,
295 ZYNQMP_PM_RESET_USB1_APB = 1064,
296 ZYNQMP_PM_RESET_IPI = 1065,
297 ZYNQMP_PM_RESET_APM_LPD = 1066,
298 ZYNQMP_PM_RESET_RTC = 1067,
299 ZYNQMP_PM_RESET_SYSMON = 1068,
300 ZYNQMP_PM_RESET_AFI_FM6 = 1069,
301 ZYNQMP_PM_RESET_LPD_SWDT = 1070,
302 ZYNQMP_PM_RESET_FPD = 1071,
303 ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
304 ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
305 ZYNQMP_PM_RESET_DBG_LPD = 1074,
306 ZYNQMP_PM_RESET_DBG_FPD = 1075,
307 ZYNQMP_PM_RESET_APLL = 1076,
308 ZYNQMP_PM_RESET_DPLL = 1077,
309 ZYNQMP_PM_RESET_VPLL = 1078,
310 ZYNQMP_PM_RESET_IOPLL = 1079,
311 ZYNQMP_PM_RESET_RPLL = 1080,
312 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
313 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
314 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
315 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
316 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
317 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
318 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
319 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
320 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
321 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
322 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
323 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
324 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
325 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
326 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
327 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
328 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
329 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
330 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
331 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
332 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
333 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
334 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
335 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
336 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
337 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
338 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
339 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
340 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
341 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
342 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
343 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
344 ZYNQMP_PM_RESET_RPU_LS = 1113,
345 ZYNQMP_PM_RESET_PS_ONLY = 1114,
346 ZYNQMP_PM_RESET_PL = 1115,
347 ZYNQMP_PM_RESET_PS_PL0 = 1116,
348 ZYNQMP_PM_RESET_PS_PL1 = 1117,
349 ZYNQMP_PM_RESET_PS_PL2 = 1118,
350 ZYNQMP_PM_RESET_PS_PL3 = 1119,
351 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
352 };
353
354 enum zynqmp_pm_suspend_reason {
355 SUSPEND_POWER_REQUEST = 201,
356 SUSPEND_ALERT = 202,
357 SUSPEND_SYSTEM_SHUTDOWN = 203,
358 };
359
360 enum zynqmp_pm_request_ack {
361 ZYNQMP_PM_REQUEST_ACK_NO = 1,
362 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
363 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
364 };
365
366 enum pm_node_id {
367 NODE_SD_0 = 39,
368 NODE_SD_1 = 40,
369 };
370
371 enum tap_delay_type {
372 PM_TAPDELAY_INPUT = 0,
373 PM_TAPDELAY_OUTPUT = 1,
374 };
375
376 enum dll_reset_type {
377 PM_DLL_RESET_ASSERT = 0,
378 PM_DLL_RESET_RELEASE = 1,
379 PM_DLL_RESET_PULSE = 2,
380 };
381
382 enum pm_pinctrl_config_param {
383 PM_PINCTRL_CONFIG_SLEW_RATE = 0,
384 PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
385 PM_PINCTRL_CONFIG_PULL_CTRL = 2,
386 PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
387 PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
388 PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
389 PM_PINCTRL_CONFIG_TRI_STATE = 6,
390 PM_PINCTRL_CONFIG_MAX = 7,
391 };
392
393 enum pm_pinctrl_slew_rate {
394 PM_PINCTRL_SLEW_RATE_FAST = 0,
395 PM_PINCTRL_SLEW_RATE_SLOW = 1,
396 };
397
398 enum pm_pinctrl_bias_status {
399 PM_PINCTRL_BIAS_DISABLE = 0,
400 PM_PINCTRL_BIAS_ENABLE = 1,
401 };
402
403 enum pm_pinctrl_pull_ctrl {
404 PM_PINCTRL_BIAS_PULL_DOWN = 0,
405 PM_PINCTRL_BIAS_PULL_UP = 1,
406 };
407
408 enum pm_pinctrl_schmitt_cmos {
409 PM_PINCTRL_INPUT_TYPE_CMOS = 0,
410 PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
411 };
412
413 enum pm_pinctrl_drive_strength {
414 PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
415 PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
416 PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
417 PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
418 };
419
420 enum pm_pinctrl_tri_state {
421 PM_PINCTRL_TRI_STATE_DISABLE = 0,
422 PM_PINCTRL_TRI_STATE_ENABLE = 1,
423 };
424
425 enum zynqmp_pm_shutdown_type {
426 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
427 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
428 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
429 };
430
431 enum zynqmp_pm_shutdown_subtype {
432 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
433 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
434 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
435 };
436
437 enum tap_delay_signal_type {
438 PM_TAPDELAY_NAND_DQS_IN = 0,
439 PM_TAPDELAY_NAND_DQS_OUT = 1,
440 PM_TAPDELAY_QSPI = 2,
441 PM_TAPDELAY_MAX = 3,
442 };
443
444 enum tap_delay_bypass_ctrl {
445 PM_TAPDELAY_BYPASS_DISABLE = 0,
446 PM_TAPDELAY_BYPASS_ENABLE = 1,
447 };
448
449 enum ospi_mux_select_type {
450 PM_OSPI_MUX_SEL_DMA = 0,
451 PM_OSPI_MUX_SEL_LINEAR = 1,
452 };
453
454 enum pm_feature_config_id {
455 PM_FEATURE_INVALID = 0,
456 PM_FEATURE_OVERTEMP_STATUS = 1,
457 PM_FEATURE_OVERTEMP_VALUE = 2,
458 PM_FEATURE_EXTWDT_STATUS = 3,
459 PM_FEATURE_EXTWDT_VALUE = 4,
460 };
461
462 /**
463 * enum pm_sd_config_type - PM SD configuration.
464 * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE
465 * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1
466 * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2
467 * @SD_CONFIG_FIXED: To set fixed config registers
468 */
469 enum pm_sd_config_type {
470 SD_CONFIG_EMMC_SEL = 1,
471 SD_CONFIG_BASECLK = 2,
472 SD_CONFIG_8BIT = 3,
473 SD_CONFIG_FIXED = 4,
474 };
475
476 /**
477 * enum pm_gem_config_type - PM GEM configuration.
478 * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register
479 * @GEM_CONFIG_FIXED: To set fixed config registers
480 */
481 enum pm_gem_config_type {
482 GEM_CONFIG_SGMII_MODE = 1,
483 GEM_CONFIG_FIXED = 2,
484 };
485
486 /**
487 * struct zynqmp_pm_query_data - PM query data
488 * @qid: query ID
489 * @arg1: Argument 1 of query data
490 * @arg2: Argument 2 of query data
491 * @arg3: Argument 3 of query data
492 */
493 struct zynqmp_pm_query_data {
494 u32 qid;
495 u32 arg1;
496 u32 arg2;
497 u32 arg3;
498 };
499
500 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
501 u32 arg2, u32 arg3, u32 *ret_payload);
502
503 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
504 int zynqmp_pm_get_api_version(u32 *version);
505 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
506 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
507 int zynqmp_pm_clock_enable(u32 clock_id);
508 int zynqmp_pm_clock_disable(u32 clock_id);
509 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
510 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
511 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
512 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
513 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
514 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
515 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
516 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
517 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
518 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
519 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
520 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
521 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
522 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
523 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
524 const enum zynqmp_pm_reset_action assert_flag);
525 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
526 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
527 int zynqmp_pm_bootmode_write(u32 ps_mode);
528 int zynqmp_pm_init_finalize(void);
529 int zynqmp_pm_set_suspend_mode(u32 mode);
530 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
531 const u32 qos, const enum zynqmp_pm_request_ack ack);
532 int zynqmp_pm_release_node(const u32 node);
533 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
534 const u32 qos,
535 const enum zynqmp_pm_request_ack ack);
536 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
537 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
538 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
539 int zynqmp_pm_fpga_get_status(u32 *value);
540 int zynqmp_pm_fpga_get_config_status(u32 *value);
541 int zynqmp_pm_write_ggs(u32 index, u32 value);
542 int zynqmp_pm_read_ggs(u32 index, u32 *value);
543 int zynqmp_pm_write_pggs(u32 index, u32 value);
544 int zynqmp_pm_read_pggs(u32 index, u32 *value);
545 int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
546 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
547 int zynqmp_pm_set_boot_health_status(u32 value);
548 int zynqmp_pm_pinctrl_request(const u32 pin);
549 int zynqmp_pm_pinctrl_release(const u32 pin);
550 int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
551 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
552 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
553 u32 *value);
554 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
555 u32 value);
556 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
557 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
558 const u32 wake, const u32 enable);
559 int zynqmp_pm_feature(const u32 api_id);
560 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
561 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
562 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
563 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
564 int zynqmp_pm_force_pwrdwn(const u32 target,
565 const enum zynqmp_pm_request_ack ack);
566 int zynqmp_pm_request_wake(const u32 node,
567 const bool set_addr,
568 const u64 address,
569 const enum zynqmp_pm_request_ack ack);
570 int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode);
571 int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode);
572 int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode);
573 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
574 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
575 u32 value);
576 #else
zynqmp_pm_get_api_version(u32 * version)577 static inline int zynqmp_pm_get_api_version(u32 *version)
578 {
579 return -ENODEV;
580 }
581
zynqmp_pm_get_chipid(u32 * idcode,u32 * version)582 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
583 {
584 return -ENODEV;
585 }
586
zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,u32 * out)587 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
588 u32 *out)
589 {
590 return -ENODEV;
591 }
592
zynqmp_pm_clock_enable(u32 clock_id)593 static inline int zynqmp_pm_clock_enable(u32 clock_id)
594 {
595 return -ENODEV;
596 }
597
zynqmp_pm_clock_disable(u32 clock_id)598 static inline int zynqmp_pm_clock_disable(u32 clock_id)
599 {
600 return -ENODEV;
601 }
602
zynqmp_pm_clock_getstate(u32 clock_id,u32 * state)603 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
604 {
605 return -ENODEV;
606 }
607
zynqmp_pm_clock_setdivider(u32 clock_id,u32 divider)608 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
609 {
610 return -ENODEV;
611 }
612
zynqmp_pm_clock_getdivider(u32 clock_id,u32 * divider)613 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
614 {
615 return -ENODEV;
616 }
617
zynqmp_pm_clock_setrate(u32 clock_id,u64 rate)618 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
619 {
620 return -ENODEV;
621 }
622
zynqmp_pm_clock_getrate(u32 clock_id,u64 * rate)623 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
624 {
625 return -ENODEV;
626 }
627
zynqmp_pm_clock_setparent(u32 clock_id,u32 parent_id)628 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
629 {
630 return -ENODEV;
631 }
632
zynqmp_pm_clock_getparent(u32 clock_id,u32 * parent_id)633 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
634 {
635 return -ENODEV;
636 }
637
zynqmp_pm_set_pll_frac_mode(u32 clk_id,u32 mode)638 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
639 {
640 return -ENODEV;
641 }
642
zynqmp_pm_get_pll_frac_mode(u32 clk_id,u32 * mode)643 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
644 {
645 return -ENODEV;
646 }
647
zynqmp_pm_set_pll_frac_data(u32 clk_id,u32 data)648 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
649 {
650 return -ENODEV;
651 }
652
zynqmp_pm_get_pll_frac_data(u32 clk_id,u32 * data)653 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
654 {
655 return -ENODEV;
656 }
657
zynqmp_pm_set_sd_tapdelay(u32 node_id,u32 type,u32 value)658 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
659 {
660 return -ENODEV;
661 }
662
zynqmp_pm_sd_dll_reset(u32 node_id,u32 type)663 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
664 {
665 return -ENODEV;
666 }
667
zynqmp_pm_ospi_mux_select(u32 dev_id,u32 select)668 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
669 {
670 return -ENODEV;
671 }
672
zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,const enum zynqmp_pm_reset_action assert_flag)673 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
674 const enum zynqmp_pm_reset_action assert_flag)
675 {
676 return -ENODEV;
677 }
678
zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,u32 * status)679 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
680 u32 *status)
681 {
682 return -ENODEV;
683 }
684
zynqmp_pm_bootmode_read(u32 * ps_mode)685 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
686 {
687 return -ENODEV;
688 }
689
zynqmp_pm_bootmode_write(u32 ps_mode)690 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
691 {
692 return -ENODEV;
693 }
694
zynqmp_pm_init_finalize(void)695 static inline int zynqmp_pm_init_finalize(void)
696 {
697 return -ENODEV;
698 }
699
zynqmp_pm_set_suspend_mode(u32 mode)700 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
701 {
702 return -ENODEV;
703 }
704
zynqmp_pm_request_node(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)705 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
706 const u32 qos,
707 const enum zynqmp_pm_request_ack ack)
708 {
709 return -ENODEV;
710 }
711
zynqmp_pm_release_node(const u32 node)712 static inline int zynqmp_pm_release_node(const u32 node)
713 {
714 return -ENODEV;
715 }
716
zynqmp_pm_set_requirement(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)717 static inline int zynqmp_pm_set_requirement(const u32 node,
718 const u32 capabilities,
719 const u32 qos,
720 const enum zynqmp_pm_request_ack ack)
721 {
722 return -ENODEV;
723 }
724
zynqmp_pm_aes_engine(const u64 address,u32 * out)725 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
726 {
727 return -ENODEV;
728 }
729
zynqmp_pm_sha_hash(const u64 address,const u32 size,const u32 flags)730 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
731 const u32 flags)
732 {
733 return -ENODEV;
734 }
735
zynqmp_pm_fpga_load(const u64 address,const u32 size,const u32 flags)736 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
737 const u32 flags)
738 {
739 return -ENODEV;
740 }
741
zynqmp_pm_fpga_get_status(u32 * value)742 static inline int zynqmp_pm_fpga_get_status(u32 *value)
743 {
744 return -ENODEV;
745 }
746
zynqmp_pm_fpga_get_config_status(u32 * value)747 static inline int zynqmp_pm_fpga_get_config_status(u32 *value)
748 {
749 return -ENODEV;
750 }
751
zynqmp_pm_write_ggs(u32 index,u32 value)752 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
753 {
754 return -ENODEV;
755 }
756
zynqmp_pm_read_ggs(u32 index,u32 * value)757 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
758 {
759 return -ENODEV;
760 }
761
zynqmp_pm_write_pggs(u32 index,u32 value)762 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
763 {
764 return -ENODEV;
765 }
766
zynqmp_pm_read_pggs(u32 index,u32 * value)767 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
768 {
769 return -ENODEV;
770 }
771
zynqmp_pm_set_tapdelay_bypass(u32 index,u32 value)772 static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
773 {
774 return -ENODEV;
775 }
776
zynqmp_pm_system_shutdown(const u32 type,const u32 subtype)777 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
778 {
779 return -ENODEV;
780 }
781
zynqmp_pm_set_boot_health_status(u32 value)782 static inline int zynqmp_pm_set_boot_health_status(u32 value)
783 {
784 return -ENODEV;
785 }
786
zynqmp_pm_pinctrl_request(const u32 pin)787 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
788 {
789 return -ENODEV;
790 }
791
zynqmp_pm_pinctrl_release(const u32 pin)792 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
793 {
794 return -ENODEV;
795 }
796
zynqmp_pm_pinctrl_get_function(const u32 pin,u32 * id)797 static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
798 {
799 return -ENODEV;
800 }
801
zynqmp_pm_is_function_supported(const u32 api_id,const u32 id)802 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
803 {
804 return -ENODEV;
805 }
806
zynqmp_pm_pinctrl_set_function(const u32 pin,const u32 id)807 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
808 {
809 return -ENODEV;
810 }
811
zynqmp_pm_pinctrl_get_config(const u32 pin,const u32 param,u32 * value)812 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
813 u32 *value)
814 {
815 return -ENODEV;
816 }
817
zynqmp_pm_pinctrl_set_config(const u32 pin,const u32 param,u32 value)818 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
819 u32 value)
820 {
821 return -ENODEV;
822 }
823
zynqmp_pm_load_pdi(const u32 src,const u64 address)824 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
825 {
826 return -ENODEV;
827 }
828
zynqmp_pm_register_notifier(const u32 node,const u32 event,const u32 wake,const u32 enable)829 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
830 const u32 wake, const u32 enable)
831 {
832 return -ENODEV;
833 }
834
zynqmp_pm_feature(const u32 api_id)835 static inline int zynqmp_pm_feature(const u32 api_id)
836 {
837 return -ENODEV;
838 }
839
zynqmp_pm_set_feature_config(enum pm_feature_config_id id,u32 value)840 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
841 u32 value)
842 {
843 return -ENODEV;
844 }
845
zynqmp_pm_get_feature_config(enum pm_feature_config_id id,u32 * payload)846 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
847 u32 *payload)
848 {
849 return -ENODEV;
850 }
851
zynqmp_pm_register_sgi(u32 sgi_num,u32 reset)852 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
853 {
854 return -ENODEV;
855 }
856
zynqmp_pm_force_pwrdwn(const u32 target,const enum zynqmp_pm_request_ack ack)857 static inline int zynqmp_pm_force_pwrdwn(const u32 target,
858 const enum zynqmp_pm_request_ack ack)
859 {
860 return -ENODEV;
861 }
862
zynqmp_pm_request_wake(const u32 node,const bool set_addr,const u64 address,const enum zynqmp_pm_request_ack ack)863 static inline int zynqmp_pm_request_wake(const u32 node,
864 const bool set_addr,
865 const u64 address,
866 const enum zynqmp_pm_request_ack ack)
867 {
868 return -ENODEV;
869 }
870
zynqmp_pm_get_rpu_mode(u32 node_id,enum rpu_oper_mode * rpu_mode)871 static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)
872 {
873 return -ENODEV;
874 }
875
zynqmp_pm_set_rpu_mode(u32 node_id,enum rpu_oper_mode rpu_mode)876 static inline int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode)
877 {
878 return -ENODEV;
879 }
880
zynqmp_pm_set_tcm_config(u32 node_id,enum rpu_tcm_comb tcm_mode)881 static inline int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode)
882 {
883 return -ENODEV;
884 }
885
zynqmp_pm_set_sd_config(u32 node,enum pm_sd_config_type config,u32 value)886 static inline int zynqmp_pm_set_sd_config(u32 node,
887 enum pm_sd_config_type config,
888 u32 value)
889 {
890 return -ENODEV;
891 }
892
zynqmp_pm_set_gem_config(u32 node,enum pm_gem_config_type config,u32 value)893 static inline int zynqmp_pm_set_gem_config(u32 node,
894 enum pm_gem_config_type config,
895 u32 value)
896 {
897 return -ENODEV;
898 }
899
900 #endif
901
902 #endif /* __FIRMWARE_ZYNQMP_H__ */
903