1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
3 
4 #ifndef __QCOM_CLK_ALPHA_PLL_H__
5 #define __QCOM_CLK_ALPHA_PLL_H__
6 
7 #include <linux/clk-provider.h>
8 #include "clk-regmap.h"
9 
10 /* Alpha PLL types */
11 enum {
12 	CLK_ALPHA_PLL_TYPE_DEFAULT,
13 	CLK_ALPHA_PLL_TYPE_HUAYRA,
14 	CLK_ALPHA_PLL_TYPE_BRAMMO,
15 	CLK_ALPHA_PLL_TYPE_FABIA,
16 	CLK_ALPHA_PLL_TYPE_TRION,
17 	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
18 	CLK_ALPHA_PLL_TYPE_AGERA,
19 	CLK_ALPHA_PLL_TYPE_ZONDA,
20 	CLK_ALPHA_PLL_TYPE_LUCID_EVO,
21 	CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
22 	CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
23 	CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
24 	CLK_ALPHA_PLL_TYPE_MAX,
25 };
26 
27 enum {
28 	PLL_OFF_L_VAL,
29 	PLL_OFF_CAL_L_VAL,
30 	PLL_OFF_ALPHA_VAL,
31 	PLL_OFF_ALPHA_VAL_U,
32 	PLL_OFF_USER_CTL,
33 	PLL_OFF_USER_CTL_U,
34 	PLL_OFF_USER_CTL_U1,
35 	PLL_OFF_CONFIG_CTL,
36 	PLL_OFF_CONFIG_CTL_U,
37 	PLL_OFF_CONFIG_CTL_U1,
38 	PLL_OFF_TEST_CTL,
39 	PLL_OFF_TEST_CTL_U,
40 	PLL_OFF_TEST_CTL_U1,
41 	PLL_OFF_STATUS,
42 	PLL_OFF_OPMODE,
43 	PLL_OFF_FRAC,
44 	PLL_OFF_CAL_VAL,
45 	PLL_OFF_MAX_REGS
46 };
47 
48 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
49 
50 struct pll_vco {
51 	unsigned long min_freq;
52 	unsigned long max_freq;
53 	u32 val;
54 };
55 
56 #define VCO(a, b, c) { \
57 	.val = a,\
58 	.min_freq = b,\
59 	.max_freq = c,\
60 }
61 
62 /**
63  * struct clk_alpha_pll - phase locked loop (PLL)
64  * @offset: base address of registers
65  * @vco_table: array of VCO settings
66  * @regs: alpha pll register map (see @clk_alpha_pll_regs)
67  * @clkr: regmap clock handle
68  */
69 struct clk_alpha_pll {
70 	u32 offset;
71 	const u8 *regs;
72 
73 	const struct pll_vco *vco_table;
74 	size_t num_vco;
75 #define SUPPORTS_OFFLINE_REQ		BIT(0)
76 #define SUPPORTS_FSM_MODE		BIT(2)
77 #define SUPPORTS_DYNAMIC_UPDATE	BIT(3)
78 #define SUPPORTS_FSM_LEGACY_MODE	BIT(4)
79 	u8 flags;
80 
81 	struct clk_regmap clkr;
82 };
83 
84 /**
85  * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
86  * @offset: base address of registers
87  * @regs: alpha pll register map (see @clk_alpha_pll_regs)
88  * @width: width of post-divider
89  * @post_div_shift: shift to differentiate between odd & even post-divider
90  * @post_div_table: table with PLL odd and even post-divider settings
91  * @num_post_div: Number of PLL post-divider settings
92  *
93  * @clkr: regmap clock handle
94  */
95 struct clk_alpha_pll_postdiv {
96 	u32 offset;
97 	u8 width;
98 	const u8 *regs;
99 
100 	struct clk_regmap clkr;
101 	int post_div_shift;
102 	const struct clk_div_table *post_div_table;
103 	size_t num_post_div;
104 };
105 
106 struct alpha_pll_config {
107 	u32 l;
108 	u32 alpha;
109 	u32 alpha_hi;
110 	u32 config_ctl_val;
111 	u32 config_ctl_hi_val;
112 	u32 config_ctl_hi1_val;
113 	u32 user_ctl_val;
114 	u32 user_ctl_hi_val;
115 	u32 user_ctl_hi1_val;
116 	u32 test_ctl_val;
117 	u32 test_ctl_hi_val;
118 	u32 test_ctl_hi1_val;
119 	u32 main_output_mask;
120 	u32 aux_output_mask;
121 	u32 aux2_output_mask;
122 	u32 early_output_mask;
123 	u32 alpha_en_mask;
124 	u32 alpha_mode_mask;
125 	u32 pre_div_val;
126 	u32 pre_div_mask;
127 	u32 post_div_val;
128 	u32 post_div_mask;
129 	u32 vco_val;
130 	u32 vco_mask;
131 };
132 
133 extern const struct clk_ops clk_alpha_pll_ops;
134 extern const struct clk_ops clk_alpha_pll_fixed_ops;
135 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
136 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
137 extern const struct clk_ops clk_alpha_pll_huayra_ops;
138 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
139 
140 extern const struct clk_ops clk_alpha_pll_fabia_ops;
141 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
142 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
143 
144 extern const struct clk_ops clk_alpha_pll_trion_ops;
145 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
146 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
147 
148 extern const struct clk_ops clk_alpha_pll_lucid_ops;
149 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
150 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
151 extern const struct clk_ops clk_alpha_pll_agera_ops;
152 
153 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
154 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
155 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
156 
157 extern const struct clk_ops clk_alpha_pll_zonda_ops;
158 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
159 
160 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
161 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
162 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
163 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
164 
165 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
166 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
167 
168 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
169 			     const struct alpha_pll_config *config);
170 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
171 				const struct alpha_pll_config *config);
172 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
173 			     const struct alpha_pll_config *config);
174 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
175 				const struct alpha_pll_config *config);
176 #define clk_lucid_pll_configure(pll, regmap, config) \
177 	clk_trion_pll_configure(pll, regmap, config)
178 
179 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
180 			     const struct alpha_pll_config *config);
181 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
182 				 const struct alpha_pll_config *config);
183 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
184 				  const struct alpha_pll_config *config);
185 
186 #endif
187