1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2  * All Rights Reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the
13  * next paragraph) shall be included in all copies or substantial portions
14  * of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef _I915_REG_H_
26 #define _I915_REG_H_
27 
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29 
30 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
31 
32 /*
33  * The Bridge device's PCI config space has information about the
34  * fb aperture size and the amount of pre-reserved memory.
35  * This is all handled in the intel-gtt.ko module. i915.ko only
36  * cares about the vga bit for the vga rbiter.
37  */
38 #define INTEL_GMCH_CTRL		0x52
39 #define INTEL_GMCH_VGA_DISABLE  (1 << 1)
40 
41 /* PCI config space */
42 
43 #define HPLLCC	0xc0 /* 855 only */
44 #define   GC_CLOCK_CONTROL_MASK		(0xf << 0)
45 #define   GC_CLOCK_133_200		(0 << 0)
46 #define   GC_CLOCK_100_200		(1 << 0)
47 #define   GC_CLOCK_100_133		(2 << 0)
48 #define   GC_CLOCK_166_250		(3 << 0)
49 #define GCFGC2	0xda
50 #define GCFGC	0xf0 /* 915+ only */
51 #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
52 #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
53 #define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
54 #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
55 #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
56 #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
57 #define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
58 #define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
59 #define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
60 #define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
61 #define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
62 #define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
63 #define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
64 #define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
65 #define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
66 #define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
67 #define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
68 #define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
69 #define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
70 #define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
71 #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
72 #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
73 #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
74 #define LBB	0xf4
75 
76 /* Graphics reset regs */
77 #define I965_GDRST 0xc0 /* PCI config register */
78 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
79 #define  GRDOM_FULL	(0<<2)
80 #define  GRDOM_RENDER	(1<<2)
81 #define  GRDOM_MEDIA	(3<<2)
82 
83 #define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */
84 #define   GEN6_MBC_SNPCR_SHIFT	21
85 #define   GEN6_MBC_SNPCR_MASK	(3<<21)
86 #define   GEN6_MBC_SNPCR_MAX	(0<<21)
87 #define   GEN6_MBC_SNPCR_MED	(1<<21)
88 #define   GEN6_MBC_SNPCR_LOW	(2<<21)
89 #define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
90 
91 #define GEN6_MBCTL		0x0907c
92 #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
93 #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
94 #define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
95 #define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
96 #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
97 
98 #define GEN6_GDRST	0x941c
99 #define  GEN6_GRDOM_FULL		(1 << 0)
100 #define  GEN6_GRDOM_RENDER		(1 << 1)
101 #define  GEN6_GRDOM_MEDIA		(1 << 2)
102 #define  GEN6_GRDOM_BLT			(1 << 3)
103 
104 /* PPGTT stuff */
105 #define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
106 
107 #define GEN6_PDE_VALID			(1 << 0)
108 #define GEN6_PDE_LARGE_PAGE		(2 << 0) /* use 32kb pages */
109 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
110 #define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
111 
112 #define GEN6_PTE_VALID			(1 << 0)
113 #define GEN6_PTE_UNCACHED		(1 << 1)
114 #define GEN6_PTE_CACHE_LLC		(2 << 1)
115 #define GEN6_PTE_CACHE_LLC_MLC		(3 << 1)
116 #define GEN6_PTE_CACHE_BITS		(3 << 1)
117 #define GEN6_PTE_GFDT			(1 << 3)
118 #define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
119 
120 #define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)
121 #define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)
122 #define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
123 #define   PP_DIR_DCLV_2G		0xffffffff
124 
125 #define GAM_ECOCHK			0x4090
126 #define   ECOCHK_SNB_BIT		(1<<10)
127 #define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
128 #define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
129 
130 /* VGA stuff */
131 
132 #define VGA_ST01_MDA 0x3ba
133 #define VGA_ST01_CGA 0x3da
134 
135 #define VGA_MSR_WRITE 0x3c2
136 #define VGA_MSR_READ 0x3cc
137 #define   VGA_MSR_MEM_EN (1<<1)
138 #define   VGA_MSR_CGA_MODE (1<<0)
139 
140 #define VGA_SR_INDEX 0x3c4
141 #define VGA_SR_DATA 0x3c5
142 
143 #define VGA_AR_INDEX 0x3c0
144 #define   VGA_AR_VID_EN (1<<5)
145 #define VGA_AR_DATA_WRITE 0x3c0
146 #define VGA_AR_DATA_READ 0x3c1
147 
148 #define VGA_GR_INDEX 0x3ce
149 #define VGA_GR_DATA 0x3cf
150 /* GR05 */
151 #define   VGA_GR_MEM_READ_MODE_SHIFT 3
152 #define     VGA_GR_MEM_READ_MODE_PLANE 1
153 /* GR06 */
154 #define   VGA_GR_MEM_MODE_MASK 0xc
155 #define   VGA_GR_MEM_MODE_SHIFT 2
156 #define   VGA_GR_MEM_A0000_AFFFF 0
157 #define   VGA_GR_MEM_A0000_BFFFF 1
158 #define   VGA_GR_MEM_B0000_B7FFF 2
159 #define   VGA_GR_MEM_B0000_BFFFF 3
160 
161 #define VGA_DACMASK 0x3c6
162 #define VGA_DACRX 0x3c7
163 #define VGA_DACWX 0x3c8
164 #define VGA_DACDATA 0x3c9
165 
166 #define VGA_CR_INDEX_MDA 0x3b4
167 #define VGA_CR_DATA_MDA 0x3b5
168 #define VGA_CR_INDEX_CGA 0x3d4
169 #define VGA_CR_DATA_CGA 0x3d5
170 
171 /*
172  * Memory interface instructions used by the kernel
173  */
174 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
175 
176 #define MI_NOOP			MI_INSTR(0, 0)
177 #define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
178 #define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
179 #define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
180 #define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
181 #define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
182 #define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
183 #define MI_FLUSH		MI_INSTR(0x04, 0)
184 #define   MI_READ_FLUSH		(1 << 0)
185 #define   MI_EXE_FLUSH		(1 << 1)
186 #define   MI_NO_WRITE_FLUSH	(1 << 2)
187 #define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
188 #define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
189 #define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
190 #define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
191 #define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
192 #define   MI_SUSPEND_FLUSH_EN	(1<<0)
193 #define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
194 #define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
195 #define   MI_OVERLAY_CONTINUE	(0x0<<21)
196 #define   MI_OVERLAY_ON		(0x1<<21)
197 #define   MI_OVERLAY_OFF	(0x2<<21)
198 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
199 #define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
200 #define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
201 #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
202 /* IVB has funny definitions for which plane to flip. */
203 #define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
204 #define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
205 #define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
206 #define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
207 #define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
208 #define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
209 
210 #define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
211 #define   MI_MM_SPACE_GTT		(1<<8)
212 #define   MI_MM_SPACE_PHYSICAL		(0<<8)
213 #define   MI_SAVE_EXT_STATE_EN		(1<<3)
214 #define   MI_RESTORE_EXT_STATE_EN	(1<<2)
215 #define   MI_FORCE_RESTORE		(1<<1)
216 #define   MI_RESTORE_INHIBIT		(1<<0)
217 #define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
218 #define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */
219 #define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
220 #define   MI_STORE_DWORD_INDEX_SHIFT 2
221 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
222  * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
223  *   simply ignores the register load under certain conditions.
224  * - One can actually load arbitrary many arbitrary registers: Simply issue x
225  *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
226  */
227 #define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)
228 #define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
229 #define   MI_INVALIDATE_TLB	(1<<18)
230 #define   MI_INVALIDATE_BSD	(1<<7)
231 #define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
232 #define   MI_BATCH_NON_SECURE	(1)
233 #define   MI_BATCH_NON_SECURE_I965 (1<<8)
234 #define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
235 #define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6+ */
236 #define  MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
237 #define  MI_SEMAPHORE_UPDATE	    (1<<21)
238 #define  MI_SEMAPHORE_COMPARE	    (1<<20)
239 #define  MI_SEMAPHORE_REGISTER	    (1<<18)
240 #define  MI_SEMAPHORE_SYNC_RV	    (2<<16)
241 #define  MI_SEMAPHORE_SYNC_RB	    (0<<16)
242 #define  MI_SEMAPHORE_SYNC_VR	    (0<<16)
243 #define  MI_SEMAPHORE_SYNC_VB	    (2<<16)
244 #define  MI_SEMAPHORE_SYNC_BR	    (2<<16)
245 #define  MI_SEMAPHORE_SYNC_BV	    (0<<16)
246 #define  MI_SEMAPHORE_SYNC_INVALID  (1<<0)
247 /*
248  * 3D instructions used by the kernel
249  */
250 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
251 
252 #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
253 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
254 #define   SC_UPDATE_SCISSOR       (0x1<<1)
255 #define   SC_ENABLE_MASK          (0x1<<0)
256 #define   SC_ENABLE               (0x1<<0)
257 #define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
258 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
259 #define   SCI_YMIN_MASK      (0xffff<<16)
260 #define   SCI_XMIN_MASK      (0xffff<<0)
261 #define   SCI_YMAX_MASK      (0xffff<<16)
262 #define   SCI_XMAX_MASK      (0xffff<<0)
263 #define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
264 #define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
265 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
266 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
267 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
268 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
269 #define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
270 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
271 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
272 #define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
273 #define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
274 #define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)
275 #define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
276 #define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
277 #define   BLT_DEPTH_8			(0<<24)
278 #define   BLT_DEPTH_16_565		(1<<24)
279 #define   BLT_DEPTH_16_1555		(2<<24)
280 #define   BLT_DEPTH_32			(3<<24)
281 #define   BLT_ROP_GXCOPY		(0xcc<<16)
282 #define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
283 #define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
284 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
285 #define   ASYNC_FLIP                (1<<22)
286 #define   DISPLAY_PLANE_A           (0<<20)
287 #define   DISPLAY_PLANE_B           (1<<20)
288 #define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
289 #define   PIPE_CONTROL_CS_STALL				(1<<20)
290 #define   PIPE_CONTROL_QW_WRITE				(1<<14)
291 #define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
292 #define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
293 #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
294 #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */
295 #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
296 #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
297 #define   PIPE_CONTROL_NOTIFY				(1<<8)
298 #define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
299 #define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
300 #define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
301 #define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
302 #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
303 #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
304 
305 
306 /*
307  * Reset registers
308  */
309 #define DEBUG_RESET_I830		0x6070
310 #define  DEBUG_RESET_FULL		(1<<7)
311 #define  DEBUG_RESET_RENDER		(1<<8)
312 #define  DEBUG_RESET_DISPLAY		(1<<9)
313 
314 
315 /*
316  * Fence registers
317  */
318 #define FENCE_REG_830_0			0x2000
319 #define FENCE_REG_945_8			0x3000
320 #define   I830_FENCE_START_MASK		0x07f80000
321 #define   I830_FENCE_TILING_Y_SHIFT	12
322 #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
323 #define   I830_FENCE_PITCH_SHIFT	4
324 #define   I830_FENCE_REG_VALID		(1<<0)
325 #define   I915_FENCE_MAX_PITCH_VAL	4
326 #define   I830_FENCE_MAX_PITCH_VAL	6
327 #define   I830_FENCE_MAX_SIZE_VAL	(1<<8)
328 
329 #define   I915_FENCE_START_MASK		0x0ff00000
330 #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
331 
332 #define FENCE_REG_965_0			0x03000
333 #define   I965_FENCE_PITCH_SHIFT	2
334 #define   I965_FENCE_TILING_Y_SHIFT	1
335 #define   I965_FENCE_REG_VALID		(1<<0)
336 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
337 
338 #define FENCE_REG_SANDYBRIDGE_0		0x100000
339 #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
340 
341 /* control register for cpu gtt access */
342 #define TILECTL				0x101000
343 #define   TILECTL_SWZCTL			(1 << 0)
344 #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
345 #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
346 
347 /*
348  * Instruction and interrupt control regs
349  */
350 #define PGTBL_ER	0x02024
351 #define RENDER_RING_BASE	0x02000
352 #define BSD_RING_BASE		0x04000
353 #define GEN6_BSD_RING_BASE	0x12000
354 #define BLT_RING_BASE		0x22000
355 #define RING_TAIL(base)		((base)+0x30)
356 #define RING_HEAD(base)		((base)+0x34)
357 #define RING_START(base)	((base)+0x38)
358 #define RING_CTL(base)		((base)+0x3c)
359 #define RING_SYNC_0(base)	((base)+0x40)
360 #define RING_SYNC_1(base)	((base)+0x44)
361 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
362 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
363 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
364 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
365 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
366 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
367 #define RING_MAX_IDLE(base)	((base)+0x54)
368 #define RING_HWS_PGA(base)	((base)+0x80)
369 #define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
370 #define ARB_MODE		0x04030
371 #define   ARB_MODE_SWIZZLE_SNB	(1<<4)
372 #define   ARB_MODE_SWIZZLE_IVB	(1<<5)
373 #define   ARB_MODE_ENABLE(x)	GFX_MODE_ENABLE(x)
374 #define   ARB_MODE_DISABLE(x)	GFX_MODE_DISABLE(x)
375 #define RENDER_HWS_PGA_GEN7	(0x04080)
376 #define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
377 #define DONE_REG		0x40b0
378 #define BSD_HWS_PGA_GEN7	(0x04180)
379 #define BLT_HWS_PGA_GEN7	(0x04280)
380 #define RING_ACTHD(base)	((base)+0x74)
381 #define RING_NOPID(base)	((base)+0x94)
382 #define RING_IMR(base)		((base)+0xa8)
383 #define   TAIL_ADDR		0x001FFFF8
384 #define   HEAD_WRAP_COUNT	0xFFE00000
385 #define   HEAD_WRAP_ONE		0x00200000
386 #define   HEAD_ADDR		0x001FFFFC
387 #define   RING_NR_PAGES		0x001FF000
388 #define   RING_REPORT_MASK	0x00000006
389 #define   RING_REPORT_64K	0x00000002
390 #define   RING_REPORT_128K	0x00000004
391 #define   RING_NO_REPORT	0x00000000
392 #define   RING_VALID_MASK	0x00000001
393 #define   RING_VALID		0x00000001
394 #define   RING_INVALID		0x00000000
395 #define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */
396 #define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
397 #define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */
398 #if 0
399 #define PRB0_TAIL	0x02030
400 #define PRB0_HEAD	0x02034
401 #define PRB0_START	0x02038
402 #define PRB0_CTL	0x0203c
403 #define PRB1_TAIL	0x02040 /* 915+ only */
404 #define PRB1_HEAD	0x02044 /* 915+ only */
405 #define PRB1_START	0x02048 /* 915+ only */
406 #define PRB1_CTL	0x0204c /* 915+ only */
407 #endif
408 #define IPEIR_I965	0x02064
409 #define IPEHR_I965	0x02068
410 #define INSTDONE_I965	0x0206c
411 #define RING_IPEIR(base)	((base)+0x64)
412 #define RING_IPEHR(base)	((base)+0x68)
413 #define RING_INSTDONE(base)	((base)+0x6c)
414 #define RING_INSTPS(base)	((base)+0x70)
415 #define RING_DMA_FADD(base)	((base)+0x78)
416 #define RING_INSTPM(base)	((base)+0xc0)
417 #define INSTPS		0x02070 /* 965+ only */
418 #define INSTDONE1	0x0207c /* 965+ only */
419 #define ACTHD_I965	0x02074
420 #define HWS_PGA		0x02080
421 #define HWS_ADDRESS_MASK	0xfffff000
422 #define HWS_START_ADDRESS_SHIFT	4
423 #define PWRCTXA		0x2088 /* 965GM+ only */
424 #define   PWRCTX_EN	(1<<0)
425 #define IPEIR		0x02088
426 #define IPEHR		0x0208c
427 #define INSTDONE	0x02090
428 #define NOPID		0x02094
429 #define HWSTAM		0x02098
430 
431 #define ERROR_GEN6	0x040a0
432 
433 /* GM45+ chicken bits -- debug workaround bits that may be required
434  * for various sorts of correct behavior.  The top 16 bits of each are
435  * the enables for writing to the corresponding low bit.
436  */
437 #define _3D_CHICKEN	0x02084
438 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
439 #define _3D_CHICKEN2	0x0208c
440 /* Disables pipelining of read flushes past the SF-WIZ interface.
441  * Required on all Ironlake steppings according to the B-Spec, but the
442  * particular danger of not doing so is not specified.
443  */
444 # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
445 #define _3D_CHICKEN3	0x02090
446 
447 #define MI_MODE		0x0209c
448 # define VS_TIMER_DISPATCH				(1 << 6)
449 # define MI_FLUSH_ENABLE				(1 << 12)
450 
451 #define GEN6_GT_MODE	0x20d0
452 #define   GEN6_GT_MODE_HI	(1 << 9)
453 
454 #define GFX_MODE	0x02520
455 #define GFX_MODE_GEN7	0x0229c
456 #define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)
457 #define   GFX_RUN_LIST_ENABLE		(1<<15)
458 #define   GFX_TLB_INVALIDATE_ALWAYS	(1<<13)
459 #define   GFX_SURFACE_FAULT_ENABLE	(1<<12)
460 #define   GFX_REPLAY_MODE		(1<<11)
461 #define   GFX_PSMI_GRANULARITY		(1<<10)
462 #define   GFX_PPGTT_ENABLE		(1<<9)
463 
464 #define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
465 #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
466 
467 #define SCPD0		0x0209c /* 915+ only */
468 #define IER		0x020a0
469 #define IIR		0x020a4
470 #define IMR		0x020a8
471 #define ISR		0x020ac
472 #define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
473 #define   I915_DISPLAY_PORT_INTERRUPT			(1<<17)
474 #define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
475 #define   I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */
476 #define   I915_HWB_OOM_INTERRUPT			(1<<13)
477 #define   I915_SYNC_STATUS_INTERRUPT			(1<<12)
478 #define   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
479 #define   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
480 #define   I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
481 #define   I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
482 #define   I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
483 #define   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
484 #define   I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
485 #define   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
486 #define   I915_DEBUG_INTERRUPT				(1<<2)
487 #define   I915_USER_INTERRUPT				(1<<1)
488 #define   I915_ASLE_INTERRUPT				(1<<0)
489 #define   I915_BSD_USER_INTERRUPT                      (1<<25)
490 #define EIR		0x020b0
491 #define EMR		0x020b4
492 #define ESR		0x020b8
493 #define   GM45_ERROR_PAGE_TABLE				(1<<5)
494 #define   GM45_ERROR_MEM_PRIV				(1<<4)
495 #define   I915_ERROR_PAGE_TABLE				(1<<4)
496 #define   GM45_ERROR_CP_PRIV				(1<<3)
497 #define   I915_ERROR_MEMORY_REFRESH			(1<<1)
498 #define   I915_ERROR_INSTRUCTION			(1<<0)
499 #define INSTPM	        0x020c0
500 #define   INSTPM_SELF_EN (1<<12) /* 915GM only */
501 #define   INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
502 					will not assert AGPBUSY# and will only
503 					be delivered when out of C3. */
504 #define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
505 #define   INSTPM_TLB_INVALIDATE	(1<<9)
506 #define   INSTPM_SYNC_FLUSH	(1<<5)
507 #define ACTHD	        0x020c8
508 #define FW_BLC		0x020d8
509 #define FW_BLC2		0x020dc
510 #define FW_BLC_SELF	0x020e0 /* 915+ only */
511 #define   FW_BLC_SELF_EN_MASK      (1<<31)
512 #define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
513 #define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
514 #define MM_BURST_LENGTH     0x00700000
515 #define MM_FIFO_WATERMARK   0x0001F000
516 #define LM_BURST_LENGTH     0x00000700
517 #define LM_FIFO_WATERMARK   0x0000001F
518 #define MI_ARB_STATE	0x020e4 /* 915+ only */
519 #define   MI_ARB_MASK_SHIFT	  16	/* shift for enable bits */
520 
521 /* Make render/texture TLB fetches lower priorty than associated data
522  *   fetches. This is not turned on by default
523  */
524 #define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
525 
526 /* Isoch request wait on GTT enable (Display A/B/C streams).
527  * Make isoch requests stall on the TLB update. May cause
528  * display underruns (test mode only)
529  */
530 #define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
531 
532 /* Block grant count for isoch requests when block count is
533  * set to a finite value.
534  */
535 #define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
536 #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
537 #define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
538 #define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
539 #define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
540 
541 /* Enable render writes to complete in C2/C3/C4 power states.
542  * If this isn't enabled, render writes are prevented in low
543  * power states. That seems bad to me.
544  */
545 #define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
546 
547 /* This acknowledges an async flip immediately instead
548  * of waiting for 2TLB fetches.
549  */
550 #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
551 
552 /* Enables non-sequential data reads through arbiter
553  */
554 #define   MI_ARB_DUAL_DATA_PHASE_DISABLE	(1 << 9)
555 
556 /* Disable FSB snooping of cacheable write cycles from binner/render
557  * command stream
558  */
559 #define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
560 
561 /* Arbiter time slice for non-isoch streams */
562 #define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
563 #define   MI_ARB_TIME_SLICE_1			(0 << 5)
564 #define   MI_ARB_TIME_SLICE_2			(1 << 5)
565 #define   MI_ARB_TIME_SLICE_4			(2 << 5)
566 #define   MI_ARB_TIME_SLICE_6			(3 << 5)
567 #define   MI_ARB_TIME_SLICE_8			(4 << 5)
568 #define   MI_ARB_TIME_SLICE_10			(5 << 5)
569 #define   MI_ARB_TIME_SLICE_14			(6 << 5)
570 #define   MI_ARB_TIME_SLICE_16			(7 << 5)
571 
572 /* Low priority grace period page size */
573 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
574 #define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
575 
576 /* Disable display A/B trickle feed */
577 #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
578 
579 /* Set display plane priority */
580 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
581 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
582 
583 #define CACHE_MODE_0	0x02120 /* 915+ only */
584 #define   CM0_MASK_SHIFT          16
585 #define   CM0_IZ_OPT_DISABLE      (1<<6)
586 #define   CM0_ZR_OPT_DISABLE      (1<<5)
587 #define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
588 #define   CM0_DEPTH_EVICT_DISABLE (1<<4)
589 #define   CM0_COLOR_EVICT_DISABLE (1<<3)
590 #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
591 #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
592 #define BB_ADDR		0x02140 /* 8 bytes */
593 #define GFX_FLSH_CNTL	0x02170 /* 915+ only */
594 #define ECOSKPD		0x021d0
595 #define   ECO_GATING_CX_ONLY	(1<<3)
596 #define   ECO_FLIP_DONE		(1<<0)
597 
598 /* GEN6 interrupt control */
599 #define GEN6_RENDER_HWSTAM	0x2098
600 #define GEN6_RENDER_IMR		0x20a8
601 #define   GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT		(1 << 8)
602 #define   GEN6_RENDER_PPGTT_PAGE_FAULT			(1 << 7)
603 #define   GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED		(1 << 6)
604 #define   GEN6_RENDER_L3_PARITY_ERROR			(1 << 5)
605 #define   GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT	(1 << 4)
606 #define   GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR	(1 << 3)
607 #define   GEN6_RENDER_SYNC_STATUS			(1 << 2)
608 #define   GEN6_RENDER_DEBUG_INTERRUPT			(1 << 1)
609 #define   GEN6_RENDER_USER_INTERRUPT			(1 << 0)
610 
611 #define GEN6_BLITTER_HWSTAM	0x22098
612 #define GEN6_BLITTER_IMR	0x220a8
613 #define   GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT	(1 << 26)
614 #define   GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR	(1 << 25)
615 #define   GEN6_BLITTER_SYNC_STATUS			(1 << 24)
616 #define   GEN6_BLITTER_USER_INTERRUPT			(1 << 22)
617 
618 #define GEN6_BLITTER_ECOSKPD	0x221d0
619 #define   GEN6_BLITTER_LOCK_SHIFT			16
620 #define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
621 
622 #define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
623 #define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK	(1 << 16)
624 #define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE		(1 << 0)
625 #define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE		0
626 #define   GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR			(1 << 3)
627 
628 #define GEN6_BSD_HWSTAM			0x12098
629 #define GEN6_BSD_IMR			0x120a8
630 #define   GEN6_BSD_USER_INTERRUPT	(1 << 12)
631 
632 #define GEN6_BSD_RNCID			0x12198
633 
634 #define GEN7_FF_THREAD_MODE		0x20a0
635 #define   GEN7_FF_SCHED_MASK		0x0077070
636 #define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
637 #define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
638 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
639 #define   GEN7_FF_TS_SCHED_HW		(0x0<<16) /* Default */
640 #define   GEN7_FF_VS_SCHED_HS1		(0x5<<12)
641 #define   GEN7_FF_VS_SCHED_HS0		(0x3<<12)
642 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1<<12) /* Default */
643 #define   GEN7_FF_VS_SCHED_HW		(0x0<<12)
644 #define   GEN7_FF_DS_SCHED_HS1		(0x5<<4)
645 #define   GEN7_FF_DS_SCHED_HS0		(0x3<<4)
646 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1<<4)  /* Default */
647 #define   GEN7_FF_DS_SCHED_HW		(0x0<<4)
648 
649 /*
650  * Framebuffer compression (915+ only)
651  */
652 
653 #define FBC_CFB_BASE		0x03200 /* 4k page aligned */
654 #define FBC_LL_BASE		0x03204 /* 4k page aligned */
655 #define FBC_CONTROL		0x03208
656 #define   FBC_CTL_EN		(1<<31)
657 #define   FBC_CTL_PERIODIC	(1<<30)
658 #define   FBC_CTL_INTERVAL_SHIFT (16)
659 #define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
660 #define   FBC_CTL_C3_IDLE	(1<<13)
661 #define   FBC_CTL_STRIDE_SHIFT	(5)
662 #define   FBC_CTL_FENCENO	(1<<0)
663 #define FBC_COMMAND		0x0320c
664 #define   FBC_CMD_COMPRESS	(1<<0)
665 #define FBC_STATUS		0x03210
666 #define   FBC_STAT_COMPRESSING	(1<<31)
667 #define   FBC_STAT_COMPRESSED	(1<<30)
668 #define   FBC_STAT_MODIFIED	(1<<29)
669 #define   FBC_STAT_CURRENT_LINE	(1<<0)
670 #define FBC_CONTROL2		0x03214
671 #define   FBC_CTL_FENCE_DBL	(0<<4)
672 #define   FBC_CTL_IDLE_IMM	(0<<2)
673 #define   FBC_CTL_IDLE_FULL	(1<<2)
674 #define   FBC_CTL_IDLE_LINE	(2<<2)
675 #define   FBC_CTL_IDLE_DEBUG	(3<<2)
676 #define   FBC_CTL_CPU_FENCE	(1<<1)
677 #define   FBC_CTL_PLANEA	(0<<0)
678 #define   FBC_CTL_PLANEB	(1<<0)
679 #define FBC_FENCE_OFF		0x0321b
680 #define FBC_TAG			0x03300
681 
682 #define FBC_LL_SIZE		(1536)
683 
684 /* Framebuffer compression for GM45+ */
685 #define DPFC_CB_BASE		0x3200
686 #define DPFC_CONTROL		0x3208
687 #define   DPFC_CTL_EN		(1<<31)
688 #define   DPFC_CTL_PLANEA	(0<<30)
689 #define   DPFC_CTL_PLANEB	(1<<30)
690 #define   DPFC_CTL_FENCE_EN	(1<<29)
691 #define   DPFC_CTL_PERSISTENT_MODE	(1<<25)
692 #define   DPFC_SR_EN		(1<<10)
693 #define   DPFC_CTL_LIMIT_1X	(0<<6)
694 #define   DPFC_CTL_LIMIT_2X	(1<<6)
695 #define   DPFC_CTL_LIMIT_4X	(2<<6)
696 #define DPFC_RECOMP_CTL		0x320c
697 #define   DPFC_RECOMP_STALL_EN	(1<<27)
698 #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
699 #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
700 #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
701 #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
702 #define DPFC_STATUS		0x3210
703 #define   DPFC_INVAL_SEG_SHIFT  (16)
704 #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
705 #define   DPFC_COMP_SEG_SHIFT	(0)
706 #define   DPFC_COMP_SEG_MASK	(0x000003ff)
707 #define DPFC_STATUS2		0x3214
708 #define DPFC_FENCE_YOFF		0x3218
709 #define DPFC_CHICKEN		0x3224
710 #define   DPFC_HT_MODIFY	(1<<31)
711 
712 /* Framebuffer compression for Ironlake */
713 #define ILK_DPFC_CB_BASE	0x43200
714 #define ILK_DPFC_CONTROL	0x43208
715 /* The bit 28-8 is reserved */
716 #define   DPFC_RESERVED		(0x1FFFFF00)
717 #define ILK_DPFC_RECOMP_CTL	0x4320c
718 #define ILK_DPFC_STATUS		0x43210
719 #define ILK_DPFC_FENCE_YOFF	0x43218
720 #define ILK_DPFC_CHICKEN	0x43224
721 #define ILK_FBC_RT_BASE		0x2128
722 #define   ILK_FBC_RT_VALID	(1<<0)
723 
724 #define ILK_DISPLAY_CHICKEN1	0x42000
725 #define   ILK_FBCQ_DIS		(1<<22)
726 #define	  ILK_PABSTRETCH_DIS	(1<<21)
727 
728 
729 /*
730  * Framebuffer compression for Sandybridge
731  *
732  * The following two registers are of type GTTMMADR
733  */
734 #define SNB_DPFC_CTL_SA		0x100100
735 #define   SNB_CPU_FENCE_ENABLE	(1<<29)
736 #define DPFC_CPU_FENCE_OFFSET	0x100104
737 
738 
739 /*
740  * GPIO regs
741  */
742 #define GPIOA			0x5010
743 #define GPIOB			0x5014
744 #define GPIOC			0x5018
745 #define GPIOD			0x501c
746 #define GPIOE			0x5020
747 #define GPIOF			0x5024
748 #define GPIOG			0x5028
749 #define GPIOH			0x502c
750 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
751 # define GPIO_CLOCK_DIR_IN		(0 << 1)
752 # define GPIO_CLOCK_DIR_OUT		(1 << 1)
753 # define GPIO_CLOCK_VAL_MASK		(1 << 2)
754 # define GPIO_CLOCK_VAL_OUT		(1 << 3)
755 # define GPIO_CLOCK_VAL_IN		(1 << 4)
756 # define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
757 # define GPIO_DATA_DIR_MASK		(1 << 8)
758 # define GPIO_DATA_DIR_IN		(0 << 9)
759 # define GPIO_DATA_DIR_OUT		(1 << 9)
760 # define GPIO_DATA_VAL_MASK		(1 << 10)
761 # define GPIO_DATA_VAL_OUT		(1 << 11)
762 # define GPIO_DATA_VAL_IN		(1 << 12)
763 # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
764 
765 #define GMBUS0			0x5100 /* clock/port select */
766 #define   GMBUS_RATE_100KHZ	(0<<8)
767 #define   GMBUS_RATE_50KHZ	(1<<8)
768 #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
769 #define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
770 #define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
771 #define   GMBUS_PORT_DISABLED	0
772 #define   GMBUS_PORT_SSC	1
773 #define   GMBUS_PORT_VGADDC	2
774 #define   GMBUS_PORT_PANEL	3
775 #define   GMBUS_PORT_DPC	4 /* HDMIC */
776 #define   GMBUS_PORT_DPB	5 /* SDVO, HDMIB */
777 				  /* 6 reserved */
778 #define   GMBUS_PORT_DPD	7 /* HDMID */
779 #define   GMBUS_NUM_PORTS       8
780 #define GMBUS1			0x5104 /* command/status */
781 #define   GMBUS_SW_CLR_INT	(1<<31)
782 #define   GMBUS_SW_RDY		(1<<30)
783 #define   GMBUS_ENT		(1<<29) /* enable timeout */
784 #define   GMBUS_CYCLE_NONE	(0<<25)
785 #define   GMBUS_CYCLE_WAIT	(1<<25)
786 #define   GMBUS_CYCLE_INDEX	(2<<25)
787 #define   GMBUS_CYCLE_STOP	(4<<25)
788 #define   GMBUS_BYTE_COUNT_SHIFT 16
789 #define   GMBUS_SLAVE_INDEX_SHIFT 8
790 #define   GMBUS_SLAVE_ADDR_SHIFT 1
791 #define   GMBUS_SLAVE_READ	(1<<0)
792 #define   GMBUS_SLAVE_WRITE	(0<<0)
793 #define GMBUS2			0x5108 /* status */
794 #define   GMBUS_INUSE		(1<<15)
795 #define   GMBUS_HW_WAIT_PHASE	(1<<14)
796 #define   GMBUS_STALL_TIMEOUT	(1<<13)
797 #define   GMBUS_INT		(1<<12)
798 #define   GMBUS_HW_RDY		(1<<11)
799 #define   GMBUS_SATOER		(1<<10)
800 #define   GMBUS_ACTIVE		(1<<9)
801 #define GMBUS3			0x510c /* data buffer bytes 3-0 */
802 #define GMBUS4			0x5110 /* interrupt mask (Pineview+) */
803 #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
804 #define   GMBUS_NAK_EN		(1<<3)
805 #define   GMBUS_IDLE_EN		(1<<2)
806 #define   GMBUS_HW_WAIT_EN	(1<<1)
807 #define   GMBUS_HW_RDY_EN	(1<<0)
808 #define GMBUS5			0x5120 /* byte index */
809 #define   GMBUS_2BYTE_INDEX_EN	(1<<31)
810 
811 /*
812  * Clock control & power management
813  */
814 
815 #define VGA0	0x6000
816 #define VGA1	0x6004
817 #define VGA_PD	0x6010
818 #define   VGA0_PD_P2_DIV_4	(1 << 7)
819 #define   VGA0_PD_P1_DIV_2	(1 << 5)
820 #define   VGA0_PD_P1_SHIFT	0
821 #define   VGA0_PD_P1_MASK	(0x1f << 0)
822 #define   VGA1_PD_P2_DIV_4	(1 << 15)
823 #define   VGA1_PD_P1_DIV_2	(1 << 13)
824 #define   VGA1_PD_P1_SHIFT	8
825 #define   VGA1_PD_P1_MASK	(0x1f << 8)
826 #define _DPLL_A	0x06014
827 #define _DPLL_B	0x06018
828 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
829 #define   DPLL_VCO_ENABLE		(1 << 31)
830 #define   DPLL_DVO_HIGH_SPEED		(1 << 30)
831 #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
832 #define   DPLL_VGA_MODE_DIS		(1 << 28)
833 #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
834 #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
835 #define   DPLL_MODE_MASK		(3 << 26)
836 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
837 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
838 #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
839 #define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
840 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
841 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
842 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
843 
844 #define SRX_INDEX		0x3c4
845 #define SRX_DATA		0x3c5
846 #define SR01			1
847 #define SR01_SCREEN_OFF		(1<<5)
848 
849 #define PPCR			0x61204
850 #define PPCR_ON			(1<<0)
851 
852 #define DVOB			0x61140
853 #define DVOB_ON			(1<<31)
854 #define DVOC			0x61160
855 #define DVOC_ON			(1<<31)
856 #define LVDS			0x61180
857 #define LVDS_ON			(1<<31)
858 
859 /* Scratch pad debug 0 reg:
860  */
861 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
862 /*
863  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
864  * this field (only one bit may be set).
865  */
866 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
867 #define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
868 #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
869 /* i830, required in DVO non-gang */
870 #define   PLL_P2_DIVIDE_BY_4		(1 << 23)
871 #define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
872 #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
873 #define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
874 #define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
875 #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
876 #define   PLL_REF_INPUT_MASK		(3 << 13)
877 #define   PLL_LOAD_PULSE_PHASE_SHIFT		9
878 /* Ironlake */
879 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
880 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
881 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x)-1) << 9)
882 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
883 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
884 
885 /*
886  * Parallel to Serial Load Pulse phase selection.
887  * Selects the phase for the 10X DPLL clock for the PCIe
888  * digital display port. The range is 4 to 13; 10 or more
889  * is just a flip delay. The default is 6
890  */
891 #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
892 #define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
893 /*
894  * SDVO multiplier for 945G/GM. Not used on 965.
895  */
896 #define   SDVO_MULTIPLIER_MASK			0x000000ff
897 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
898 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
899 #define _DPLL_A_MD 0x0601c /* 965+ only */
900 /*
901  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
902  *
903  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
904  */
905 #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
906 #define   DPLL_MD_UDI_DIVIDER_SHIFT		24
907 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
908 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
909 #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
910 /*
911  * SDVO/UDI pixel multiplier.
912  *
913  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
914  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
915  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
916  * dummy bytes in the datastream at an increased clock rate, with both sides of
917  * the link knowing how many bytes are fill.
918  *
919  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
920  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
921  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
922  * through an SDVO command.
923  *
924  * This register field has values of multiplication factor minus 1, with
925  * a maximum multiplier of 5 for SDVO.
926  */
927 #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
928 #define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
929 /*
930  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
931  * This best be set to the default value (3) or the CRT won't work. No,
932  * I don't entirely understand what this does...
933  */
934 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
935 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
936 #define _DPLL_B_MD 0x06020 /* 965+ only */
937 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
938 #define _FPA0	0x06040
939 #define _FPA1	0x06044
940 #define _FPB0	0x06048
941 #define _FPB1	0x0604c
942 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
943 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
944 #define   FP_N_DIV_MASK		0x003f0000
945 #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
946 #define   FP_N_DIV_SHIFT		16
947 #define   FP_M1_DIV_MASK	0x00003f00
948 #define   FP_M1_DIV_SHIFT		 8
949 #define   FP_M2_DIV_MASK	0x0000003f
950 #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
951 #define   FP_M2_DIV_SHIFT		 0
952 #define DPLL_TEST	0x606c
953 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
954 #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
955 #define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
956 #define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
957 #define   DPLLB_TEST_N_BYPASS		(1 << 19)
958 #define   DPLLB_TEST_M_BYPASS		(1 << 18)
959 #define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
960 #define   DPLLA_TEST_N_BYPASS		(1 << 3)
961 #define   DPLLA_TEST_M_BYPASS		(1 << 2)
962 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
963 #define D_STATE		0x6104
964 #define  DSTATE_GFX_RESET_I830			(1<<6)
965 #define  DSTATE_PLL_D3_OFF			(1<<3)
966 #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
967 #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
968 #define DSPCLK_GATE_D		0x6200
969 # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
970 # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
971 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
972 # define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
973 # define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
974 # define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
975 # define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
976 # define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
977 # define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
978 # define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
979 # define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
980 # define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
981 # define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
982 # define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
983 # define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
984 # define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
985 # define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
986 # define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
987 # define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
988 # define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
989 # define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
990 # define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
991 # define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
992 # define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
993 # define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
994 # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
995 # define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
996 # define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
997 /**
998  * This bit must be set on the 830 to prevent hangs when turning off the
999  * overlay scaler.
1000  */
1001 # define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
1002 # define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
1003 # define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
1004 # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
1005 # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
1006 
1007 #define RENCLK_GATE_D1		0x6204
1008 # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
1009 # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
1010 # define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
1011 # define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
1012 # define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
1013 # define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
1014 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
1015 # define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
1016 # define MAG_CLOCK_GATE_DISABLE			(1 << 5)
1017 /** This bit must be unset on 855,865 */
1018 # define MECI_CLOCK_GATE_DISABLE		(1 << 4)
1019 # define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
1020 # define MEC_CLOCK_GATE_DISABLE			(1 << 2)
1021 # define MECO_CLOCK_GATE_DISABLE		(1 << 1)
1022 /** This bit must be set on 855,865. */
1023 # define SV_CLOCK_GATE_DISABLE			(1 << 0)
1024 # define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
1025 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
1026 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
1027 # define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
1028 # define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
1029 # define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
1030 # define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
1031 # define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
1032 # define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
1033 # define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
1034 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
1035 # define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
1036 # define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
1037 # define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
1038 # define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
1039 # define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
1040 # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
1041 
1042 # define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
1043 /** This bit must always be set on 965G/965GM */
1044 # define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
1045 # define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
1046 # define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
1047 # define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
1048 # define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
1049 # define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
1050 /** This bit must always be set on 965G */
1051 # define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
1052 # define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
1053 # define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
1054 # define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
1055 # define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
1056 # define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
1057 # define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
1058 # define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
1059 # define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
1060 # define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
1061 # define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
1062 # define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
1063 # define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
1064 # define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
1065 # define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
1066 # define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
1067 # define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
1068 # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
1069 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
1070 
1071 #define RENCLK_GATE_D2		0x6208
1072 #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
1073 #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
1074 #define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
1075 #define RAMCLK_GATE_D		0x6210		/* CRL only */
1076 #define DEUC			0x6214          /* CRL only */
1077 
1078 /*
1079  * Palette regs
1080  */
1081 
1082 #define _PALETTE_A		0x0a000
1083 #define _PALETTE_B		0x0a800
1084 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
1085 
1086 /* MCH MMIO space */
1087 
1088 /*
1089  * MCHBAR mirror.
1090  *
1091  * This mirrors the MCHBAR MMIO space whose location is determined by
1092  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1093  * every way.  It is not accessible from the CP register read instructions.
1094  *
1095  */
1096 #define MCHBAR_MIRROR_BASE	0x10000
1097 
1098 #define MCHBAR_MIRROR_BASE_SNB	0x140000
1099 
1100 /** 915-945 and GM965 MCH register controlling DRAM channel access */
1101 #define DCC			0x10200
1102 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
1103 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
1104 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
1105 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
1106 #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
1107 #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
1108 
1109 /** Pineview MCH register contains DDR3 setting */
1110 #define CSHRDDR3CTL            0x101a8
1111 #define CSHRDDR3CTL_DDR3       (1 << 2)
1112 
1113 /** 965 MCH register controlling DRAM channel configuration */
1114 #define C0DRB3			0x10206
1115 #define C1DRB3			0x10606
1116 
1117 /** snb MCH registers for reading the DRAM channel configuration */
1118 #define MAD_DIMM_C0			(MCHBAR_MIRROR_BASE_SNB + 0x5004)
1119 #define MAD_DIMM_C1			(MCHBAR_MIRROR_BASE_SNB + 0x5008)
1120 #define MAD_DIMM_C2			(MCHBAR_MIRROR_BASE_SNB + 0x500C)
1121 #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
1122 #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
1123 #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
1124 #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
1125 #define   MAD_DIMM_ECC_ON		(0x3 << 24)
1126 #define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
1127 #define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
1128 #define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
1129 #define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
1130 #define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
1131 #define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
1132 #define   MAD_DIMM_A_SELECT		(0x1 << 16)
1133 /* DIMM sizes are in multiples of 256mb. */
1134 #define   MAD_DIMM_B_SIZE_SHIFT		8
1135 #define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
1136 #define   MAD_DIMM_A_SIZE_SHIFT		0
1137 #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
1138 
1139 
1140 /* Clocking configuration register */
1141 #define CLKCFG			0x10c00
1142 #define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
1143 #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
1144 #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
1145 #define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
1146 #define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
1147 #define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
1148 /* Note, below two are guess */
1149 #define CLKCFG_FSB_1600					(4 << 0)	/* hrawclk 400 */
1150 #define CLKCFG_FSB_1600_ALT				(0 << 0)	/* hrawclk 400 */
1151 #define CLKCFG_FSB_MASK					(7 << 0)
1152 #define CLKCFG_MEM_533					(1 << 4)
1153 #define CLKCFG_MEM_667					(2 << 4)
1154 #define CLKCFG_MEM_800					(3 << 4)
1155 #define CLKCFG_MEM_MASK					(7 << 4)
1156 
1157 #define TSC1			0x11001
1158 #define   TSE			(1<<0)
1159 #define TR1			0x11006
1160 #define TSFS			0x11020
1161 #define   TSFS_SLOPE_MASK	0x0000ff00
1162 #define   TSFS_SLOPE_SHIFT	8
1163 #define   TSFS_INTR_MASK	0x000000ff
1164 
1165 #define CRSTANDVID		0x11100
1166 #define PXVFREQ_BASE		0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1167 #define   PXVFREQ_PX_MASK	0x7f000000
1168 #define   PXVFREQ_PX_SHIFT	24
1169 #define VIDFREQ_BASE		0x11110
1170 #define VIDFREQ1		0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1171 #define VIDFREQ2		0x11114
1172 #define VIDFREQ3		0x11118
1173 #define VIDFREQ4		0x1111c
1174 #define   VIDFREQ_P0_MASK	0x1f000000
1175 #define   VIDFREQ_P0_SHIFT	24
1176 #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
1177 #define   VIDFREQ_P0_CSCLK_SHIFT 20
1178 #define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
1179 #define   VIDFREQ_P0_CRCLK_SHIFT 16
1180 #define   VIDFREQ_P1_MASK	0x00001f00
1181 #define   VIDFREQ_P1_SHIFT	8
1182 #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
1183 #define   VIDFREQ_P1_CSCLK_SHIFT 4
1184 #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
1185 #define INTTOEXT_BASE_ILK	0x11300
1186 #define INTTOEXT_BASE		0x11120 /* INTTOEXT1-8 (0x1113c) */
1187 #define   INTTOEXT_MAP3_SHIFT	24
1188 #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
1189 #define   INTTOEXT_MAP2_SHIFT	16
1190 #define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
1191 #define   INTTOEXT_MAP1_SHIFT	8
1192 #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
1193 #define   INTTOEXT_MAP0_SHIFT	0
1194 #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
1195 #define MEMSWCTL		0x11170 /* Ironlake only */
1196 #define   MEMCTL_CMD_MASK	0xe000
1197 #define   MEMCTL_CMD_SHIFT	13
1198 #define   MEMCTL_CMD_RCLK_OFF	0
1199 #define   MEMCTL_CMD_RCLK_ON	1
1200 #define   MEMCTL_CMD_CHFREQ	2
1201 #define   MEMCTL_CMD_CHVID	3
1202 #define   MEMCTL_CMD_VMMOFF	4
1203 #define   MEMCTL_CMD_VMMON	5
1204 #define   MEMCTL_CMD_STS	(1<<12) /* write 1 triggers command, clears
1205 					   when command complete */
1206 #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
1207 #define   MEMCTL_FREQ_SHIFT	8
1208 #define   MEMCTL_SFCAVM		(1<<7)
1209 #define   MEMCTL_TGT_VID_MASK	0x007f
1210 #define MEMIHYST		0x1117c
1211 #define MEMINTREN		0x11180 /* 16 bits */
1212 #define   MEMINT_RSEXIT_EN	(1<<8)
1213 #define   MEMINT_CX_SUPR_EN	(1<<7)
1214 #define   MEMINT_CONT_BUSY_EN	(1<<6)
1215 #define   MEMINT_AVG_BUSY_EN	(1<<5)
1216 #define   MEMINT_EVAL_CHG_EN	(1<<4)
1217 #define   MEMINT_MON_IDLE_EN	(1<<3)
1218 #define   MEMINT_UP_EVAL_EN	(1<<2)
1219 #define   MEMINT_DOWN_EVAL_EN	(1<<1)
1220 #define   MEMINT_SW_CMD_EN	(1<<0)
1221 #define MEMINTRSTR		0x11182 /* 16 bits */
1222 #define   MEM_RSEXIT_MASK	0xc000
1223 #define   MEM_RSEXIT_SHIFT	14
1224 #define   MEM_CONT_BUSY_MASK	0x3000
1225 #define   MEM_CONT_BUSY_SHIFT	12
1226 #define   MEM_AVG_BUSY_MASK	0x0c00
1227 #define   MEM_AVG_BUSY_SHIFT	10
1228 #define   MEM_EVAL_CHG_MASK	0x0300
1229 #define   MEM_EVAL_BUSY_SHIFT	8
1230 #define   MEM_MON_IDLE_MASK	0x00c0
1231 #define   MEM_MON_IDLE_SHIFT	6
1232 #define   MEM_UP_EVAL_MASK	0x0030
1233 #define   MEM_UP_EVAL_SHIFT	4
1234 #define   MEM_DOWN_EVAL_MASK	0x000c
1235 #define   MEM_DOWN_EVAL_SHIFT	2
1236 #define   MEM_SW_CMD_MASK	0x0003
1237 #define   MEM_INT_STEER_GFX	0
1238 #define   MEM_INT_STEER_CMR	1
1239 #define   MEM_INT_STEER_SMI	2
1240 #define   MEM_INT_STEER_SCI	3
1241 #define MEMINTRSTS		0x11184
1242 #define   MEMINT_RSEXIT		(1<<7)
1243 #define   MEMINT_CONT_BUSY	(1<<6)
1244 #define   MEMINT_AVG_BUSY	(1<<5)
1245 #define   MEMINT_EVAL_CHG	(1<<4)
1246 #define   MEMINT_MON_IDLE	(1<<3)
1247 #define   MEMINT_UP_EVAL	(1<<2)
1248 #define   MEMINT_DOWN_EVAL	(1<<1)
1249 #define   MEMINT_SW_CMD		(1<<0)
1250 #define MEMMODECTL		0x11190
1251 #define   MEMMODE_BOOST_EN	(1<<31)
1252 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1253 #define   MEMMODE_BOOST_FREQ_SHIFT 24
1254 #define   MEMMODE_IDLE_MODE_MASK 0x00030000
1255 #define   MEMMODE_IDLE_MODE_SHIFT 16
1256 #define   MEMMODE_IDLE_MODE_EVAL 0
1257 #define   MEMMODE_IDLE_MODE_CONT 1
1258 #define   MEMMODE_HWIDLE_EN	(1<<15)
1259 #define   MEMMODE_SWMODE_EN	(1<<14)
1260 #define   MEMMODE_RCLK_GATE	(1<<13)
1261 #define   MEMMODE_HW_UPDATE	(1<<12)
1262 #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
1263 #define   MEMMODE_FSTART_SHIFT	8
1264 #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
1265 #define   MEMMODE_FMAX_SHIFT	4
1266 #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
1267 #define RCBMAXAVG		0x1119c
1268 #define MEMSWCTL2		0x1119e /* Cantiga only */
1269 #define   SWMEMCMD_RENDER_OFF	(0 << 13)
1270 #define   SWMEMCMD_RENDER_ON	(1 << 13)
1271 #define   SWMEMCMD_SWFREQ	(2 << 13)
1272 #define   SWMEMCMD_TARVID	(3 << 13)
1273 #define   SWMEMCMD_VRM_OFF	(4 << 13)
1274 #define   SWMEMCMD_VRM_ON	(5 << 13)
1275 #define   CMDSTS		(1<<12)
1276 #define   SFCAVM		(1<<11)
1277 #define   SWFREQ_MASK		0x0380 /* P0-7 */
1278 #define   SWFREQ_SHIFT		7
1279 #define   TARVID_MASK		0x001f
1280 #define MEMSTAT_CTG		0x111a0
1281 #define RCBMINAVG		0x111a0
1282 #define RCUPEI			0x111b0
1283 #define RCDNEI			0x111b4
1284 #define RSTDBYCTL		0x111b8
1285 #define   RS1EN			(1<<31)
1286 #define   RS2EN			(1<<30)
1287 #define   RS3EN			(1<<29)
1288 #define   D3RS3EN		(1<<28) /* Display D3 imlies RS3 */
1289 #define   SWPROMORSX		(1<<27) /* RSx promotion timers ignored */
1290 #define   RCWAKERW		(1<<26) /* Resetwarn from PCH causes wakeup */
1291 #define   DPRSLPVREN		(1<<25) /* Fast voltage ramp enable */
1292 #define   GFXTGHYST		(1<<24) /* Hysteresis to allow trunk gating */
1293 #define   RCX_SW_EXIT		(1<<23) /* Leave RSx and prevent re-entry */
1294 #define   RSX_STATUS_MASK	(7<<20)
1295 #define   RSX_STATUS_ON		(0<<20)
1296 #define   RSX_STATUS_RC1	(1<<20)
1297 #define   RSX_STATUS_RC1E	(2<<20)
1298 #define   RSX_STATUS_RS1	(3<<20)
1299 #define   RSX_STATUS_RS2	(4<<20) /* aka rc6 */
1300 #define   RSX_STATUS_RSVD	(5<<20) /* deep rc6 unsupported on ilk */
1301 #define   RSX_STATUS_RS3	(6<<20) /* rs3 unsupported on ilk */
1302 #define   RSX_STATUS_RSVD2	(7<<20)
1303 #define   UWRCRSXE		(1<<19) /* wake counter limit prevents rsx */
1304 #define   RSCRP			(1<<18) /* rs requests control on rs1/2 reqs */
1305 #define   JRSC			(1<<17) /* rsx coupled to cpu c-state */
1306 #define   RS2INC0		(1<<16) /* allow rs2 in cpu c0 */
1307 #define   RS1CONTSAV_MASK	(3<<14)
1308 #define   RS1CONTSAV_NO_RS1	(0<<14) /* rs1 doesn't save/restore context */
1309 #define   RS1CONTSAV_RSVD	(1<<14)
1310 #define   RS1CONTSAV_SAVE_RS1	(2<<14) /* rs1 saves context */
1311 #define   RS1CONTSAV_FULL_RS1	(3<<14) /* rs1 saves and restores context */
1312 #define   NORMSLEXLAT_MASK	(3<<12)
1313 #define   SLOW_RS123		(0<<12)
1314 #define   SLOW_RS23		(1<<12)
1315 #define   SLOW_RS3		(2<<12)
1316 #define   NORMAL_RS123		(3<<12)
1317 #define   RCMODE_TIMEOUT	(1<<11) /* 0 is eval interval method */
1318 #define   IMPROMOEN		(1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1319 #define   RCENTSYNC		(1<<9) /* rs coupled to cpu c-state (3/6/7) */
1320 #define   STATELOCK		(1<<7) /* locked to rs_cstate if 0 */
1321 #define   RS_CSTATE_MASK	(3<<4)
1322 #define   RS_CSTATE_C367_RS1	(0<<4)
1323 #define   RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1324 #define   RS_CSTATE_RSVD	(2<<4)
1325 #define   RS_CSTATE_C367_RS2	(3<<4)
1326 #define   REDSAVES		(1<<3) /* no context save if was idle during rs0 */
1327 #define   REDRESTORES		(1<<2) /* no restore if was idle during rs0 */
1328 #define VIDCTL			0x111c0
1329 #define VIDSTS			0x111c8
1330 #define VIDSTART		0x111cc /* 8 bits */
1331 #define MEMSTAT_ILK			0x111f8
1332 #define   MEMSTAT_VID_MASK	0x7f00
1333 #define   MEMSTAT_VID_SHIFT	8
1334 #define   MEMSTAT_PSTATE_MASK	0x00f8
1335 #define   MEMSTAT_PSTATE_SHIFT  3
1336 #define   MEMSTAT_MON_ACTV	(1<<2)
1337 #define   MEMSTAT_SRC_CTL_MASK	0x0003
1338 #define   MEMSTAT_SRC_CTL_CORE	0
1339 #define   MEMSTAT_SRC_CTL_TRB	1
1340 #define   MEMSTAT_SRC_CTL_THM	2
1341 #define   MEMSTAT_SRC_CTL_STDBY 3
1342 #define RCPREVBSYTUPAVG		0x113b8
1343 #define RCPREVBSYTDNAVG		0x113bc
1344 #define PMMISC			0x11214
1345 #define   MCPPCE_EN		(1<<0) /* enable PM_MSG from PCH->MPC */
1346 #define SDEW			0x1124c
1347 #define CSIEW0			0x11250
1348 #define CSIEW1			0x11254
1349 #define CSIEW2			0x11258
1350 #define PEW			0x1125c
1351 #define DEW			0x11270
1352 #define MCHAFE			0x112c0
1353 #define CSIEC			0x112e0
1354 #define DMIEC			0x112e4
1355 #define DDREC			0x112e8
1356 #define PEG0EC			0x112ec
1357 #define PEG1EC			0x112f0
1358 #define GFXEC			0x112f4
1359 #define RPPREVBSYTUPAVG		0x113b8
1360 #define RPPREVBSYTDNAVG		0x113bc
1361 #define ECR			0x11600
1362 #define   ECR_GPFE		(1<<31)
1363 #define   ECR_IMONE		(1<<30)
1364 #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
1365 #define OGW0			0x11608
1366 #define OGW1			0x1160c
1367 #define EG0			0x11610
1368 #define EG1			0x11614
1369 #define EG2			0x11618
1370 #define EG3			0x1161c
1371 #define EG4			0x11620
1372 #define EG5			0x11624
1373 #define EG6			0x11628
1374 #define EG7			0x1162c
1375 #define PXW			0x11664
1376 #define PXWL			0x11680
1377 #define LCFUSE02		0x116c0
1378 #define   LCFUSE_HIV_MASK	0x000000ff
1379 #define CSIPLL0			0x12c10
1380 #define DDRMPLL1		0X12c20
1381 #define PEG_BAND_GAP_DATA	0x14d68
1382 
1383 #define GEN6_GT_PERF_STATUS	0x145948
1384 #define GEN6_RP_STATE_LIMITS	0x145994
1385 #define GEN6_RP_STATE_CAP	0x145998
1386 
1387 /*
1388  * Logical Context regs
1389  */
1390 #define CCID			0x2180
1391 #define   CCID_EN		(1<<0)
1392 /*
1393  * Overlay regs
1394  */
1395 
1396 #define OVADD			0x30000
1397 #define DOVSTA			0x30008
1398 #define OC_BUF			(0x3<<20)
1399 #define OGAMC5			0x30010
1400 #define OGAMC4			0x30014
1401 #define OGAMC3			0x30018
1402 #define OGAMC2			0x3001c
1403 #define OGAMC1			0x30020
1404 #define OGAMC0			0x30024
1405 
1406 /*
1407  * Display engine regs
1408  */
1409 
1410 /* Pipe A timing regs */
1411 #define _HTOTAL_A	0x60000
1412 #define _HBLANK_A	0x60004
1413 #define _HSYNC_A		0x60008
1414 #define _VTOTAL_A	0x6000c
1415 #define _VBLANK_A	0x60010
1416 #define _VSYNC_A		0x60014
1417 #define _PIPEASRC	0x6001c
1418 #define _BCLRPAT_A	0x60020
1419 #define _VSYNCSHIFT_A	0x60028
1420 
1421 /* Pipe B timing regs */
1422 #define _HTOTAL_B	0x61000
1423 #define _HBLANK_B	0x61004
1424 #define _HSYNC_B		0x61008
1425 #define _VTOTAL_B	0x6100c
1426 #define _VBLANK_B	0x61010
1427 #define _VSYNC_B		0x61014
1428 #define _PIPEBSRC	0x6101c
1429 #define _BCLRPAT_B	0x61020
1430 #define _VSYNCSHIFT_B	0x61028
1431 
1432 
1433 #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1434 #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1435 #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1436 #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1437 #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1438 #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1439 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1440 #define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
1441 
1442 /* VGA port control */
1443 #define ADPA			0x61100
1444 #define   ADPA_DAC_ENABLE	(1<<31)
1445 #define   ADPA_DAC_DISABLE	0
1446 #define   ADPA_PIPE_SELECT_MASK	(1<<30)
1447 #define   ADPA_PIPE_A_SELECT	0
1448 #define   ADPA_PIPE_B_SELECT	(1<<30)
1449 #define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1450 #define   ADPA_USE_VGA_HVPOLARITY (1<<15)
1451 #define   ADPA_SETS_HVPOLARITY	0
1452 #define   ADPA_VSYNC_CNTL_DISABLE (1<<11)
1453 #define   ADPA_VSYNC_CNTL_ENABLE 0
1454 #define   ADPA_HSYNC_CNTL_DISABLE (1<<10)
1455 #define   ADPA_HSYNC_CNTL_ENABLE 0
1456 #define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1457 #define   ADPA_VSYNC_ACTIVE_LOW	0
1458 #define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1459 #define   ADPA_HSYNC_ACTIVE_LOW	0
1460 #define   ADPA_DPMS_MASK	(~(3<<10))
1461 #define   ADPA_DPMS_ON		(0<<10)
1462 #define   ADPA_DPMS_SUSPEND	(1<<10)
1463 #define   ADPA_DPMS_STANDBY	(2<<10)
1464 #define   ADPA_DPMS_OFF		(3<<10)
1465 
1466 
1467 /* Hotplug control (945+ only) */
1468 #define PORT_HOTPLUG_EN		0x61110
1469 #define   HDMIB_HOTPLUG_INT_EN			(1 << 29)
1470 #define   DPB_HOTPLUG_INT_EN			(1 << 29)
1471 #define   HDMIC_HOTPLUG_INT_EN			(1 << 28)
1472 #define   DPC_HOTPLUG_INT_EN			(1 << 28)
1473 #define   HDMID_HOTPLUG_INT_EN			(1 << 27)
1474 #define   DPD_HOTPLUG_INT_EN			(1 << 27)
1475 #define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
1476 #define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
1477 #define   TV_HOTPLUG_INT_EN			(1 << 18)
1478 #define   CRT_HOTPLUG_INT_EN			(1 << 9)
1479 #define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
1480 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
1481 /* must use period 64 on GM45 according to docs */
1482 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
1483 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
1484 #define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
1485 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
1486 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
1487 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
1488 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
1489 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
1490 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
1491 #define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
1492 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
1493 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
1494 
1495 #define PORT_HOTPLUG_STAT	0x61114
1496 #define   HDMIB_HOTPLUG_INT_STATUS		(1 << 29)
1497 #define   DPB_HOTPLUG_INT_STATUS		(1 << 29)
1498 #define   HDMIC_HOTPLUG_INT_STATUS		(1 << 28)
1499 #define   DPC_HOTPLUG_INT_STATUS		(1 << 28)
1500 #define   HDMID_HOTPLUG_INT_STATUS		(1 << 27)
1501 #define   DPD_HOTPLUG_INT_STATUS		(1 << 27)
1502 /* CRT/TV common between gen3+ */
1503 #define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
1504 #define   TV_HOTPLUG_INT_STATUS			(1 << 10)
1505 #define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
1506 #define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
1507 #define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
1508 #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
1509 /* SDVO is different across gen3/4 */
1510 #define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
1511 #define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
1512 #define   SDVOC_HOTPLUG_INT_STATUS_I965		(3 << 4)
1513 #define   SDVOB_HOTPLUG_INT_STATUS_I965		(3 << 2)
1514 #define   SDVOC_HOTPLUG_INT_STATUS_I915		(1 << 7)
1515 #define   SDVOB_HOTPLUG_INT_STATUS_I915		(1 << 6)
1516 
1517 /* SDVO port control */
1518 #define SDVOB			0x61140
1519 #define SDVOC			0x61160
1520 #define   SDVO_ENABLE		(1 << 31)
1521 #define   SDVO_PIPE_B_SELECT	(1 << 30)
1522 #define   SDVO_STALL_SELECT	(1 << 29)
1523 #define   SDVO_INTERRUPT_ENABLE	(1 << 26)
1524 /**
1525  * 915G/GM SDVO pixel multiplier.
1526  *
1527  * Programmed value is multiplier - 1, up to 5x.
1528  *
1529  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1530  */
1531 #define   SDVO_PORT_MULTIPLY_MASK	(7 << 23)
1532 #define   SDVO_PORT_MULTIPLY_SHIFT		23
1533 #define   SDVO_PHASE_SELECT_MASK	(15 << 19)
1534 #define   SDVO_PHASE_SELECT_DEFAULT	(6 << 19)
1535 #define   SDVO_CLOCK_OUTPUT_INVERT	(1 << 18)
1536 #define   SDVOC_GANG_MODE		(1 << 16)
1537 #define   SDVO_ENCODING_SDVO		(0x0 << 10)
1538 #define   SDVO_ENCODING_HDMI		(0x2 << 10)
1539 /** Requird for HDMI operation */
1540 #define   SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1541 #define   SDVO_COLOR_RANGE_16_235	(1 << 8)
1542 #define   SDVO_BORDER_ENABLE		(1 << 7)
1543 #define   SDVO_AUDIO_ENABLE		(1 << 6)
1544 /** New with 965, default is to be set */
1545 #define   SDVO_VSYNC_ACTIVE_HIGH	(1 << 4)
1546 /** New with 965, default is to be set */
1547 #define   SDVO_HSYNC_ACTIVE_HIGH	(1 << 3)
1548 #define   SDVOB_PCIE_CONCURRENCY	(1 << 3)
1549 #define   SDVO_DETECTED			(1 << 2)
1550 /* Bits to be preserved when writing */
1551 #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1552 #define   SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1553 
1554 /* DVO port control */
1555 #define DVOA			0x61120
1556 #define DVOB			0x61140
1557 #define DVOC			0x61160
1558 #define   DVO_ENABLE			(1 << 31)
1559 #define   DVO_PIPE_B_SELECT		(1 << 30)
1560 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
1561 #define   DVO_PIPE_STALL		(1 << 28)
1562 #define   DVO_PIPE_STALL_TV		(2 << 28)
1563 #define   DVO_PIPE_STALL_MASK		(3 << 28)
1564 #define   DVO_USE_VGA_SYNC		(1 << 15)
1565 #define   DVO_DATA_ORDER_I740		(0 << 14)
1566 #define   DVO_DATA_ORDER_FP		(1 << 14)
1567 #define   DVO_VSYNC_DISABLE		(1 << 11)
1568 #define   DVO_HSYNC_DISABLE		(1 << 10)
1569 #define   DVO_VSYNC_TRISTATE		(1 << 9)
1570 #define   DVO_HSYNC_TRISTATE		(1 << 8)
1571 #define   DVO_BORDER_ENABLE		(1 << 7)
1572 #define   DVO_DATA_ORDER_GBRG		(1 << 6)
1573 #define   DVO_DATA_ORDER_RGGB		(0 << 6)
1574 #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
1575 #define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
1576 #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
1577 #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
1578 #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
1579 #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
1580 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
1581 #define   DVO_PRESERVE_MASK		(0x7<<24)
1582 #define DVOA_SRCDIM		0x61124
1583 #define DVOB_SRCDIM		0x61144
1584 #define DVOC_SRCDIM		0x61164
1585 #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
1586 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
1587 
1588 /* LVDS port control */
1589 #define LVDS			0x61180
1590 /*
1591  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
1592  * the DPLL semantics change when the LVDS is assigned to that pipe.
1593  */
1594 #define   LVDS_PORT_EN			(1 << 31)
1595 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
1596 #define   LVDS_PIPEB_SELECT		(1 << 30)
1597 #define   LVDS_PIPE_MASK		(1 << 30)
1598 #define   LVDS_PIPE(pipe)		((pipe) << 30)
1599 /* LVDS dithering flag on 965/g4x platform */
1600 #define   LVDS_ENABLE_DITHER		(1 << 25)
1601 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
1602 #define   LVDS_VSYNC_POLARITY		(1 << 21)
1603 #define   LVDS_HSYNC_POLARITY		(1 << 20)
1604 
1605 /* Enable border for unscaled (or aspect-scaled) display */
1606 #define   LVDS_BORDER_ENABLE		(1 << 15)
1607 /*
1608  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1609  * pixel.
1610  */
1611 #define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
1612 #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
1613 #define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
1614 /*
1615  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1616  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1617  * on.
1618  */
1619 #define   LVDS_A3_POWER_MASK		(3 << 6)
1620 #define   LVDS_A3_POWER_DOWN		(0 << 6)
1621 #define   LVDS_A3_POWER_UP		(3 << 6)
1622 /*
1623  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
1624  * is set.
1625  */
1626 #define   LVDS_CLKB_POWER_MASK		(3 << 4)
1627 #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
1628 #define   LVDS_CLKB_POWER_UP		(3 << 4)
1629 /*
1630  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
1631  * setting for whether we are in dual-channel mode.  The B3 pair will
1632  * additionally only be powered up when LVDS_A3_POWER_UP is set.
1633  */
1634 #define   LVDS_B0B3_POWER_MASK		(3 << 2)
1635 #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
1636 #define   LVDS_B0B3_POWER_UP		(3 << 2)
1637 
1638 /* Video Data Island Packet control */
1639 #define VIDEO_DIP_DATA		0x61178
1640 #define VIDEO_DIP_CTL		0x61170
1641 #define   VIDEO_DIP_ENABLE		(1 << 31)
1642 #define   VIDEO_DIP_PORT_B		(1 << 29)
1643 #define   VIDEO_DIP_PORT_C		(2 << 29)
1644 #define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
1645 #define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
1646 #define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
1647 #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
1648 #define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
1649 #define   VIDEO_DIP_SELECT_SPD		(3 << 19)
1650 #define   VIDEO_DIP_SELECT_MASK		(3 << 19)
1651 #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
1652 #define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
1653 #define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
1654 
1655 /* Panel power sequencing */
1656 #define PP_STATUS	0x61200
1657 #define   PP_ON		(1 << 31)
1658 /*
1659  * Indicates that all dependencies of the panel are on:
1660  *
1661  * - PLL enabled
1662  * - pipe enabled
1663  * - LVDS/DVOB/DVOC on
1664  */
1665 #define   PP_READY		(1 << 30)
1666 #define   PP_SEQUENCE_NONE	(0 << 28)
1667 #define   PP_SEQUENCE_POWER_UP	(1 << 28)
1668 #define   PP_SEQUENCE_POWER_DOWN (2 << 28)
1669 #define   PP_SEQUENCE_MASK	(3 << 28)
1670 #define   PP_SEQUENCE_SHIFT	28
1671 #define   PP_CYCLE_DELAY_ACTIVE	(1 << 27)
1672 #define   PP_SEQUENCE_STATE_MASK 0x0000000f
1673 #define   PP_SEQUENCE_STATE_OFF_IDLE	(0x0 << 0)
1674 #define   PP_SEQUENCE_STATE_OFF_S0_1	(0x1 << 0)
1675 #define   PP_SEQUENCE_STATE_OFF_S0_2	(0x2 << 0)
1676 #define   PP_SEQUENCE_STATE_OFF_S0_3	(0x3 << 0)
1677 #define   PP_SEQUENCE_STATE_ON_IDLE	(0x8 << 0)
1678 #define   PP_SEQUENCE_STATE_ON_S1_0	(0x9 << 0)
1679 #define   PP_SEQUENCE_STATE_ON_S1_2	(0xa << 0)
1680 #define   PP_SEQUENCE_STATE_ON_S1_3	(0xb << 0)
1681 #define   PP_SEQUENCE_STATE_RESET	(0xf << 0)
1682 #define PP_CONTROL	0x61204
1683 #define   POWER_TARGET_ON	(1 << 0)
1684 #define PP_ON_DELAYS	0x61208
1685 #define PP_OFF_DELAYS	0x6120c
1686 #define PP_DIVISOR	0x61210
1687 
1688 /* Panel fitting */
1689 #define PFIT_CONTROL	0x61230
1690 #define   PFIT_ENABLE		(1 << 31)
1691 #define   PFIT_PIPE_MASK	(3 << 29)
1692 #define   PFIT_PIPE_SHIFT	29
1693 #define   VERT_INTERP_DISABLE	(0 << 10)
1694 #define   VERT_INTERP_BILINEAR	(1 << 10)
1695 #define   VERT_INTERP_MASK	(3 << 10)
1696 #define   VERT_AUTO_SCALE	(1 << 9)
1697 #define   HORIZ_INTERP_DISABLE	(0 << 6)
1698 #define   HORIZ_INTERP_BILINEAR	(1 << 6)
1699 #define   HORIZ_INTERP_MASK	(3 << 6)
1700 #define   HORIZ_AUTO_SCALE	(1 << 5)
1701 #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
1702 #define   PFIT_FILTER_FUZZY	(0 << 24)
1703 #define   PFIT_SCALING_AUTO	(0 << 26)
1704 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
1705 #define   PFIT_SCALING_PILLAR	(2 << 26)
1706 #define   PFIT_SCALING_LETTER	(3 << 26)
1707 #define PFIT_PGM_RATIOS	0x61234
1708 #define   PFIT_VERT_SCALE_MASK			0xfff00000
1709 #define   PFIT_HORIZ_SCALE_MASK			0x0000fff0
1710 /* Pre-965 */
1711 #define		PFIT_VERT_SCALE_SHIFT		20
1712 #define		PFIT_VERT_SCALE_MASK		0xfff00000
1713 #define		PFIT_HORIZ_SCALE_SHIFT		4
1714 #define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
1715 /* 965+ */
1716 #define		PFIT_VERT_SCALE_SHIFT_965	16
1717 #define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
1718 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
1719 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
1720 
1721 #define PFIT_AUTO_RATIOS 0x61238
1722 
1723 /* Backlight control */
1724 #define BLC_PWM_CTL		0x61254
1725 #define   BACKLIGHT_MODULATION_FREQ_SHIFT		(17)
1726 #define BLC_PWM_CTL2		0x61250 /* 965+ only */
1727 #define   BLM_COMBINATION_MODE (1 << 30)
1728 /*
1729  * This is the most significant 15 bits of the number of backlight cycles in a
1730  * complete cycle of the modulated backlight control.
1731  *
1732  * The actual value is this field multiplied by two.
1733  */
1734 #define   BACKLIGHT_MODULATION_FREQ_MASK		(0x7fff << 17)
1735 #define   BLM_LEGACY_MODE				(1 << 16)
1736 /*
1737  * This is the number of cycles out of the backlight modulation cycle for which
1738  * the backlight is on.
1739  *
1740  * This field must be no greater than the number of cycles in the complete
1741  * backlight modulation cycle.
1742  */
1743 #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
1744 #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
1745 
1746 #define BLC_HIST_CTL		0x61260
1747 
1748 /* TV port control */
1749 #define TV_CTL			0x68000
1750 /** Enables the TV encoder */
1751 # define TV_ENC_ENABLE			(1 << 31)
1752 /** Sources the TV encoder input from pipe B instead of A. */
1753 # define TV_ENC_PIPEB_SELECT		(1 << 30)
1754 /** Outputs composite video (DAC A only) */
1755 # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
1756 /** Outputs SVideo video (DAC B/C) */
1757 # define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
1758 /** Outputs Component video (DAC A/B/C) */
1759 # define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
1760 /** Outputs Composite and SVideo (DAC A/B/C) */
1761 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
1762 # define TV_TRILEVEL_SYNC		(1 << 21)
1763 /** Enables slow sync generation (945GM only) */
1764 # define TV_SLOW_SYNC			(1 << 20)
1765 /** Selects 4x oversampling for 480i and 576p */
1766 # define TV_OVERSAMPLE_4X		(0 << 18)
1767 /** Selects 2x oversampling for 720p and 1080i */
1768 # define TV_OVERSAMPLE_2X		(1 << 18)
1769 /** Selects no oversampling for 1080p */
1770 # define TV_OVERSAMPLE_NONE		(2 << 18)
1771 /** Selects 8x oversampling */
1772 # define TV_OVERSAMPLE_8X		(3 << 18)
1773 /** Selects progressive mode rather than interlaced */
1774 # define TV_PROGRESSIVE			(1 << 17)
1775 /** Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
1776 # define TV_PAL_BURST			(1 << 16)
1777 /** Field for setting delay of Y compared to C */
1778 # define TV_YC_SKEW_MASK		(7 << 12)
1779 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1780 # define TV_ENC_SDP_FIX			(1 << 11)
1781 /**
1782  * Enables a fix for the 915GM only.
1783  *
1784  * Not sure what it does.
1785  */
1786 # define TV_ENC_C0_FIX			(1 << 10)
1787 /** Bits that must be preserved by software */
1788 # define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1789 # define TV_FUSE_STATE_MASK		(3 << 4)
1790 /** Read-only state that reports all features enabled */
1791 # define TV_FUSE_STATE_ENABLED		(0 << 4)
1792 /** Read-only state that reports that Macrovision is disabled in hardware*/
1793 # define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
1794 /** Read-only state that reports that TV-out is disabled in hardware. */
1795 # define TV_FUSE_STATE_DISABLED		(2 << 4)
1796 /** Normal operation */
1797 # define TV_TEST_MODE_NORMAL		(0 << 0)
1798 /** Encoder test pattern 1 - combo pattern */
1799 # define TV_TEST_MODE_PATTERN_1		(1 << 0)
1800 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1801 # define TV_TEST_MODE_PATTERN_2		(2 << 0)
1802 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1803 # define TV_TEST_MODE_PATTERN_3		(3 << 0)
1804 /** Encoder test pattern 4 - random noise */
1805 # define TV_TEST_MODE_PATTERN_4		(4 << 0)
1806 /** Encoder test pattern 5 - linear color ramps */
1807 # define TV_TEST_MODE_PATTERN_5		(5 << 0)
1808 /**
1809  * This test mode forces the DACs to 50% of full output.
1810  *
1811  * This is used for load detection in combination with TVDAC_SENSE_MASK
1812  */
1813 # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
1814 # define TV_TEST_MODE_MASK		(7 << 0)
1815 
1816 #define TV_DAC			0x68004
1817 # define TV_DAC_SAVE		0x00ffff00
1818 /**
1819  * Reports that DAC state change logic has reported change (RO).
1820  *
1821  * This gets cleared when TV_DAC_STATE_EN is cleared
1822 */
1823 # define TVDAC_STATE_CHG		(1 << 31)
1824 # define TVDAC_SENSE_MASK		(7 << 28)
1825 /** Reports that DAC A voltage is above the detect threshold */
1826 # define TVDAC_A_SENSE			(1 << 30)
1827 /** Reports that DAC B voltage is above the detect threshold */
1828 # define TVDAC_B_SENSE			(1 << 29)
1829 /** Reports that DAC C voltage is above the detect threshold */
1830 # define TVDAC_C_SENSE			(1 << 28)
1831 /**
1832  * Enables DAC state detection logic, for load-based TV detection.
1833  *
1834  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1835  * to off, for load detection to work.
1836  */
1837 # define TVDAC_STATE_CHG_EN		(1 << 27)
1838 /** Sets the DAC A sense value to high */
1839 # define TVDAC_A_SENSE_CTL		(1 << 26)
1840 /** Sets the DAC B sense value to high */
1841 # define TVDAC_B_SENSE_CTL		(1 << 25)
1842 /** Sets the DAC C sense value to high */
1843 # define TVDAC_C_SENSE_CTL		(1 << 24)
1844 /** Overrides the ENC_ENABLE and DAC voltage levels */
1845 # define DAC_CTL_OVERRIDE		(1 << 7)
1846 /** Sets the slew rate.  Must be preserved in software */
1847 # define ENC_TVDAC_SLEW_FAST		(1 << 6)
1848 # define DAC_A_1_3_V			(0 << 4)
1849 # define DAC_A_1_1_V			(1 << 4)
1850 # define DAC_A_0_7_V			(2 << 4)
1851 # define DAC_A_MASK			(3 << 4)
1852 # define DAC_B_1_3_V			(0 << 2)
1853 # define DAC_B_1_1_V			(1 << 2)
1854 # define DAC_B_0_7_V			(2 << 2)
1855 # define DAC_B_MASK			(3 << 2)
1856 # define DAC_C_1_3_V			(0 << 0)
1857 # define DAC_C_1_1_V			(1 << 0)
1858 # define DAC_C_0_7_V			(2 << 0)
1859 # define DAC_C_MASK			(3 << 0)
1860 
1861 /**
1862  * CSC coefficients are stored in a floating point format with 9 bits of
1863  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
1864  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1865  * -1 (0x3) being the only legal negative value.
1866  */
1867 #define TV_CSC_Y		0x68010
1868 # define TV_RY_MASK			0x07ff0000
1869 # define TV_RY_SHIFT			16
1870 # define TV_GY_MASK			0x00000fff
1871 # define TV_GY_SHIFT			0
1872 
1873 #define TV_CSC_Y2		0x68014
1874 # define TV_BY_MASK			0x07ff0000
1875 # define TV_BY_SHIFT			16
1876 /**
1877  * Y attenuation for component video.
1878  *
1879  * Stored in 1.9 fixed point.
1880  */
1881 # define TV_AY_MASK			0x000003ff
1882 # define TV_AY_SHIFT			0
1883 
1884 #define TV_CSC_U		0x68018
1885 # define TV_RU_MASK			0x07ff0000
1886 # define TV_RU_SHIFT			16
1887 # define TV_GU_MASK			0x000007ff
1888 # define TV_GU_SHIFT			0
1889 
1890 #define TV_CSC_U2		0x6801c
1891 # define TV_BU_MASK			0x07ff0000
1892 # define TV_BU_SHIFT			16
1893 /**
1894  * U attenuation for component video.
1895  *
1896  * Stored in 1.9 fixed point.
1897  */
1898 # define TV_AU_MASK			0x000003ff
1899 # define TV_AU_SHIFT			0
1900 
1901 #define TV_CSC_V		0x68020
1902 # define TV_RV_MASK			0x0fff0000
1903 # define TV_RV_SHIFT			16
1904 # define TV_GV_MASK			0x000007ff
1905 # define TV_GV_SHIFT			0
1906 
1907 #define TV_CSC_V2		0x68024
1908 # define TV_BV_MASK			0x07ff0000
1909 # define TV_BV_SHIFT			16
1910 /**
1911  * V attenuation for component video.
1912  *
1913  * Stored in 1.9 fixed point.
1914  */
1915 # define TV_AV_MASK			0x000007ff
1916 # define TV_AV_SHIFT			0
1917 
1918 #define TV_CLR_KNOBS		0x68028
1919 /** 2s-complement brightness adjustment */
1920 # define TV_BRIGHTNESS_MASK		0xff000000
1921 # define TV_BRIGHTNESS_SHIFT		24
1922 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1923 # define TV_CONTRAST_MASK		0x00ff0000
1924 # define TV_CONTRAST_SHIFT		16
1925 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1926 # define TV_SATURATION_MASK		0x0000ff00
1927 # define TV_SATURATION_SHIFT		8
1928 /** Hue adjustment, as an integer phase angle in degrees */
1929 # define TV_HUE_MASK			0x000000ff
1930 # define TV_HUE_SHIFT			0
1931 
1932 #define TV_CLR_LEVEL		0x6802c
1933 /** Controls the DAC level for black */
1934 # define TV_BLACK_LEVEL_MASK		0x01ff0000
1935 # define TV_BLACK_LEVEL_SHIFT		16
1936 /** Controls the DAC level for blanking */
1937 # define TV_BLANK_LEVEL_MASK		0x000001ff
1938 # define TV_BLANK_LEVEL_SHIFT		0
1939 
1940 #define TV_H_CTL_1		0x68030
1941 /** Number of pixels in the hsync. */
1942 # define TV_HSYNC_END_MASK		0x1fff0000
1943 # define TV_HSYNC_END_SHIFT		16
1944 /** Total number of pixels minus one in the line (display and blanking). */
1945 # define TV_HTOTAL_MASK			0x00001fff
1946 # define TV_HTOTAL_SHIFT		0
1947 
1948 #define TV_H_CTL_2		0x68034
1949 /** Enables the colorburst (needed for non-component color) */
1950 # define TV_BURST_ENA			(1 << 31)
1951 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1952 # define TV_HBURST_START_SHIFT		16
1953 # define TV_HBURST_START_MASK		0x1fff0000
1954 /** Length of the colorburst */
1955 # define TV_HBURST_LEN_SHIFT		0
1956 # define TV_HBURST_LEN_MASK		0x0001fff
1957 
1958 #define TV_H_CTL_3		0x68038
1959 /** End of hblank, measured in pixels minus one from start of hsync */
1960 # define TV_HBLANK_END_SHIFT		16
1961 # define TV_HBLANK_END_MASK		0x1fff0000
1962 /** Start of hblank, measured in pixels minus one from start of hsync */
1963 # define TV_HBLANK_START_SHIFT		0
1964 # define TV_HBLANK_START_MASK		0x0001fff
1965 
1966 #define TV_V_CTL_1		0x6803c
1967 /** XXX */
1968 # define TV_NBR_END_SHIFT		16
1969 # define TV_NBR_END_MASK		0x07ff0000
1970 /** XXX */
1971 # define TV_VI_END_F1_SHIFT		8
1972 # define TV_VI_END_F1_MASK		0x00003f00
1973 /** XXX */
1974 # define TV_VI_END_F2_SHIFT		0
1975 # define TV_VI_END_F2_MASK		0x0000003f
1976 
1977 #define TV_V_CTL_2		0x68040
1978 /** Length of vsync, in half lines */
1979 # define TV_VSYNC_LEN_MASK		0x07ff0000
1980 # define TV_VSYNC_LEN_SHIFT		16
1981 /** Offset of the start of vsync in field 1, measured in one less than the
1982  * number of half lines.
1983  */
1984 # define TV_VSYNC_START_F1_MASK		0x00007f00
1985 # define TV_VSYNC_START_F1_SHIFT	8
1986 /**
1987  * Offset of the start of vsync in field 2, measured in one less than the
1988  * number of half lines.
1989  */
1990 # define TV_VSYNC_START_F2_MASK		0x0000007f
1991 # define TV_VSYNC_START_F2_SHIFT	0
1992 
1993 #define TV_V_CTL_3		0x68044
1994 /** Enables generation of the equalization signal */
1995 # define TV_EQUAL_ENA			(1 << 31)
1996 /** Length of vsync, in half lines */
1997 # define TV_VEQ_LEN_MASK		0x007f0000
1998 # define TV_VEQ_LEN_SHIFT		16
1999 /** Offset of the start of equalization in field 1, measured in one less than
2000  * the number of half lines.
2001  */
2002 # define TV_VEQ_START_F1_MASK		0x0007f00
2003 # define TV_VEQ_START_F1_SHIFT		8
2004 /**
2005  * Offset of the start of equalization in field 2, measured in one less than
2006  * the number of half lines.
2007  */
2008 # define TV_VEQ_START_F2_MASK		0x000007f
2009 # define TV_VEQ_START_F2_SHIFT		0
2010 
2011 #define TV_V_CTL_4		0x68048
2012 /**
2013  * Offset to start of vertical colorburst, measured in one less than the
2014  * number of lines from vertical start.
2015  */
2016 # define TV_VBURST_START_F1_MASK	0x003f0000
2017 # define TV_VBURST_START_F1_SHIFT	16
2018 /**
2019  * Offset to the end of vertical colorburst, measured in one less than the
2020  * number of lines from the start of NBR.
2021  */
2022 # define TV_VBURST_END_F1_MASK		0x000000ff
2023 # define TV_VBURST_END_F1_SHIFT		0
2024 
2025 #define TV_V_CTL_5		0x6804c
2026 /**
2027  * Offset to start of vertical colorburst, measured in one less than the
2028  * number of lines from vertical start.
2029  */
2030 # define TV_VBURST_START_F2_MASK	0x003f0000
2031 # define TV_VBURST_START_F2_SHIFT	16
2032 /**
2033  * Offset to the end of vertical colorburst, measured in one less than the
2034  * number of lines from the start of NBR.
2035  */
2036 # define TV_VBURST_END_F2_MASK		0x000000ff
2037 # define TV_VBURST_END_F2_SHIFT		0
2038 
2039 #define TV_V_CTL_6		0x68050
2040 /**
2041  * Offset to start of vertical colorburst, measured in one less than the
2042  * number of lines from vertical start.
2043  */
2044 # define TV_VBURST_START_F3_MASK	0x003f0000
2045 # define TV_VBURST_START_F3_SHIFT	16
2046 /**
2047  * Offset to the end of vertical colorburst, measured in one less than the
2048  * number of lines from the start of NBR.
2049  */
2050 # define TV_VBURST_END_F3_MASK		0x000000ff
2051 # define TV_VBURST_END_F3_SHIFT		0
2052 
2053 #define TV_V_CTL_7		0x68054
2054 /**
2055  * Offset to start of vertical colorburst, measured in one less than the
2056  * number of lines from vertical start.
2057  */
2058 # define TV_VBURST_START_F4_MASK	0x003f0000
2059 # define TV_VBURST_START_F4_SHIFT	16
2060 /**
2061  * Offset to the end of vertical colorburst, measured in one less than the
2062  * number of lines from the start of NBR.
2063  */
2064 # define TV_VBURST_END_F4_MASK		0x000000ff
2065 # define TV_VBURST_END_F4_SHIFT		0
2066 
2067 #define TV_SC_CTL_1		0x68060
2068 /** Turns on the first subcarrier phase generation DDA */
2069 # define TV_SC_DDA1_EN			(1 << 31)
2070 /** Turns on the first subcarrier phase generation DDA */
2071 # define TV_SC_DDA2_EN			(1 << 30)
2072 /** Turns on the first subcarrier phase generation DDA */
2073 # define TV_SC_DDA3_EN			(1 << 29)
2074 /** Sets the subcarrier DDA to reset frequency every other field */
2075 # define TV_SC_RESET_EVERY_2		(0 << 24)
2076 /** Sets the subcarrier DDA to reset frequency every fourth field */
2077 # define TV_SC_RESET_EVERY_4		(1 << 24)
2078 /** Sets the subcarrier DDA to reset frequency every eighth field */
2079 # define TV_SC_RESET_EVERY_8		(2 << 24)
2080 /** Sets the subcarrier DDA to never reset the frequency */
2081 # define TV_SC_RESET_NEVER		(3 << 24)
2082 /** Sets the peak amplitude of the colorburst.*/
2083 # define TV_BURST_LEVEL_MASK		0x00ff0000
2084 # define TV_BURST_LEVEL_SHIFT		16
2085 /** Sets the increment of the first subcarrier phase generation DDA */
2086 # define TV_SCDDA1_INC_MASK		0x00000fff
2087 # define TV_SCDDA1_INC_SHIFT		0
2088 
2089 #define TV_SC_CTL_2		0x68064
2090 /** Sets the rollover for the second subcarrier phase generation DDA */
2091 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
2092 # define TV_SCDDA2_SIZE_SHIFT		16
2093 /** Sets the increent of the second subcarrier phase generation DDA */
2094 # define TV_SCDDA2_INC_MASK		0x00007fff
2095 # define TV_SCDDA2_INC_SHIFT		0
2096 
2097 #define TV_SC_CTL_3		0x68068
2098 /** Sets the rollover for the third subcarrier phase generation DDA */
2099 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
2100 # define TV_SCDDA3_SIZE_SHIFT		16
2101 /** Sets the increent of the third subcarrier phase generation DDA */
2102 # define TV_SCDDA3_INC_MASK		0x00007fff
2103 # define TV_SCDDA3_INC_SHIFT		0
2104 
2105 #define TV_WIN_POS		0x68070
2106 /** X coordinate of the display from the start of horizontal active */
2107 # define TV_XPOS_MASK			0x1fff0000
2108 # define TV_XPOS_SHIFT			16
2109 /** Y coordinate of the display from the start of vertical active (NBR) */
2110 # define TV_YPOS_MASK			0x00000fff
2111 # define TV_YPOS_SHIFT			0
2112 
2113 #define TV_WIN_SIZE		0x68074
2114 /** Horizontal size of the display window, measured in pixels*/
2115 # define TV_XSIZE_MASK			0x1fff0000
2116 # define TV_XSIZE_SHIFT			16
2117 /**
2118  * Vertical size of the display window, measured in pixels.
2119  *
2120  * Must be even for interlaced modes.
2121  */
2122 # define TV_YSIZE_MASK			0x00000fff
2123 # define TV_YSIZE_SHIFT			0
2124 
2125 #define TV_FILTER_CTL_1		0x68080
2126 /**
2127  * Enables automatic scaling calculation.
2128  *
2129  * If set, the rest of the registers are ignored, and the calculated values can
2130  * be read back from the register.
2131  */
2132 # define TV_AUTO_SCALE			(1 << 31)
2133 /**
2134  * Disables the vertical filter.
2135  *
2136  * This is required on modes more than 1024 pixels wide */
2137 # define TV_V_FILTER_BYPASS		(1 << 29)
2138 /** Enables adaptive vertical filtering */
2139 # define TV_VADAPT			(1 << 28)
2140 # define TV_VADAPT_MODE_MASK		(3 << 26)
2141 /** Selects the least adaptive vertical filtering mode */
2142 # define TV_VADAPT_MODE_LEAST		(0 << 26)
2143 /** Selects the moderately adaptive vertical filtering mode */
2144 # define TV_VADAPT_MODE_MODERATE	(1 << 26)
2145 /** Selects the most adaptive vertical filtering mode */
2146 # define TV_VADAPT_MODE_MOST		(3 << 26)
2147 /**
2148  * Sets the horizontal scaling factor.
2149  *
2150  * This should be the fractional part of the horizontal scaling factor divided
2151  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
2152  *
2153  * (src width - 1) / ((oversample * dest width) - 1)
2154  */
2155 # define TV_HSCALE_FRAC_MASK		0x00003fff
2156 # define TV_HSCALE_FRAC_SHIFT		0
2157 
2158 #define TV_FILTER_CTL_2		0x68084
2159 /**
2160  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2161  *
2162  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2163  */
2164 # define TV_VSCALE_INT_MASK		0x00038000
2165 # define TV_VSCALE_INT_SHIFT		15
2166 /**
2167  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2168  *
2169  * \sa TV_VSCALE_INT_MASK
2170  */
2171 # define TV_VSCALE_FRAC_MASK		0x00007fff
2172 # define TV_VSCALE_FRAC_SHIFT		0
2173 
2174 #define TV_FILTER_CTL_3		0x68088
2175 /**
2176  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2177  *
2178  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2179  *
2180  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2181  */
2182 # define TV_VSCALE_IP_INT_MASK		0x00038000
2183 # define TV_VSCALE_IP_INT_SHIFT		15
2184 /**
2185  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2186  *
2187  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2188  *
2189  * \sa TV_VSCALE_IP_INT_MASK
2190  */
2191 # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
2192 # define TV_VSCALE_IP_FRAC_SHIFT		0
2193 
2194 #define TV_CC_CONTROL		0x68090
2195 # define TV_CC_ENABLE			(1 << 31)
2196 /**
2197  * Specifies which field to send the CC data in.
2198  *
2199  * CC data is usually sent in field 0.
2200  */
2201 # define TV_CC_FID_MASK			(1 << 27)
2202 # define TV_CC_FID_SHIFT		27
2203 /** Sets the horizontal position of the CC data.  Usually 135. */
2204 # define TV_CC_HOFF_MASK		0x03ff0000
2205 # define TV_CC_HOFF_SHIFT		16
2206 /** Sets the vertical position of the CC data.  Usually 21 */
2207 # define TV_CC_LINE_MASK		0x0000003f
2208 # define TV_CC_LINE_SHIFT		0
2209 
2210 #define TV_CC_DATA		0x68094
2211 # define TV_CC_RDY			(1 << 31)
2212 /** Second word of CC data to be transmitted. */
2213 # define TV_CC_DATA_2_MASK		0x007f0000
2214 # define TV_CC_DATA_2_SHIFT		16
2215 /** First word of CC data to be transmitted. */
2216 # define TV_CC_DATA_1_MASK		0x0000007f
2217 # define TV_CC_DATA_1_SHIFT		0
2218 
2219 #define TV_H_LUMA_0		0x68100
2220 #define TV_H_LUMA_59		0x681ec
2221 #define TV_H_CHROMA_0		0x68200
2222 #define TV_H_CHROMA_59		0x682ec
2223 #define TV_V_LUMA_0		0x68300
2224 #define TV_V_LUMA_42		0x683a8
2225 #define TV_V_CHROMA_0		0x68400
2226 #define TV_V_CHROMA_42		0x684a8
2227 
2228 /* Display Port */
2229 #define DP_A				0x64000 /* eDP */
2230 #define DP_B				0x64100
2231 #define DP_C				0x64200
2232 #define DP_D				0x64300
2233 
2234 #define   DP_PORT_EN			(1 << 31)
2235 #define   DP_PIPEB_SELECT		(1 << 30)
2236 #define   DP_PIPE_MASK			(1 << 30)
2237 
2238 /* Link training mode - select a suitable mode for each stage */
2239 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
2240 #define   DP_LINK_TRAIN_PAT_2		(1 << 28)
2241 #define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
2242 #define   DP_LINK_TRAIN_OFF		(3 << 28)
2243 #define   DP_LINK_TRAIN_MASK		(3 << 28)
2244 #define   DP_LINK_TRAIN_SHIFT		28
2245 
2246 /* CPT Link training mode */
2247 #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
2248 #define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
2249 #define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
2250 #define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
2251 #define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
2252 #define   DP_LINK_TRAIN_SHIFT_CPT	8
2253 
2254 /* Signal voltages. These are mostly controlled by the other end */
2255 #define   DP_VOLTAGE_0_4		(0 << 25)
2256 #define   DP_VOLTAGE_0_6		(1 << 25)
2257 #define   DP_VOLTAGE_0_8		(2 << 25)
2258 #define   DP_VOLTAGE_1_2		(3 << 25)
2259 #define   DP_VOLTAGE_MASK		(7 << 25)
2260 #define   DP_VOLTAGE_SHIFT		25
2261 
2262 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2263  * they want
2264  */
2265 #define   DP_PRE_EMPHASIS_0		(0 << 22)
2266 #define   DP_PRE_EMPHASIS_3_5		(1 << 22)
2267 #define   DP_PRE_EMPHASIS_6		(2 << 22)
2268 #define   DP_PRE_EMPHASIS_9_5		(3 << 22)
2269 #define   DP_PRE_EMPHASIS_MASK		(7 << 22)
2270 #define   DP_PRE_EMPHASIS_SHIFT		22
2271 
2272 /* How many wires to use. I guess 3 was too hard */
2273 #define   DP_PORT_WIDTH_1		(0 << 19)
2274 #define   DP_PORT_WIDTH_2		(1 << 19)
2275 #define   DP_PORT_WIDTH_4		(3 << 19)
2276 #define   DP_PORT_WIDTH_MASK		(7 << 19)
2277 
2278 /* Mystic DPCD version 1.1 special mode */
2279 #define   DP_ENHANCED_FRAMING		(1 << 18)
2280 
2281 /* eDP */
2282 #define   DP_PLL_FREQ_270MHZ		(0 << 16)
2283 #define   DP_PLL_FREQ_160MHZ		(1 << 16)
2284 #define   DP_PLL_FREQ_MASK		(3 << 16)
2285 
2286 /** locked once port is enabled */
2287 #define   DP_PORT_REVERSAL		(1 << 15)
2288 
2289 /* eDP */
2290 #define   DP_PLL_ENABLE			(1 << 14)
2291 
2292 /** sends the clock on lane 15 of the PEG for debug */
2293 #define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
2294 
2295 #define   DP_SCRAMBLING_DISABLE		(1 << 12)
2296 #define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
2297 
2298 /** limit RGB values to avoid confusing TVs */
2299 #define   DP_COLOR_RANGE_16_235		(1 << 8)
2300 
2301 /** Turn on the audio link */
2302 #define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
2303 
2304 /** vs and hs sync polarity */
2305 #define   DP_SYNC_VS_HIGH		(1 << 4)
2306 #define   DP_SYNC_HS_HIGH		(1 << 3)
2307 
2308 /** A fantasy */
2309 #define   DP_DETECTED			(1 << 2)
2310 
2311 /** The aux channel provides a way to talk to the
2312  * signal sink for DDC etc. Max packet size supported
2313  * is 20 bytes in each direction, hence the 5 fixed
2314  * data registers
2315  */
2316 #define DPA_AUX_CH_CTL			0x64010
2317 #define DPA_AUX_CH_DATA1		0x64014
2318 #define DPA_AUX_CH_DATA2		0x64018
2319 #define DPA_AUX_CH_DATA3		0x6401c
2320 #define DPA_AUX_CH_DATA4		0x64020
2321 #define DPA_AUX_CH_DATA5		0x64024
2322 
2323 #define DPB_AUX_CH_CTL			0x64110
2324 #define DPB_AUX_CH_DATA1		0x64114
2325 #define DPB_AUX_CH_DATA2		0x64118
2326 #define DPB_AUX_CH_DATA3		0x6411c
2327 #define DPB_AUX_CH_DATA4		0x64120
2328 #define DPB_AUX_CH_DATA5		0x64124
2329 
2330 #define DPC_AUX_CH_CTL			0x64210
2331 #define DPC_AUX_CH_DATA1		0x64214
2332 #define DPC_AUX_CH_DATA2		0x64218
2333 #define DPC_AUX_CH_DATA3		0x6421c
2334 #define DPC_AUX_CH_DATA4		0x64220
2335 #define DPC_AUX_CH_DATA5		0x64224
2336 
2337 #define DPD_AUX_CH_CTL			0x64310
2338 #define DPD_AUX_CH_DATA1		0x64314
2339 #define DPD_AUX_CH_DATA2		0x64318
2340 #define DPD_AUX_CH_DATA3		0x6431c
2341 #define DPD_AUX_CH_DATA4		0x64320
2342 #define DPD_AUX_CH_DATA5		0x64324
2343 
2344 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
2345 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
2346 #define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
2347 #define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
2348 #define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
2349 #define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
2350 #define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
2351 #define   DP_AUX_CH_CTL_TIME_OUT_1600us	    (3 << 26)
2352 #define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
2353 #define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
2354 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
2355 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
2356 #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
2357 #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
2358 #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
2359 #define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
2360 #define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
2361 #define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
2362 #define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
2363 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
2364 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
2365 
2366 /*
2367  * Computing GMCH M and N values for the Display Port link
2368  *
2369  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2370  *
2371  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2372  *
2373  * The GMCH value is used internally
2374  *
2375  * bytes_per_pixel is the number of bytes coming out of the plane,
2376  * which is after the LUTs, so we want the bytes for our color format.
2377  * For our current usage, this is always 3, one byte for R, G and B.
2378  */
2379 #define _PIPEA_GMCH_DATA_M			0x70050
2380 #define _PIPEB_GMCH_DATA_M			0x71050
2381 
2382 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2383 #define   PIPE_GMCH_DATA_M_TU_SIZE_MASK		(0x3f << 25)
2384 #define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT	25
2385 
2386 #define   PIPE_GMCH_DATA_M_MASK			(0xffffff)
2387 
2388 #define _PIPEA_GMCH_DATA_N			0x70054
2389 #define _PIPEB_GMCH_DATA_N			0x71054
2390 #define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
2391 
2392 /*
2393  * Computing Link M and N values for the Display Port link
2394  *
2395  * Link M / N = pixel_clock / ls_clk
2396  *
2397  * (the DP spec calls pixel_clock the 'strm_clk')
2398  *
2399  * The Link value is transmitted in the Main Stream
2400  * Attributes and VB-ID.
2401  */
2402 
2403 #define _PIPEA_DP_LINK_M				0x70060
2404 #define _PIPEB_DP_LINK_M				0x71060
2405 #define   PIPEA_DP_LINK_M_MASK			(0xffffff)
2406 
2407 #define _PIPEA_DP_LINK_N				0x70064
2408 #define _PIPEB_DP_LINK_N				0x71064
2409 #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
2410 
2411 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2412 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2413 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2414 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2415 
2416 /* Display & cursor control */
2417 
2418 /* Pipe A */
2419 #define _PIPEADSL		0x70000
2420 #define   DSL_LINEMASK		0x00000fff
2421 #define _PIPEACONF		0x70008
2422 #define   PIPECONF_ENABLE	(1<<31)
2423 #define   PIPECONF_DISABLE	0
2424 #define   PIPECONF_DOUBLE_WIDE	(1<<30)
2425 #define   I965_PIPECONF_ACTIVE	(1<<30)
2426 #define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
2427 #define   PIPECONF_SINGLE_WIDE	0
2428 #define   PIPECONF_PIPE_UNLOCKED 0
2429 #define   PIPECONF_PIPE_LOCKED	(1<<25)
2430 #define   PIPECONF_PALETTE	0
2431 #define   PIPECONF_GAMMA		(1<<24)
2432 #define   PIPECONF_FORCE_BORDER	(1<<25)
2433 #define   PIPECONF_INTERLACE_MASK	(7 << 21)
2434 /* Note that pre-gen3 does not support interlaced display directly. Panel
2435  * fitting must be disabled on pre-ilk for interlaced. */
2436 #define   PIPECONF_PROGRESSIVE			(0 << 21)
2437 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
2438 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
2439 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
2440 #define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
2441 /* Ironlake and later have a complete new set of values for interlaced. PFIT
2442  * means panel fitter required, PF means progressive fetch, DBL means power
2443  * saving pixel doubling. */
2444 #define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
2445 #define   PIPECONF_INTERLACED_ILK		(3 << 21)
2446 #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
2447 #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
2448 #define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
2449 #define   PIPECONF_BPP_MASK	(0x000000e0)
2450 #define   PIPECONF_BPP_8	(0<<5)
2451 #define   PIPECONF_BPP_10	(1<<5)
2452 #define   PIPECONF_BPP_6	(2<<5)
2453 #define   PIPECONF_BPP_12	(3<<5)
2454 #define   PIPECONF_DITHER_EN	(1<<4)
2455 #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2456 #define   PIPECONF_DITHER_TYPE_SP (0<<2)
2457 #define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
2458 #define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
2459 #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
2460 #define _PIPEASTAT		0x70024
2461 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
2462 #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
2463 #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
2464 #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
2465 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
2466 #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
2467 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
2468 #define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
2469 #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
2470 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
2471 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
2472 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
2473 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
2474 #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
2475 #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
2476 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
2477 #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
2478 #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
2479 #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
2480 #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
2481 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
2482 #define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
2483 #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
2484 #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
2485 #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
2486 #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
2487 #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
2488 #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
2489 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
2490 #define   PIPE_BPC_MASK				(7 << 5) /* Ironlake */
2491 #define   PIPE_8BPC				(0 << 5)
2492 #define   PIPE_10BPC				(1 << 5)
2493 #define   PIPE_6BPC				(2 << 5)
2494 #define   PIPE_12BPC				(3 << 5)
2495 
2496 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2497 #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2498 #define PIPEDSL(pipe)  _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2499 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2500 #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2501 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2502 
2503 #define DSPARB			0x70030
2504 #define   DSPARB_CSTART_MASK	(0x7f << 7)
2505 #define   DSPARB_CSTART_SHIFT	7
2506 #define   DSPARB_BSTART_MASK	(0x7f)
2507 #define   DSPARB_BSTART_SHIFT	0
2508 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
2509 #define   DSPARB_AEND_SHIFT	0
2510 
2511 #define DSPFW1			0x70034
2512 #define   DSPFW_SR_SHIFT	23
2513 #define   DSPFW_SR_MASK		(0x1ff<<23)
2514 #define   DSPFW_CURSORB_SHIFT	16
2515 #define   DSPFW_CURSORB_MASK	(0x3f<<16)
2516 #define   DSPFW_PLANEB_SHIFT	8
2517 #define   DSPFW_PLANEB_MASK	(0x7f<<8)
2518 #define   DSPFW_PLANEA_MASK	(0x7f)
2519 #define DSPFW2			0x70038
2520 #define   DSPFW_CURSORA_MASK	0x00003f00
2521 #define   DSPFW_CURSORA_SHIFT	8
2522 #define   DSPFW_PLANEC_MASK	(0x7f)
2523 #define DSPFW3			0x7003c
2524 #define   DSPFW_HPLL_SR_EN	(1<<31)
2525 #define   DSPFW_CURSOR_SR_SHIFT	24
2526 #define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
2527 #define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
2528 #define   DSPFW_HPLL_CURSOR_SHIFT	16
2529 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
2530 #define   DSPFW_HPLL_SR_MASK		(0x1ff)
2531 
2532 /* FIFO watermark sizes etc */
2533 #define G4X_FIFO_LINE_SIZE	64
2534 #define I915_FIFO_LINE_SIZE	64
2535 #define I830_FIFO_LINE_SIZE	32
2536 
2537 #define G4X_FIFO_SIZE		127
2538 #define I965_FIFO_SIZE		512
2539 #define I945_FIFO_SIZE		127
2540 #define I915_FIFO_SIZE		95
2541 #define I855GM_FIFO_SIZE	127 /* In cachelines */
2542 #define I830_FIFO_SIZE		95
2543 
2544 #define G4X_MAX_WM		0x3f
2545 #define I915_MAX_WM		0x3f
2546 
2547 #define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
2548 #define PINEVIEW_FIFO_LINE_SIZE	64
2549 #define PINEVIEW_MAX_WM		0x1ff
2550 #define PINEVIEW_DFT_WM		0x3f
2551 #define PINEVIEW_DFT_HPLLOFF_WM	0
2552 #define PINEVIEW_GUARD_WM		10
2553 #define PINEVIEW_CURSOR_FIFO		64
2554 #define PINEVIEW_CURSOR_MAX_WM	0x3f
2555 #define PINEVIEW_CURSOR_DFT_WM	0
2556 #define PINEVIEW_CURSOR_GUARD_WM	5
2557 
2558 #define I965_CURSOR_FIFO	64
2559 #define I965_CURSOR_MAX_WM	32
2560 #define I965_CURSOR_DFT_WM	8
2561 
2562 /* define the Watermark register on Ironlake */
2563 #define WM0_PIPEA_ILK		0x45100
2564 #define  WM0_PIPE_PLANE_MASK	(0x7f<<16)
2565 #define  WM0_PIPE_PLANE_SHIFT	16
2566 #define  WM0_PIPE_SPRITE_MASK	(0x3f<<8)
2567 #define  WM0_PIPE_SPRITE_SHIFT	8
2568 #define  WM0_PIPE_CURSOR_MASK	(0x1f)
2569 
2570 #define WM0_PIPEB_ILK		0x45104
2571 #define WM0_PIPEC_IVB		0x45200
2572 #define WM1_LP_ILK		0x45108
2573 #define  WM1_LP_SR_EN		(1<<31)
2574 #define  WM1_LP_LATENCY_SHIFT	24
2575 #define  WM1_LP_LATENCY_MASK	(0x7f<<24)
2576 #define  WM1_LP_FBC_MASK	(0xf<<20)
2577 #define  WM1_LP_FBC_SHIFT	20
2578 #define  WM1_LP_SR_MASK		(0x1ff<<8)
2579 #define  WM1_LP_SR_SHIFT	8
2580 #define  WM1_LP_CURSOR_MASK	(0x3f)
2581 #define WM2_LP_ILK		0x4510c
2582 #define  WM2_LP_EN		(1<<31)
2583 #define WM3_LP_ILK		0x45110
2584 #define  WM3_LP_EN		(1<<31)
2585 #define WM1S_LP_ILK		0x45120
2586 #define WM2S_LP_IVB		0x45124
2587 #define WM3S_LP_IVB		0x45128
2588 #define  WM1S_LP_EN		(1<<31)
2589 
2590 /* Memory latency timer register */
2591 #define MLTR_ILK		0x11222
2592 #define  MLTR_WM1_SHIFT		0
2593 #define  MLTR_WM2_SHIFT		8
2594 /* the unit of memory self-refresh latency time is 0.5us */
2595 #define  ILK_SRLT_MASK		0x3f
2596 #define ILK_LATENCY(shift)	(I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2597 #define ILK_READ_WM1_LATENCY()	ILK_LATENCY(MLTR_WM1_SHIFT)
2598 #define ILK_READ_WM2_LATENCY()	ILK_LATENCY(MLTR_WM2_SHIFT)
2599 
2600 /* define the fifo size on Ironlake */
2601 #define ILK_DISPLAY_FIFO	128
2602 #define ILK_DISPLAY_MAXWM	64
2603 #define ILK_DISPLAY_DFTWM	8
2604 #define ILK_CURSOR_FIFO		32
2605 #define ILK_CURSOR_MAXWM	16
2606 #define ILK_CURSOR_DFTWM	8
2607 
2608 #define ILK_DISPLAY_SR_FIFO	512
2609 #define ILK_DISPLAY_MAX_SRWM	0x1ff
2610 #define ILK_DISPLAY_DFT_SRWM	0x3f
2611 #define ILK_CURSOR_SR_FIFO	64
2612 #define ILK_CURSOR_MAX_SRWM	0x3f
2613 #define ILK_CURSOR_DFT_SRWM	8
2614 
2615 #define ILK_FIFO_LINE_SIZE	64
2616 
2617 /* define the WM info on Sandybridge */
2618 #define SNB_DISPLAY_FIFO	128
2619 #define SNB_DISPLAY_MAXWM	0x7f	/* bit 16:22 */
2620 #define SNB_DISPLAY_DFTWM	8
2621 #define SNB_CURSOR_FIFO		32
2622 #define SNB_CURSOR_MAXWM	0x1f	/* bit 4:0 */
2623 #define SNB_CURSOR_DFTWM	8
2624 
2625 #define SNB_DISPLAY_SR_FIFO	512
2626 #define SNB_DISPLAY_MAX_SRWM	0x1ff	/* bit 16:8 */
2627 #define SNB_DISPLAY_DFT_SRWM	0x3f
2628 #define SNB_CURSOR_SR_FIFO	64
2629 #define SNB_CURSOR_MAX_SRWM	0x3f	/* bit 5:0 */
2630 #define SNB_CURSOR_DFT_SRWM	8
2631 
2632 #define SNB_FBC_MAX_SRWM	0xf	/* bit 23:20 */
2633 
2634 #define SNB_FIFO_LINE_SIZE	64
2635 
2636 
2637 /* the address where we get all kinds of latency value */
2638 #define SSKPD			0x5d10
2639 #define SSKPD_WM_MASK		0x3f
2640 #define SSKPD_WM0_SHIFT		0
2641 #define SSKPD_WM1_SHIFT		8
2642 #define SSKPD_WM2_SHIFT		16
2643 #define SSKPD_WM3_SHIFT		24
2644 
2645 #define SNB_LATENCY(shift)	(I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2646 #define SNB_READ_WM0_LATENCY()		SNB_LATENCY(SSKPD_WM0_SHIFT)
2647 #define SNB_READ_WM1_LATENCY()		SNB_LATENCY(SSKPD_WM1_SHIFT)
2648 #define SNB_READ_WM2_LATENCY()		SNB_LATENCY(SSKPD_WM2_SHIFT)
2649 #define SNB_READ_WM3_LATENCY()		SNB_LATENCY(SSKPD_WM3_SHIFT)
2650 
2651 /*
2652  * The two pipe frame counter registers are not synchronized, so
2653  * reading a stable value is somewhat tricky. The following code
2654  * should work:
2655  *
2656  *  do {
2657  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2658  *             PIPE_FRAME_HIGH_SHIFT;
2659  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2660  *             PIPE_FRAME_LOW_SHIFT);
2661  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2662  *             PIPE_FRAME_HIGH_SHIFT);
2663  *  } while (high1 != high2);
2664  *  frame = (high1 << 8) | low1;
2665  */
2666 #define _PIPEAFRAMEHIGH          0x70040
2667 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
2668 #define   PIPE_FRAME_HIGH_SHIFT   0
2669 #define _PIPEAFRAMEPIXEL         0x70044
2670 #define   PIPE_FRAME_LOW_MASK     0xff000000
2671 #define   PIPE_FRAME_LOW_SHIFT    24
2672 #define   PIPE_PIXEL_MASK         0x00ffffff
2673 #define   PIPE_PIXEL_SHIFT        0
2674 /* GM45+ just has to be different */
2675 #define _PIPEA_FRMCOUNT_GM45	0x70040
2676 #define _PIPEA_FLIPCOUNT_GM45	0x70044
2677 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2678 
2679 /* Cursor A & B regs */
2680 #define _CURACNTR		0x70080
2681 /* Old style CUR*CNTR flags (desktop 8xx) */
2682 #define   CURSOR_ENABLE		0x80000000
2683 #define   CURSOR_GAMMA_ENABLE	0x40000000
2684 #define   CURSOR_STRIDE_MASK	0x30000000
2685 #define   CURSOR_FORMAT_SHIFT	24
2686 #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
2687 #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
2688 #define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
2689 #define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
2690 #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
2691 #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
2692 /* New style CUR*CNTR flags */
2693 #define   CURSOR_MODE		0x27
2694 #define   CURSOR_MODE_DISABLE   0x00
2695 #define   CURSOR_MODE_64_32B_AX 0x07
2696 #define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2697 #define   MCURSOR_PIPE_SELECT	(1 << 28)
2698 #define   MCURSOR_PIPE_A	0x00
2699 #define   MCURSOR_PIPE_B	(1 << 28)
2700 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
2701 #define _CURABASE		0x70084
2702 #define _CURAPOS			0x70088
2703 #define   CURSOR_POS_MASK       0x007FF
2704 #define   CURSOR_POS_SIGN       0x8000
2705 #define   CURSOR_X_SHIFT        0
2706 #define   CURSOR_Y_SHIFT        16
2707 #define CURSIZE			0x700a0
2708 #define _CURBCNTR		0x700c0
2709 #define _CURBBASE		0x700c4
2710 #define _CURBPOS			0x700c8
2711 
2712 #define _CURBCNTR_IVB		0x71080
2713 #define _CURBBASE_IVB		0x71084
2714 #define _CURBPOS_IVB		0x71088
2715 
2716 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2717 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2718 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2719 
2720 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
2721 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
2722 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
2723 
2724 /* Display A control */
2725 #define _DSPACNTR                0x70180
2726 #define   DISPLAY_PLANE_ENABLE			(1<<31)
2727 #define   DISPLAY_PLANE_DISABLE			0
2728 #define   DISPPLANE_GAMMA_ENABLE		(1<<30)
2729 #define   DISPPLANE_GAMMA_DISABLE		0
2730 #define   DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
2731 #define   DISPPLANE_8BPP			(0x2<<26)
2732 #define   DISPPLANE_15_16BPP			(0x4<<26)
2733 #define   DISPPLANE_16BPP			(0x5<<26)
2734 #define   DISPPLANE_32BPP_NO_ALPHA		(0x6<<26)
2735 #define   DISPPLANE_32BPP			(0x7<<26)
2736 #define   DISPPLANE_32BPP_30BIT_NO_ALPHA	(0xa<<26)
2737 #define   DISPPLANE_STEREO_ENABLE		(1<<25)
2738 #define   DISPPLANE_STEREO_DISABLE		0
2739 #define   DISPPLANE_SEL_PIPE_SHIFT		24
2740 #define   DISPPLANE_SEL_PIPE_MASK		(3<<DISPPLANE_SEL_PIPE_SHIFT)
2741 #define   DISPPLANE_SEL_PIPE_A			0
2742 #define   DISPPLANE_SEL_PIPE_B			(1<<DISPPLANE_SEL_PIPE_SHIFT)
2743 #define   DISPPLANE_SRC_KEY_ENABLE		(1<<22)
2744 #define   DISPPLANE_SRC_KEY_DISABLE		0
2745 #define   DISPPLANE_LINE_DOUBLE			(1<<20)
2746 #define   DISPPLANE_NO_LINE_DOUBLE		0
2747 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
2748 #define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
2749 #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
2750 #define   DISPPLANE_TILED			(1<<10)
2751 #define _DSPAADDR		0x70184
2752 #define _DSPASTRIDE		0x70188
2753 #define _DSPAPOS			0x7018C /* reserved */
2754 #define _DSPASIZE		0x70190
2755 #define _DSPASURF		0x7019C /* 965+ only */
2756 #define _DSPATILEOFF		0x701A4 /* 965+ only */
2757 
2758 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2759 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2760 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2761 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2762 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2763 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2764 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
2765 
2766 /* VBIOS flags */
2767 #define SWF00			0x71410
2768 #define SWF01			0x71414
2769 #define SWF02			0x71418
2770 #define SWF03			0x7141c
2771 #define SWF04			0x71420
2772 #define SWF05			0x71424
2773 #define SWF06			0x71428
2774 #define SWF10			0x70410
2775 #define SWF11			0x70414
2776 #define SWF14			0x71420
2777 #define SWF30			0x72414
2778 #define SWF31			0x72418
2779 #define SWF32			0x7241c
2780 
2781 /* Pipe B */
2782 #define _PIPEBDSL		0x71000
2783 #define _PIPEBCONF		0x71008
2784 #define _PIPEBSTAT		0x71024
2785 #define _PIPEBFRAMEHIGH		0x71040
2786 #define _PIPEBFRAMEPIXEL		0x71044
2787 #define _PIPEB_FRMCOUNT_GM45	0x71040
2788 #define _PIPEB_FLIPCOUNT_GM45	0x71044
2789 
2790 
2791 /* Display B control */
2792 #define _DSPBCNTR		0x71180
2793 #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
2794 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
2795 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
2796 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
2797 #define _DSPBADDR		0x71184
2798 #define _DSPBSTRIDE		0x71188
2799 #define _DSPBPOS			0x7118C
2800 #define _DSPBSIZE		0x71190
2801 #define _DSPBSURF		0x7119C
2802 #define _DSPBTILEOFF		0x711A4
2803 
2804 /* Sprite A control */
2805 #define _DVSACNTR		0x72180
2806 #define   DVS_ENABLE		(1<<31)
2807 #define   DVS_GAMMA_ENABLE	(1<<30)
2808 #define   DVS_PIXFORMAT_MASK	(3<<25)
2809 #define   DVS_FORMAT_YUV422	(0<<25)
2810 #define   DVS_FORMAT_RGBX101010	(1<<25)
2811 #define   DVS_FORMAT_RGBX888	(2<<25)
2812 #define   DVS_FORMAT_RGBX161616	(3<<25)
2813 #define   DVS_SOURCE_KEY	(1<<22)
2814 #define   DVS_RGB_ORDER_XBGR	(1<<20)
2815 #define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
2816 #define   DVS_YUV_ORDER_YUYV	(0<<16)
2817 #define   DVS_YUV_ORDER_UYVY	(1<<16)
2818 #define   DVS_YUV_ORDER_YVYU	(2<<16)
2819 #define   DVS_YUV_ORDER_VYUY	(3<<16)
2820 #define   DVS_DEST_KEY		(1<<2)
2821 #define   DVS_TRICKLE_FEED_DISABLE (1<<14)
2822 #define   DVS_TILED		(1<<10)
2823 #define _DVSALINOFF		0x72184
2824 #define _DVSASTRIDE		0x72188
2825 #define _DVSAPOS		0x7218c
2826 #define _DVSASIZE		0x72190
2827 #define _DVSAKEYVAL		0x72194
2828 #define _DVSAKEYMSK		0x72198
2829 #define _DVSASURF		0x7219c
2830 #define _DVSAKEYMAXVAL		0x721a0
2831 #define _DVSATILEOFF		0x721a4
2832 #define _DVSASURFLIVE		0x721ac
2833 #define _DVSASCALE		0x72204
2834 #define   DVS_SCALE_ENABLE	(1<<31)
2835 #define   DVS_FILTER_MASK	(3<<29)
2836 #define   DVS_FILTER_MEDIUM	(0<<29)
2837 #define   DVS_FILTER_ENHANCING	(1<<29)
2838 #define   DVS_FILTER_SOFTENING	(2<<29)
2839 #define   DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
2840 #define   DVS_VERTICAL_OFFSET_ENABLE (1<<27)
2841 #define _DVSAGAMC		0x72300
2842 
2843 #define _DVSBCNTR		0x73180
2844 #define _DVSBLINOFF		0x73184
2845 #define _DVSBSTRIDE		0x73188
2846 #define _DVSBPOS		0x7318c
2847 #define _DVSBSIZE		0x73190
2848 #define _DVSBKEYVAL		0x73194
2849 #define _DVSBKEYMSK		0x73198
2850 #define _DVSBSURF		0x7319c
2851 #define _DVSBKEYMAXVAL		0x731a0
2852 #define _DVSBTILEOFF		0x731a4
2853 #define _DVSBSURFLIVE		0x731ac
2854 #define _DVSBSCALE		0x73204
2855 #define _DVSBGAMC		0x73300
2856 
2857 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
2858 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
2859 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
2860 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
2861 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
2862 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
2863 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
2864 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
2865 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
2866 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
2867 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
2868 
2869 #define _SPRA_CTL		0x70280
2870 #define   SPRITE_ENABLE			(1<<31)
2871 #define   SPRITE_GAMMA_ENABLE		(1<<30)
2872 #define   SPRITE_PIXFORMAT_MASK		(7<<25)
2873 #define   SPRITE_FORMAT_YUV422		(0<<25)
2874 #define   SPRITE_FORMAT_RGBX101010	(1<<25)
2875 #define   SPRITE_FORMAT_RGBX888		(2<<25)
2876 #define   SPRITE_FORMAT_RGBX161616	(3<<25)
2877 #define   SPRITE_FORMAT_YUV444		(4<<25)
2878 #define   SPRITE_FORMAT_XR_BGR101010	(5<<25) /* Extended range */
2879 #define   SPRITE_CSC_ENABLE		(1<<24)
2880 #define   SPRITE_SOURCE_KEY		(1<<22)
2881 #define   SPRITE_RGB_ORDER_RGBX		(1<<20) /* only for 888 and 161616 */
2882 #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1<<19)
2883 #define   SPRITE_YUV_CSC_FORMAT_BT709	(1<<18) /* 0 is BT601 */
2884 #define   SPRITE_YUV_BYTE_ORDER_MASK	(3<<16)
2885 #define   SPRITE_YUV_ORDER_YUYV		(0<<16)
2886 #define   SPRITE_YUV_ORDER_UYVY		(1<<16)
2887 #define   SPRITE_YUV_ORDER_YVYU		(2<<16)
2888 #define   SPRITE_YUV_ORDER_VYUY		(3<<16)
2889 #define   SPRITE_TRICKLE_FEED_DISABLE	(1<<14)
2890 #define   SPRITE_INT_GAMMA_ENABLE	(1<<13)
2891 #define   SPRITE_TILED			(1<<10)
2892 #define   SPRITE_DEST_KEY		(1<<2)
2893 #define _SPRA_LINOFF		0x70284
2894 #define _SPRA_STRIDE		0x70288
2895 #define _SPRA_POS		0x7028c
2896 #define _SPRA_SIZE		0x70290
2897 #define _SPRA_KEYVAL		0x70294
2898 #define _SPRA_KEYMSK		0x70298
2899 #define _SPRA_SURF		0x7029c
2900 #define _SPRA_KEYMAX		0x702a0
2901 #define _SPRA_TILEOFF		0x702a4
2902 #define _SPRA_SCALE		0x70304
2903 #define   SPRITE_SCALE_ENABLE	(1<<31)
2904 #define   SPRITE_FILTER_MASK	(3<<29)
2905 #define   SPRITE_FILTER_MEDIUM	(0<<29)
2906 #define   SPRITE_FILTER_ENHANCING	(1<<29)
2907 #define   SPRITE_FILTER_SOFTENING	(2<<29)
2908 #define   SPRITE_VERTICAL_OFFSET_HALF	(1<<28) /* must be enabled below */
2909 #define   SPRITE_VERTICAL_OFFSET_ENABLE	(1<<27)
2910 #define _SPRA_GAMC		0x70400
2911 
2912 #define _SPRB_CTL		0x71280
2913 #define _SPRB_LINOFF		0x71284
2914 #define _SPRB_STRIDE		0x71288
2915 #define _SPRB_POS		0x7128c
2916 #define _SPRB_SIZE		0x71290
2917 #define _SPRB_KEYVAL		0x71294
2918 #define _SPRB_KEYMSK		0x71298
2919 #define _SPRB_SURF		0x7129c
2920 #define _SPRB_KEYMAX		0x712a0
2921 #define _SPRB_TILEOFF		0x712a4
2922 #define _SPRB_SCALE		0x71304
2923 #define _SPRB_GAMC		0x71400
2924 
2925 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
2926 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
2927 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
2928 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
2929 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
2930 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
2931 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
2932 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
2933 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
2934 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
2935 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
2936 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
2937 
2938 /* VBIOS regs */
2939 #define VGACNTRL		0x71400
2940 # define VGA_DISP_DISABLE			(1 << 31)
2941 # define VGA_2X_MODE				(1 << 30)
2942 # define VGA_PIPE_B_SELECT			(1 << 29)
2943 
2944 /* Ironlake */
2945 
2946 #define CPU_VGACNTRL	0x41000
2947 
2948 #define DIGITAL_PORT_HOTPLUG_CNTRL      0x44030
2949 #define  DIGITAL_PORTA_HOTPLUG_ENABLE           (1 << 4)
2950 #define  DIGITAL_PORTA_SHORT_PULSE_2MS          (0 << 2)
2951 #define  DIGITAL_PORTA_SHORT_PULSE_4_5MS        (1 << 2)
2952 #define  DIGITAL_PORTA_SHORT_PULSE_6MS          (2 << 2)
2953 #define  DIGITAL_PORTA_SHORT_PULSE_100MS        (3 << 2)
2954 #define  DIGITAL_PORTA_NO_DETECT                (0 << 0)
2955 #define  DIGITAL_PORTA_LONG_PULSE_DETECT_MASK   (1 << 1)
2956 #define  DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK  (1 << 0)
2957 
2958 /* refresh rate hardware control */
2959 #define RR_HW_CTL       0x45300
2960 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
2961 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
2962 
2963 #define FDI_PLL_BIOS_0  0x46000
2964 #define  FDI_PLL_FB_CLOCK_MASK  0xff
2965 #define FDI_PLL_BIOS_1  0x46004
2966 #define FDI_PLL_BIOS_2  0x46008
2967 #define DISPLAY_PORT_PLL_BIOS_0         0x4600c
2968 #define DISPLAY_PORT_PLL_BIOS_1         0x46010
2969 #define DISPLAY_PORT_PLL_BIOS_2         0x46014
2970 
2971 #define PCH_DSPCLK_GATE_D	0x42020
2972 # define DPFCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
2973 # define DPFCRUNIT_CLOCK_GATE_DISABLE		(1 << 8)
2974 # define DPFDUNIT_CLOCK_GATE_DISABLE		(1 << 7)
2975 # define DPARBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
2976 
2977 #define PCH_3DCGDIS0		0x46020
2978 # define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
2979 # define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
2980 
2981 #define PCH_3DCGDIS1		0x46024
2982 # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
2983 
2984 #define FDI_PLL_FREQ_CTL        0x46030
2985 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
2986 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
2987 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
2988 
2989 
2990 #define _PIPEA_DATA_M1           0x60030
2991 #define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
2992 #define  TU_SIZE_MASK           0x7e000000
2993 #define  PIPE_DATA_M1_OFFSET    0
2994 #define _PIPEA_DATA_N1           0x60034
2995 #define  PIPE_DATA_N1_OFFSET    0
2996 
2997 #define _PIPEA_DATA_M2           0x60038
2998 #define  PIPE_DATA_M2_OFFSET    0
2999 #define _PIPEA_DATA_N2           0x6003c
3000 #define  PIPE_DATA_N2_OFFSET    0
3001 
3002 #define _PIPEA_LINK_M1           0x60040
3003 #define  PIPE_LINK_M1_OFFSET    0
3004 #define _PIPEA_LINK_N1           0x60044
3005 #define  PIPE_LINK_N1_OFFSET    0
3006 
3007 #define _PIPEA_LINK_M2           0x60048
3008 #define  PIPE_LINK_M2_OFFSET    0
3009 #define _PIPEA_LINK_N2           0x6004c
3010 #define  PIPE_LINK_N2_OFFSET    0
3011 
3012 /* PIPEB timing regs are same start from 0x61000 */
3013 
3014 #define _PIPEB_DATA_M1           0x61030
3015 #define _PIPEB_DATA_N1           0x61034
3016 
3017 #define _PIPEB_DATA_M2           0x61038
3018 #define _PIPEB_DATA_N2           0x6103c
3019 
3020 #define _PIPEB_LINK_M1           0x61040
3021 #define _PIPEB_LINK_N1           0x61044
3022 
3023 #define _PIPEB_LINK_M2           0x61048
3024 #define _PIPEB_LINK_N2           0x6104c
3025 
3026 #define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3027 #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3028 #define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3029 #define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3030 #define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3031 #define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3032 #define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3033 #define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
3034 
3035 /* CPU panel fitter */
3036 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3037 #define _PFA_CTL_1               0x68080
3038 #define _PFB_CTL_1               0x68880
3039 #define  PF_ENABLE              (1<<31)
3040 #define  PF_PIPE_SEL_MASK_IVB	(3<<29)
3041 #define  PF_PIPE_SEL_IVB(pipe)	((pipe)<<29)
3042 #define  PF_FILTER_MASK		(3<<23)
3043 #define  PF_FILTER_PROGRAMMED	(0<<23)
3044 #define  PF_FILTER_MED_3x3	(1<<23)
3045 #define  PF_FILTER_EDGE_ENHANCE	(2<<23)
3046 #define  PF_FILTER_EDGE_SOFTEN	(3<<23)
3047 #define _PFA_WIN_SZ		0x68074
3048 #define _PFB_WIN_SZ		0x68874
3049 #define _PFA_WIN_POS		0x68070
3050 #define _PFB_WIN_POS		0x68870
3051 #define _PFA_VSCALE		0x68084
3052 #define _PFB_VSCALE		0x68884
3053 #define _PFA_HSCALE		0x68090
3054 #define _PFB_HSCALE		0x68890
3055 
3056 #define PF_CTL(pipe)		_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3057 #define PF_WIN_SZ(pipe)		_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3058 #define PF_WIN_POS(pipe)	_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3059 #define PF_VSCALE(pipe)		_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3060 #define PF_HSCALE(pipe)		_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3061 
3062 /* legacy palette */
3063 #define _LGC_PALETTE_A           0x4a000
3064 #define _LGC_PALETTE_B           0x4a800
3065 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
3066 
3067 /* interrupts */
3068 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
3069 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
3070 #define DE_SPRITEA_FLIP_DONE    (1 << 28)
3071 #define DE_PLANEB_FLIP_DONE     (1 << 27)
3072 #define DE_PLANEA_FLIP_DONE     (1 << 26)
3073 #define DE_PCU_EVENT            (1 << 25)
3074 #define DE_GTT_FAULT            (1 << 24)
3075 #define DE_POISON               (1 << 23)
3076 #define DE_PERFORM_COUNTER      (1 << 22)
3077 #define DE_PCH_EVENT            (1 << 21)
3078 #define DE_AUX_CHANNEL_A        (1 << 20)
3079 #define DE_DP_A_HOTPLUG         (1 << 19)
3080 #define DE_GSE                  (1 << 18)
3081 #define DE_PIPEB_VBLANK         (1 << 15)
3082 #define DE_PIPEB_EVEN_FIELD     (1 << 14)
3083 #define DE_PIPEB_ODD_FIELD      (1 << 13)
3084 #define DE_PIPEB_LINE_COMPARE   (1 << 12)
3085 #define DE_PIPEB_VSYNC          (1 << 11)
3086 #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
3087 #define DE_PIPEA_VBLANK         (1 << 7)
3088 #define DE_PIPEA_EVEN_FIELD     (1 << 6)
3089 #define DE_PIPEA_ODD_FIELD      (1 << 5)
3090 #define DE_PIPEA_LINE_COMPARE   (1 << 4)
3091 #define DE_PIPEA_VSYNC          (1 << 3)
3092 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
3093 
3094 /* More Ivybridge lolz */
3095 #define DE_ERR_DEBUG_IVB		(1<<30)
3096 #define DE_GSE_IVB			(1<<29)
3097 #define DE_PCH_EVENT_IVB		(1<<28)
3098 #define DE_DP_A_HOTPLUG_IVB		(1<<27)
3099 #define DE_AUX_CHANNEL_A_IVB		(1<<26)
3100 #define DE_SPRITEB_FLIP_DONE_IVB	(1<<9)
3101 #define DE_SPRITEA_FLIP_DONE_IVB	(1<<4)
3102 #define DE_PLANEB_FLIP_DONE_IVB		(1<<8)
3103 #define DE_PLANEA_FLIP_DONE_IVB		(1<<3)
3104 #define DE_PIPEB_VBLANK_IVB		(1<<5)
3105 #define DE_PIPEA_VBLANK_IVB		(1<<0)
3106 
3107 #define DEISR   0x44000
3108 #define DEIMR   0x44004
3109 #define DEIIR   0x44008
3110 #define DEIER   0x4400c
3111 
3112 /* GT interrupt */
3113 #define GT_PIPE_NOTIFY		(1 << 4)
3114 #define GT_SYNC_STATUS          (1 << 2)
3115 #define GT_USER_INTERRUPT       (1 << 0)
3116 #define GT_BSD_USER_INTERRUPT   (1 << 5)
3117 #define GT_GEN6_BSD_USER_INTERRUPT	(1 << 12)
3118 #define GT_BLT_USER_INTERRUPT	(1 << 22)
3119 
3120 #define GTISR   0x44010
3121 #define GTIMR   0x44014
3122 #define GTIIR   0x44018
3123 #define GTIER   0x4401c
3124 
3125 #define ILK_DISPLAY_CHICKEN2	0x42004
3126 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
3127 #define  ILK_ELPIN_409_SELECT	(1 << 25)
3128 #define  ILK_DPARB_GATE	(1<<22)
3129 #define  ILK_VSDPFD_FULL	(1<<21)
3130 #define ILK_DISPLAY_CHICKEN_FUSES	0x42014
3131 #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1<<31)
3132 #define  ILK_INTERNAL_DISPLAY_DISABLE	(1<<30)
3133 #define  ILK_DISPLAY_DEBUG_DISABLE	(1<<29)
3134 #define  ILK_HDCP_DISABLE		(1<<25)
3135 #define  ILK_eDP_A_DISABLE		(1<<24)
3136 #define  ILK_DESKTOP			(1<<23)
3137 #define ILK_DSPCLK_GATE		0x42020
3138 #define  IVB_VRHUNIT_CLK_GATE	(1<<28)
3139 #define  ILK_DPARB_CLK_GATE	(1<<5)
3140 #define  ILK_DPFD_CLK_GATE	(1<<7)
3141 
3142 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
3143 #define   ILK_CLK_FBC		(1<<7)
3144 #define   ILK_DPFC_DIS1		(1<<8)
3145 #define   ILK_DPFC_DIS2		(1<<9)
3146 
3147 #define IVB_CHICKEN3	0x4200c
3148 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
3149 # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
3150 
3151 #define DISP_ARB_CTL	0x45000
3152 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
3153 #define  DISP_FBC_WM_DIS		(1<<15)
3154 
3155 /* GEN7 chicken */
3156 #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
3157 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
3158 
3159 #define GEN7_L3CNTLREG1				0xB01C
3160 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
3161 
3162 #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
3163 #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
3164 
3165 /* WaCatErrorRejectionIssue */
3166 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
3167 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
3168 
3169 /* PCH */
3170 
3171 /* south display engine interrupt */
3172 #define SDE_AUDIO_POWER_D	(1 << 27)
3173 #define SDE_AUDIO_POWER_C	(1 << 26)
3174 #define SDE_AUDIO_POWER_B	(1 << 25)
3175 #define SDE_AUDIO_POWER_SHIFT	(25)
3176 #define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
3177 #define SDE_GMBUS		(1 << 24)
3178 #define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
3179 #define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
3180 #define SDE_AUDIO_HDCP_MASK	(3 << 22)
3181 #define SDE_AUDIO_TRANSB	(1 << 21)
3182 #define SDE_AUDIO_TRANSA	(1 << 20)
3183 #define SDE_AUDIO_TRANS_MASK	(3 << 20)
3184 #define SDE_POISON		(1 << 19)
3185 /* 18 reserved */
3186 #define SDE_FDI_RXB		(1 << 17)
3187 #define SDE_FDI_RXA		(1 << 16)
3188 #define SDE_FDI_MASK		(3 << 16)
3189 #define SDE_AUXD		(1 << 15)
3190 #define SDE_AUXC		(1 << 14)
3191 #define SDE_AUXB		(1 << 13)
3192 #define SDE_AUX_MASK		(7 << 13)
3193 /* 12 reserved */
3194 #define SDE_CRT_HOTPLUG         (1 << 11)
3195 #define SDE_PORTD_HOTPLUG       (1 << 10)
3196 #define SDE_PORTC_HOTPLUG       (1 << 9)
3197 #define SDE_PORTB_HOTPLUG       (1 << 8)
3198 #define SDE_SDVOB_HOTPLUG       (1 << 6)
3199 #define SDE_HOTPLUG_MASK	(0xf << 8)
3200 #define SDE_TRANSB_CRC_DONE	(1 << 5)
3201 #define SDE_TRANSB_CRC_ERR	(1 << 4)
3202 #define SDE_TRANSB_FIFO_UNDER	(1 << 3)
3203 #define SDE_TRANSA_CRC_DONE	(1 << 2)
3204 #define SDE_TRANSA_CRC_ERR	(1 << 1)
3205 #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
3206 #define SDE_TRANS_MASK		(0x3f)
3207 /* CPT */
3208 #define SDE_CRT_HOTPLUG_CPT	(1 << 19)
3209 #define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
3210 #define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
3211 #define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
3212 #define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
3213 				 SDE_PORTD_HOTPLUG_CPT |	\
3214 				 SDE_PORTC_HOTPLUG_CPT |	\
3215 				 SDE_PORTB_HOTPLUG_CPT)
3216 
3217 #define SDEISR  0xc4000
3218 #define SDEIMR  0xc4004
3219 #define SDEIIR  0xc4008
3220 #define SDEIER  0xc400c
3221 
3222 /* digital port hotplug */
3223 #define PCH_PORT_HOTPLUG        0xc4030		/* SHOTPLUG_CTL */
3224 #define PORTD_HOTPLUG_ENABLE            (1 << 20)
3225 #define PORTD_PULSE_DURATION_2ms        (0)
3226 #define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
3227 #define PORTD_PULSE_DURATION_6ms        (2 << 18)
3228 #define PORTD_PULSE_DURATION_100ms      (3 << 18)
3229 #define PORTD_PULSE_DURATION_MASK	(3 << 18)
3230 #define PORTD_HOTPLUG_NO_DETECT         (0)
3231 #define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
3232 #define PORTD_HOTPLUG_LONG_DETECT       (1 << 17)
3233 #define PORTC_HOTPLUG_ENABLE            (1 << 12)
3234 #define PORTC_PULSE_DURATION_2ms        (0)
3235 #define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
3236 #define PORTC_PULSE_DURATION_6ms        (2 << 10)
3237 #define PORTC_PULSE_DURATION_100ms      (3 << 10)
3238 #define PORTC_PULSE_DURATION_MASK	(3 << 10)
3239 #define PORTC_HOTPLUG_NO_DETECT         (0)
3240 #define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
3241 #define PORTC_HOTPLUG_LONG_DETECT       (1 << 9)
3242 #define PORTB_HOTPLUG_ENABLE            (1 << 4)
3243 #define PORTB_PULSE_DURATION_2ms        (0)
3244 #define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
3245 #define PORTB_PULSE_DURATION_6ms        (2 << 2)
3246 #define PORTB_PULSE_DURATION_100ms      (3 << 2)
3247 #define PORTB_PULSE_DURATION_MASK	(3 << 2)
3248 #define PORTB_HOTPLUG_NO_DETECT         (0)
3249 #define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
3250 #define PORTB_HOTPLUG_LONG_DETECT       (1 << 1)
3251 
3252 #define PCH_GPIOA               0xc5010
3253 #define PCH_GPIOB               0xc5014
3254 #define PCH_GPIOC               0xc5018
3255 #define PCH_GPIOD               0xc501c
3256 #define PCH_GPIOE               0xc5020
3257 #define PCH_GPIOF               0xc5024
3258 
3259 #define PCH_GMBUS0		0xc5100
3260 #define PCH_GMBUS1		0xc5104
3261 #define PCH_GMBUS2		0xc5108
3262 #define PCH_GMBUS3		0xc510c
3263 #define PCH_GMBUS4		0xc5110
3264 #define PCH_GMBUS5		0xc5120
3265 
3266 #define _PCH_DPLL_A              0xc6014
3267 #define _PCH_DPLL_B              0xc6018
3268 #define PCH_DPLL(pipe) (pipe == 0 ?  _PCH_DPLL_A : _PCH_DPLL_B)
3269 
3270 #define _PCH_FPA0                0xc6040
3271 #define  FP_CB_TUNE		(0x3<<22)
3272 #define _PCH_FPA1                0xc6044
3273 #define _PCH_FPB0                0xc6048
3274 #define _PCH_FPB1                0xc604c
3275 #define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0)
3276 #define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1)
3277 
3278 #define PCH_DPLL_TEST           0xc606c
3279 
3280 #define PCH_DREF_CONTROL        0xC6200
3281 #define  DREF_CONTROL_MASK      0x7fc3
3282 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
3283 #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
3284 #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
3285 #define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
3286 #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
3287 #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
3288 #define  DREF_SSC_SOURCE_MASK			(3<<11)
3289 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
3290 #define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
3291 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
3292 #define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
3293 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
3294 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
3295 #define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
3296 #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
3297 #define  DREF_SSC4_CENTERSPREAD                 (1<<6)
3298 #define  DREF_SSC1_DISABLE                      (0<<1)
3299 #define  DREF_SSC1_ENABLE                       (1<<1)
3300 #define  DREF_SSC4_DISABLE                      (0)
3301 #define  DREF_SSC4_ENABLE                       (1)
3302 
3303 #define PCH_RAWCLK_FREQ         0xc6204
3304 #define  FDL_TP1_TIMER_SHIFT    12
3305 #define  FDL_TP1_TIMER_MASK     (3<<12)
3306 #define  FDL_TP2_TIMER_SHIFT    10
3307 #define  FDL_TP2_TIMER_MASK     (3<<10)
3308 #define  RAWCLK_FREQ_MASK       0x3ff
3309 
3310 #define PCH_DPLL_TMR_CFG        0xc6208
3311 
3312 #define PCH_SSC4_PARMS          0xc6210
3313 #define PCH_SSC4_AUX_PARMS      0xc6214
3314 
3315 #define PCH_DPLL_SEL		0xc7000
3316 #define  TRANSA_DPLL_ENABLE	(1<<3)
3317 #define	 TRANSA_DPLLB_SEL	(1<<0)
3318 #define	 TRANSA_DPLLA_SEL	0
3319 #define  TRANSB_DPLL_ENABLE	(1<<7)
3320 #define	 TRANSB_DPLLB_SEL	(1<<4)
3321 #define	 TRANSB_DPLLA_SEL	(0)
3322 #define  TRANSC_DPLL_ENABLE	(1<<11)
3323 #define	 TRANSC_DPLLB_SEL	(1<<8)
3324 #define	 TRANSC_DPLLA_SEL	(0)
3325 
3326 /* transcoder */
3327 
3328 #define _TRANS_HTOTAL_A          0xe0000
3329 #define  TRANS_HTOTAL_SHIFT     16
3330 #define  TRANS_HACTIVE_SHIFT    0
3331 #define _TRANS_HBLANK_A          0xe0004
3332 #define  TRANS_HBLANK_END_SHIFT 16
3333 #define  TRANS_HBLANK_START_SHIFT 0
3334 #define _TRANS_HSYNC_A           0xe0008
3335 #define  TRANS_HSYNC_END_SHIFT  16
3336 #define  TRANS_HSYNC_START_SHIFT 0
3337 #define _TRANS_VTOTAL_A          0xe000c
3338 #define  TRANS_VTOTAL_SHIFT     16
3339 #define  TRANS_VACTIVE_SHIFT    0
3340 #define _TRANS_VBLANK_A          0xe0010
3341 #define  TRANS_VBLANK_END_SHIFT 16
3342 #define  TRANS_VBLANK_START_SHIFT 0
3343 #define _TRANS_VSYNC_A           0xe0014
3344 #define  TRANS_VSYNC_END_SHIFT  16
3345 #define  TRANS_VSYNC_START_SHIFT 0
3346 #define _TRANS_VSYNCSHIFT_A	0xe0028
3347 
3348 #define _TRANSA_DATA_M1          0xe0030
3349 #define _TRANSA_DATA_N1          0xe0034
3350 #define _TRANSA_DATA_M2          0xe0038
3351 #define _TRANSA_DATA_N2          0xe003c
3352 #define _TRANSA_DP_LINK_M1       0xe0040
3353 #define _TRANSA_DP_LINK_N1       0xe0044
3354 #define _TRANSA_DP_LINK_M2       0xe0048
3355 #define _TRANSA_DP_LINK_N2       0xe004c
3356 
3357 /* Per-transcoder DIP controls */
3358 
3359 #define _VIDEO_DIP_CTL_A         0xe0200
3360 #define _VIDEO_DIP_DATA_A        0xe0208
3361 #define _VIDEO_DIP_GCP_A         0xe0210
3362 
3363 #define _VIDEO_DIP_CTL_B         0xe1200
3364 #define _VIDEO_DIP_DATA_B        0xe1208
3365 #define _VIDEO_DIP_GCP_B         0xe1210
3366 
3367 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3368 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3369 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3370 
3371 #define _TRANS_HTOTAL_B          0xe1000
3372 #define _TRANS_HBLANK_B          0xe1004
3373 #define _TRANS_HSYNC_B           0xe1008
3374 #define _TRANS_VTOTAL_B          0xe100c
3375 #define _TRANS_VBLANK_B          0xe1010
3376 #define _TRANS_VSYNC_B           0xe1014
3377 #define _TRANS_VSYNCSHIFT_B	 0xe1028
3378 
3379 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3380 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3381 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3382 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3383 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3384 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3385 #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
3386 				     _TRANS_VSYNCSHIFT_B)
3387 
3388 #define _TRANSB_DATA_M1          0xe1030
3389 #define _TRANSB_DATA_N1          0xe1034
3390 #define _TRANSB_DATA_M2          0xe1038
3391 #define _TRANSB_DATA_N2          0xe103c
3392 #define _TRANSB_DP_LINK_M1       0xe1040
3393 #define _TRANSB_DP_LINK_N1       0xe1044
3394 #define _TRANSB_DP_LINK_M2       0xe1048
3395 #define _TRANSB_DP_LINK_N2       0xe104c
3396 
3397 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3398 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3399 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3400 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3401 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3402 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3403 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3404 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3405 
3406 #define _TRANSACONF              0xf0008
3407 #define _TRANSBCONF              0xf1008
3408 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3409 #define  TRANS_DISABLE          (0<<31)
3410 #define  TRANS_ENABLE           (1<<31)
3411 #define  TRANS_STATE_MASK       (1<<30)
3412 #define  TRANS_STATE_DISABLE    (0<<30)
3413 #define  TRANS_STATE_ENABLE     (1<<30)
3414 #define  TRANS_FSYNC_DELAY_HB1  (0<<27)
3415 #define  TRANS_FSYNC_DELAY_HB2  (1<<27)
3416 #define  TRANS_FSYNC_DELAY_HB3  (2<<27)
3417 #define  TRANS_FSYNC_DELAY_HB4  (3<<27)
3418 #define  TRANS_DP_AUDIO_ONLY    (1<<26)
3419 #define  TRANS_DP_VIDEO_AUDIO   (0<<26)
3420 #define  TRANS_INTERLACE_MASK   (7<<21)
3421 #define  TRANS_PROGRESSIVE      (0<<21)
3422 #define  TRANS_INTERLACED       (3<<21)
3423 #define  TRANS_LEGACY_INTERLACED_ILK (2<<21)
3424 #define  TRANS_8BPC             (0<<5)
3425 #define  TRANS_10BPC            (1<<5)
3426 #define  TRANS_6BPC             (2<<5)
3427 #define  TRANS_12BPC            (3<<5)
3428 
3429 #define _TRANSA_CHICKEN2	 0xf0064
3430 #define _TRANSB_CHICKEN2	 0xf1064
3431 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3432 #define   TRANS_AUTOTRAIN_GEN_STALL_DIS	(1<<31)
3433 
3434 #define SOUTH_CHICKEN1		0xc2000
3435 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
3436 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
3437 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3438 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3439 #define SOUTH_CHICKEN2		0xc2004
3440 #define  DPLS_EDP_PPS_FIX_DIS	(1<<0)
3441 
3442 #define _FDI_RXA_CHICKEN         0xc200c
3443 #define _FDI_RXB_CHICKEN         0xc2010
3444 #define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)
3445 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1<<0)
3446 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3447 
3448 #define SOUTH_DSPCLK_GATE_D	0xc2020
3449 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3450 
3451 /* CPU: FDI_TX */
3452 #define _FDI_TXA_CTL             0x60100
3453 #define _FDI_TXB_CTL             0x61100
3454 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3455 #define  FDI_TX_DISABLE         (0<<31)
3456 #define  FDI_TX_ENABLE          (1<<31)
3457 #define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
3458 #define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
3459 #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
3460 #define  FDI_LINK_TRAIN_NONE            (3<<28)
3461 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0<<25)
3462 #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1<<25)
3463 #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2<<25)
3464 #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3<<25)
3465 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3466 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3467 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2<<22)
3468 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3<<22)
3469 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3470    SNB has different settings. */
3471 /* SNB A-stepping */
3472 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
3473 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
3474 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
3475 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
3476 /* SNB B-stepping */
3477 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0<<22)
3478 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a<<22)
3479 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39<<22)
3480 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38<<22)
3481 #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f<<22)
3482 #define  FDI_DP_PORT_WIDTH_X1           (0<<19)
3483 #define  FDI_DP_PORT_WIDTH_X2           (1<<19)
3484 #define  FDI_DP_PORT_WIDTH_X3           (2<<19)
3485 #define  FDI_DP_PORT_WIDTH_X4           (3<<19)
3486 #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
3487 /* Ironlake: hardwired to 1 */
3488 #define  FDI_TX_PLL_ENABLE              (1<<14)
3489 
3490 /* Ivybridge has different bits for lolz */
3491 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
3492 #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
3493 #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
3494 #define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
3495 
3496 /* both Tx and Rx */
3497 #define  FDI_COMPOSITE_SYNC		(1<<11)
3498 #define  FDI_LINK_TRAIN_AUTO		(1<<10)
3499 #define  FDI_SCRAMBLING_ENABLE          (0<<7)
3500 #define  FDI_SCRAMBLING_DISABLE         (1<<7)
3501 
3502 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3503 #define _FDI_RXA_CTL             0xf000c
3504 #define _FDI_RXB_CTL             0xf100c
3505 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3506 #define  FDI_RX_ENABLE          (1<<31)
3507 /* train, dp width same as FDI_TX */
3508 #define  FDI_FS_ERRC_ENABLE		(1<<27)
3509 #define  FDI_FE_ERRC_ENABLE		(1<<26)
3510 #define  FDI_DP_PORT_WIDTH_X8           (7<<19)
3511 #define  FDI_8BPC                       (0<<16)
3512 #define  FDI_10BPC                      (1<<16)
3513 #define  FDI_6BPC                       (2<<16)
3514 #define  FDI_12BPC                      (3<<16)
3515 #define  FDI_LINK_REVERSE_OVERWRITE     (1<<15)
3516 #define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
3517 #define  FDI_RX_PLL_ENABLE              (1<<13)
3518 #define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)
3519 #define  FDI_FE_ERR_CORRECT_ENABLE      (1<<10)
3520 #define  FDI_FS_ERR_REPORT_ENABLE       (1<<9)
3521 #define  FDI_FE_ERR_REPORT_ENABLE       (1<<8)
3522 #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1<<6)
3523 #define  FDI_PCDCLK	                (1<<4)
3524 /* CPT */
3525 #define  FDI_AUTO_TRAINING			(1<<10)
3526 #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0<<8)
3527 #define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1<<8)
3528 #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
3529 #define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
3530 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
3531 
3532 #define _FDI_RXA_MISC            0xf0010
3533 #define _FDI_RXB_MISC            0xf1010
3534 #define _FDI_RXA_TUSIZE1         0xf0030
3535 #define _FDI_RXA_TUSIZE2         0xf0038
3536 #define _FDI_RXB_TUSIZE1         0xf1030
3537 #define _FDI_RXB_TUSIZE2         0xf1038
3538 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3539 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3540 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3541 
3542 /* FDI_RX interrupt register format */
3543 #define FDI_RX_INTER_LANE_ALIGN         (1<<10)
3544 #define FDI_RX_SYMBOL_LOCK              (1<<9) /* train 2 */
3545 #define FDI_RX_BIT_LOCK                 (1<<8) /* train 1 */
3546 #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1<<7)
3547 #define FDI_RX_FS_CODE_ERR              (1<<6)
3548 #define FDI_RX_FE_CODE_ERR              (1<<5)
3549 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1<<4)
3550 #define FDI_RX_HDCP_LINK_FAIL           (1<<3)
3551 #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1<<2)
3552 #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
3553 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
3554 
3555 #define _FDI_RXA_IIR             0xf0014
3556 #define _FDI_RXA_IMR             0xf0018
3557 #define _FDI_RXB_IIR             0xf1014
3558 #define _FDI_RXB_IMR             0xf1018
3559 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3560 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3561 
3562 #define FDI_PLL_CTL_1           0xfe000
3563 #define FDI_PLL_CTL_2           0xfe004
3564 
3565 /* CRT */
3566 #define PCH_ADPA                0xe1100
3567 #define  ADPA_TRANS_SELECT_MASK (1<<30)
3568 #define  ADPA_TRANS_A_SELECT    0
3569 #define  ADPA_TRANS_B_SELECT    (1<<30)
3570 #define  ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
3571 #define  ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
3572 #define  ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
3573 #define  ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3574 #define  ADPA_CRT_HOTPLUG_MONITOR_MONO  (2<<24)
3575 #define  ADPA_CRT_HOTPLUG_ENABLE        (1<<23)
3576 #define  ADPA_CRT_HOTPLUG_PERIOD_64     (0<<22)
3577 #define  ADPA_CRT_HOTPLUG_PERIOD_128    (1<<22)
3578 #define  ADPA_CRT_HOTPLUG_WARMUP_5MS    (0<<21)
3579 #define  ADPA_CRT_HOTPLUG_WARMUP_10MS   (1<<21)
3580 #define  ADPA_CRT_HOTPLUG_SAMPLE_2S     (0<<20)
3581 #define  ADPA_CRT_HOTPLUG_SAMPLE_4S     (1<<20)
3582 #define  ADPA_CRT_HOTPLUG_VOLTAGE_40    (0<<18)
3583 #define  ADPA_CRT_HOTPLUG_VOLTAGE_50    (1<<18)
3584 #define  ADPA_CRT_HOTPLUG_VOLTAGE_60    (2<<18)
3585 #define  ADPA_CRT_HOTPLUG_VOLTAGE_70    (3<<18)
3586 #define  ADPA_CRT_HOTPLUG_VOLREF_325MV  (0<<17)
3587 #define  ADPA_CRT_HOTPLUG_VOLREF_475MV  (1<<17)
3588 #define  ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3589 
3590 /* or SDVOB */
3591 #define HDMIB   0xe1140
3592 #define  PORT_ENABLE    (1 << 31)
3593 #define  TRANSCODER(pipe)       ((pipe) << 30)
3594 #define  TRANSCODER_CPT(pipe)   ((pipe) << 29)
3595 #define  TRANSCODER_MASK        (1 << 30)
3596 #define  TRANSCODER_MASK_CPT    (3 << 29)
3597 #define  COLOR_FORMAT_8bpc      (0)
3598 #define  COLOR_FORMAT_12bpc     (3 << 26)
3599 #define  SDVOB_HOTPLUG_ENABLE   (1 << 23)
3600 #define  SDVO_ENCODING          (0)
3601 #define  TMDS_ENCODING          (2 << 10)
3602 #define  NULL_PACKET_VSYNC_ENABLE       (1 << 9)
3603 /* CPT */
3604 #define  HDMI_MODE_SELECT	(1 << 9)
3605 #define  DVI_MODE_SELECT	(0)
3606 #define  SDVOB_BORDER_ENABLE    (1 << 7)
3607 #define  AUDIO_ENABLE           (1 << 6)
3608 #define  VSYNC_ACTIVE_HIGH      (1 << 4)
3609 #define  HSYNC_ACTIVE_HIGH      (1 << 3)
3610 #define  PORT_DETECTED          (1 << 2)
3611 
3612 /* PCH SDVOB multiplex with HDMIB */
3613 #define PCH_SDVOB	HDMIB
3614 
3615 #define HDMIC   0xe1150
3616 #define HDMID   0xe1160
3617 
3618 #define PCH_LVDS	0xe1180
3619 #define  LVDS_DETECTED	(1 << 1)
3620 
3621 #define BLC_PWM_CPU_CTL2	0x48250
3622 #define  PWM_ENABLE		(1 << 31)
3623 #define  PWM_PIPE_A		(0 << 29)
3624 #define  PWM_PIPE_B		(1 << 29)
3625 #define BLC_PWM_CPU_CTL		0x48254
3626 
3627 #define BLC_PWM_PCH_CTL1	0xc8250
3628 #define  PWM_PCH_ENABLE		(1 << 31)
3629 #define  PWM_POLARITY_ACTIVE_LOW	(1 << 29)
3630 #define  PWM_POLARITY_ACTIVE_HIGH	(0 << 29)
3631 #define  PWM_POLARITY_ACTIVE_LOW2	(1 << 28)
3632 #define  PWM_POLARITY_ACTIVE_HIGH2	(0 << 28)
3633 
3634 #define BLC_PWM_PCH_CTL2	0xc8254
3635 
3636 #define PCH_PP_STATUS		0xc7200
3637 #define PCH_PP_CONTROL		0xc7204
3638 #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
3639 #define  PANEL_UNLOCK_MASK	(0xffff << 16)
3640 #define  EDP_FORCE_VDD		(1 << 3)
3641 #define  EDP_BLC_ENABLE		(1 << 2)
3642 #define  PANEL_POWER_RESET	(1 << 1)
3643 #define  PANEL_POWER_OFF	(0 << 0)
3644 #define  PANEL_POWER_ON		(1 << 0)
3645 #define PCH_PP_ON_DELAYS	0xc7208
3646 #define  PANEL_PORT_SELECT_MASK	(3 << 30)
3647 #define  PANEL_PORT_SELECT_LVDS	(0 << 30)
3648 #define  PANEL_PORT_SELECT_DPA	(1 << 30)
3649 #define  EDP_PANEL		(1 << 30)
3650 #define  PANEL_PORT_SELECT_DPC	(2 << 30)
3651 #define  PANEL_PORT_SELECT_DPD	(3 << 30)
3652 #define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
3653 #define  PANEL_POWER_UP_DELAY_SHIFT	16
3654 #define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
3655 #define  PANEL_LIGHT_ON_DELAY_SHIFT	0
3656 
3657 #define PCH_PP_OFF_DELAYS	0xc720c
3658 #define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
3659 #define  PANEL_POWER_DOWN_DELAY_SHIFT	16
3660 #define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
3661 #define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
3662 
3663 #define PCH_PP_DIVISOR		0xc7210
3664 #define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
3665 #define  PP_REFERENCE_DIVIDER_SHIFT	8
3666 #define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
3667 #define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
3668 
3669 #define PCH_DP_B		0xe4100
3670 #define PCH_DPB_AUX_CH_CTL	0xe4110
3671 #define PCH_DPB_AUX_CH_DATA1	0xe4114
3672 #define PCH_DPB_AUX_CH_DATA2	0xe4118
3673 #define PCH_DPB_AUX_CH_DATA3	0xe411c
3674 #define PCH_DPB_AUX_CH_DATA4	0xe4120
3675 #define PCH_DPB_AUX_CH_DATA5	0xe4124
3676 
3677 #define PCH_DP_C		0xe4200
3678 #define PCH_DPC_AUX_CH_CTL	0xe4210
3679 #define PCH_DPC_AUX_CH_DATA1	0xe4214
3680 #define PCH_DPC_AUX_CH_DATA2	0xe4218
3681 #define PCH_DPC_AUX_CH_DATA3	0xe421c
3682 #define PCH_DPC_AUX_CH_DATA4	0xe4220
3683 #define PCH_DPC_AUX_CH_DATA5	0xe4224
3684 
3685 #define PCH_DP_D		0xe4300
3686 #define PCH_DPD_AUX_CH_CTL	0xe4310
3687 #define PCH_DPD_AUX_CH_DATA1	0xe4314
3688 #define PCH_DPD_AUX_CH_DATA2	0xe4318
3689 #define PCH_DPD_AUX_CH_DATA3	0xe431c
3690 #define PCH_DPD_AUX_CH_DATA4	0xe4320
3691 #define PCH_DPD_AUX_CH_DATA5	0xe4324
3692 
3693 /* CPT */
3694 #define  PORT_TRANS_A_SEL_CPT	0
3695 #define  PORT_TRANS_B_SEL_CPT	(1<<29)
3696 #define  PORT_TRANS_C_SEL_CPT	(2<<29)
3697 #define  PORT_TRANS_SEL_MASK	(3<<29)
3698 #define  PORT_TRANS_SEL_CPT(pipe)	((pipe) << 29)
3699 
3700 #define TRANS_DP_CTL_A		0xe0300
3701 #define TRANS_DP_CTL_B		0xe1300
3702 #define TRANS_DP_CTL_C		0xe2300
3703 #define TRANS_DP_CTL(pipe)	(TRANS_DP_CTL_A + (pipe) * 0x01000)
3704 #define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
3705 #define  TRANS_DP_PORT_SEL_B	(0<<29)
3706 #define  TRANS_DP_PORT_SEL_C	(1<<29)
3707 #define  TRANS_DP_PORT_SEL_D	(2<<29)
3708 #define  TRANS_DP_PORT_SEL_NONE	(3<<29)
3709 #define  TRANS_DP_PORT_SEL_MASK	(3<<29)
3710 #define  TRANS_DP_AUDIO_ONLY	(1<<26)
3711 #define  TRANS_DP_ENH_FRAMING	(1<<18)
3712 #define  TRANS_DP_8BPC		(0<<9)
3713 #define  TRANS_DP_10BPC		(1<<9)
3714 #define  TRANS_DP_6BPC		(2<<9)
3715 #define  TRANS_DP_12BPC		(3<<9)
3716 #define  TRANS_DP_BPC_MASK	(3<<9)
3717 #define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1<<4)
3718 #define  TRANS_DP_VSYNC_ACTIVE_LOW	0
3719 #define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1<<3)
3720 #define  TRANS_DP_HSYNC_ACTIVE_LOW	0
3721 #define  TRANS_DP_SYNC_MASK	(3<<3)
3722 
3723 /* SNB eDP training params */
3724 /* SNB A-stepping */
3725 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
3726 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
3727 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
3728 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
3729 /* SNB B-stepping */
3730 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0<<22)
3731 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1<<22)
3732 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a<<22)
3733 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39<<22)
3734 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38<<22)
3735 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f<<22)
3736 
3737 /* IVB */
3738 #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 <<22)
3739 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a <<22)
3740 #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f <<22)
3741 #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 <<22)
3742 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 <<22)
3743 #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 <<22)
3744 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e <<22)
3745 
3746 /* legacy values */
3747 #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 <<22)
3748 #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 <<22)
3749 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 <<22)
3750 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 <<22)
3751 #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 <<22)
3752 
3753 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
3754 
3755 #define  FORCEWAKE				0xA18C
3756 #define  FORCEWAKE_ACK				0x130090
3757 #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
3758 #define  FORCEWAKE_MT_ACK			0x130040
3759 #define  ECOBUS					0xa180
3760 #define    FORCEWAKE_MT_ENABLE			(1<<5)
3761 
3762 #define  GTFIFODBG				0x120000
3763 #define    GT_FIFO_CPU_ERROR_MASK		7
3764 #define    GT_FIFO_OVFERR			(1<<2)
3765 #define    GT_FIFO_IAWRERR			(1<<1)
3766 #define    GT_FIFO_IARDERR			(1<<0)
3767 
3768 #define  GT_FIFO_FREE_ENTRIES			0x120008
3769 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
3770 
3771 #define GEN6_UCGCTL1				0x9400
3772 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
3773 
3774 #define GEN6_UCGCTL2				0x9404
3775 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
3776 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
3777 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
3778 
3779 #define GEN6_RPNSWREQ				0xA008
3780 #define   GEN6_TURBO_DISABLE			(1<<31)
3781 #define   GEN6_FREQUENCY(x)			((x)<<25)
3782 #define   GEN6_OFFSET(x)			((x)<<19)
3783 #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
3784 #define GEN6_RC_VIDEO_FREQ			0xA00C
3785 #define GEN6_RC_CONTROL				0xA090
3786 #define   GEN6_RC_CTL_RC6pp_ENABLE		(1<<16)
3787 #define   GEN6_RC_CTL_RC6p_ENABLE		(1<<17)
3788 #define   GEN6_RC_CTL_RC6_ENABLE		(1<<18)
3789 #define   GEN6_RC_CTL_RC1e_ENABLE		(1<<20)
3790 #define   GEN6_RC_CTL_RC7_ENABLE		(1<<22)
3791 #define   GEN6_RC_CTL_EI_MODE(x)		((x)<<27)
3792 #define   GEN6_RC_CTL_HW_ENABLE			(1<<31)
3793 #define GEN6_RP_DOWN_TIMEOUT			0xA010
3794 #define GEN6_RP_INTERRUPT_LIMITS		0xA014
3795 #define GEN6_RPSTAT1				0xA01C
3796 #define   GEN6_CAGF_SHIFT			8
3797 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
3798 #define GEN6_RP_CONTROL				0xA024
3799 #define   GEN6_RP_MEDIA_TURBO			(1<<11)
3800 #define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
3801 #define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3<<9)
3802 #define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2<<9)
3803 #define   GEN6_RP_MEDIA_HW_MODE			(1<<9)
3804 #define   GEN6_RP_MEDIA_SW_MODE			(0<<9)
3805 #define   GEN6_RP_MEDIA_IS_GFX			(1<<8)
3806 #define   GEN6_RP_ENABLE			(1<<7)
3807 #define   GEN6_RP_UP_IDLE_MIN			(0x1<<3)
3808 #define   GEN6_RP_UP_BUSY_AVG			(0x2<<3)
3809 #define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
3810 #define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
3811 #define GEN6_RP_UP_THRESHOLD			0xA02C
3812 #define GEN6_RP_DOWN_THRESHOLD			0xA030
3813 #define GEN6_RP_CUR_UP_EI			0xA050
3814 #define   GEN6_CURICONT_MASK			0xffffff
3815 #define GEN6_RP_CUR_UP				0xA054
3816 #define   GEN6_CURBSYTAVG_MASK			0xffffff
3817 #define GEN6_RP_PREV_UP				0xA058
3818 #define GEN6_RP_CUR_DOWN_EI			0xA05C
3819 #define   GEN6_CURIAVG_MASK			0xffffff
3820 #define GEN6_RP_CUR_DOWN			0xA060
3821 #define GEN6_RP_PREV_DOWN			0xA064
3822 #define GEN6_RP_UP_EI				0xA068
3823 #define GEN6_RP_DOWN_EI				0xA06C
3824 #define GEN6_RP_IDLE_HYSTERSIS			0xA070
3825 #define GEN6_RC_STATE				0xA094
3826 #define GEN6_RC1_WAKE_RATE_LIMIT		0xA098
3827 #define GEN6_RC6_WAKE_RATE_LIMIT		0xA09C
3828 #define GEN6_RC6pp_WAKE_RATE_LIMIT		0xA0A0
3829 #define GEN6_RC_EVALUATION_INTERVAL		0xA0A8
3830 #define GEN6_RC_IDLE_HYSTERSIS			0xA0AC
3831 #define GEN6_RC_SLEEP				0xA0B0
3832 #define GEN6_RC1e_THRESHOLD			0xA0B4
3833 #define GEN6_RC6_THRESHOLD			0xA0B8
3834 #define GEN6_RC6p_THRESHOLD			0xA0BC
3835 #define GEN6_RC6pp_THRESHOLD			0xA0C0
3836 #define GEN6_PMINTRMSK				0xA168
3837 
3838 #define GEN6_PMISR				0x44020
3839 #define GEN6_PMIMR				0x44024 /* rps_lock */
3840 #define GEN6_PMIIR				0x44028
3841 #define GEN6_PMIER				0x4402C
3842 #define  GEN6_PM_MBOX_EVENT			(1<<25)
3843 #define  GEN6_PM_THERMAL_EVENT			(1<<24)
3844 #define  GEN6_PM_RP_DOWN_TIMEOUT		(1<<6)
3845 #define  GEN6_PM_RP_UP_THRESHOLD		(1<<5)
3846 #define  GEN6_PM_RP_DOWN_THRESHOLD		(1<<4)
3847 #define  GEN6_PM_RP_UP_EI_EXPIRED		(1<<2)
3848 #define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1<<1)
3849 #define  GEN6_PM_DEFERRED_EVENTS		(GEN6_PM_RP_UP_THRESHOLD | \
3850 						 GEN6_PM_RP_DOWN_THRESHOLD | \
3851 						 GEN6_PM_RP_DOWN_TIMEOUT)
3852 
3853 #define GEN6_PCODE_MAILBOX			0x138124
3854 #define   GEN6_PCODE_READY			(1<<31)
3855 #define   GEN6_READ_OC_PARAMS			0xc
3856 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
3857 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
3858 #define GEN6_PCODE_DATA				0x138128
3859 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
3860 
3861 #define GEN6_GT_CORE_STATUS		0x138060
3862 #define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
3863 #define   GEN6_RCn_MASK			7
3864 #define   GEN6_RC0			0
3865 #define   GEN6_RC3			2
3866 #define   GEN6_RC6			3
3867 #define   GEN6_RC7			4
3868 
3869 #define G4X_AUD_VID_DID			0x62020
3870 #define INTEL_AUDIO_DEVCL		0x808629FB
3871 #define INTEL_AUDIO_DEVBLC		0x80862801
3872 #define INTEL_AUDIO_DEVCTG		0x80862802
3873 
3874 #define G4X_AUD_CNTL_ST			0x620B4
3875 #define G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
3876 #define G4X_ELDV_DEVCTG			(1 << 14)
3877 #define G4X_ELD_ADDR			(0xf << 5)
3878 #define G4X_ELD_ACK			(1 << 4)
3879 #define G4X_HDMIW_HDMIEDID		0x6210C
3880 
3881 #define IBX_HDMIW_HDMIEDID_A		0xE2050
3882 #define IBX_AUD_CNTL_ST_A		0xE20B4
3883 #define IBX_ELD_BUFFER_SIZE		(0x1f << 10)
3884 #define IBX_ELD_ADDRESS			(0x1f << 5)
3885 #define IBX_ELD_ACK			(1 << 4)
3886 #define IBX_AUD_CNTL_ST2		0xE20C0
3887 #define IBX_ELD_VALIDB			(1 << 0)
3888 #define IBX_CP_READYB			(1 << 1)
3889 
3890 #define CPT_HDMIW_HDMIEDID_A		0xE5050
3891 #define CPT_AUD_CNTL_ST_A		0xE50B4
3892 #define CPT_AUD_CNTRL_ST2		0xE50C0
3893 
3894 /* These are the 4 32-bit write offset registers for each stream
3895  * output buffer.  It determines the offset from the
3896  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
3897  */
3898 #define GEN7_SO_WRITE_OFFSET(n)		(0x5280 + (n) * 4)
3899 
3900 #define IBX_AUD_CONFIG_A			0xe2000
3901 #define CPT_AUD_CONFIG_A			0xe5000
3902 #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
3903 #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
3904 #define   AUD_CONFIG_UPPER_N_SHIFT		20
3905 #define   AUD_CONFIG_UPPER_N_VALUE		(0xff << 20)
3906 #define   AUD_CONFIG_LOWER_N_SHIFT		4
3907 #define   AUD_CONFIG_LOWER_N_VALUE		(0xfff << 4)
3908 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
3909 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI		(0xf << 16)
3910 #define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
3911 
3912 #endif /* _I915_REG_H_ */
3913