1 #ifndef __ASM_SH_IRQ_H
2 #define __ASM_SH_IRQ_H
3
4 /*
5 *
6 * linux/include/asm-sh/irq.h
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 *
11 */
12
13 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
14 #include <asm/irq-sh7300.h>
15 #else
16 #include <linux/config.h>
17 #include <asm/machvec.h>
18 #include <asm/ptrace.h> /* for pt_regs */
19
20 #if defined(__sh3__)
21 #define INTC_IPRA 0xfffffee2UL
22 #define INTC_IPRB 0xfffffee4UL
23 #elif defined(__SH4__)
24 #define INTC_IPRA 0xffd00004UL
25 #define INTC_IPRB 0xffd00008UL
26 #define INTC_IPRC 0xffd0000cUL
27 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
28 # define INTC_IPRD 0xffd00010UL
29 #endif
30 #endif
31
32 #define TIMER_IRQ 16
33 #define TIMER_IPR_ADDR INTC_IPRA
34 #define TIMER_IPR_POS 3
35 #define TIMER_PRIORITY 2
36
37 #define RTC_IRQ 22
38 #define RTC_IPR_ADDR INTC_IPRA
39 #define RTC_IPR_POS 0
40 #define RTC_PRIORITY TIMER_PRIORITY
41
42 #if defined(__sh3__)
43 #define DMTE0_IRQ 48
44 #define DMTE1_IRQ 49
45 #define DMTE2_IRQ 50
46 #define DMTE3_IRQ 51
47 #define DMA_IPR_ADDR INTC_IPRE
48 #define DMA_IPR_POS 3
49 #define DMA_PRIORITY 7
50 #elif defined(__SH4__)
51 #define DMTE0_IRQ 34
52 #define DMTE1_IRQ 35
53 #define DMTE2_IRQ 36
54 #define DMTE3_IRQ 37
55 #define DMAE_IRQ 38
56 #define DMA_IPR_ADDR INTC_IPRC
57 #define DMA_IPR_POS 2
58 #define DMA_PRIORITY 7
59 #endif
60
61 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
62 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
63 defined (CONFIG_CPU_SUBTYPE_SH7751)
64 #define SCI_ERI_IRQ 23
65 #define SCI_RXI_IRQ 24
66 #define SCI_TXI_IRQ 25
67 #define SCI_IPR_ADDR INTC_IPRB
68 #define SCI_IPR_POS 1
69 #define SCI_PRIORITY 3
70 #endif
71
72 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
73 #define SCIF_ERI_IRQ 56
74 #define SCIF_RXI_IRQ 57
75 #define SCIF_BRI_IRQ 58
76 #define SCIF_TXI_IRQ 59
77 #define SCIF_IPR_ADDR INTC_IPRE
78 #define SCIF_IPR_POS 1
79 #define SCIF_PRIORITY 3
80
81 #define IRDA_ERI_IRQ 52
82 #define IRDA_RXI_IRQ 53
83 #define IRDA_BRI_IRQ 54
84 #define IRDA_TXI_IRQ 55
85 #define IRDA_IPR_ADDR INTC_IPRE
86 #define IRDA_IPR_POS 2
87 #define IRDA_PRIORITY 3
88 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
89 defined(CONFIG_CPU_SUBTYPE_ST40)
90 #define SCIF_ERI_IRQ 40
91 #define SCIF_RXI_IRQ 41
92 #define SCIF_BRI_IRQ 42
93 #define SCIF_TXI_IRQ 43
94 #define SCIF_IPR_ADDR INTC_IPRC
95 #define SCIF_IPR_POS 1
96 #define SCIF_PRIORITY 3
97 #if defined(CONFIG_CPU_SUBTYPE_ST40)
98 #define SCIF1_ERI_IRQ 23
99 #define SCIF1_RXI_IRQ 24
100 #define SCIF1_BRI_IRQ 25
101 #define SCIF1_TXI_IRQ 26
102 #define SCIF1_IPR_ADDR INTC_IPRB
103 #define SCIF1_IPR_POS 1
104 #define SCIF1_PRIORITY 3
105 #endif
106 #endif
107
108 /* NR_IRQS is made from three components:
109 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
110 * 2. PINT_NR_IRQS - number of PINT interrupts
111 * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
112 */
113
114 /* 1. ONCHIP_NR_IRQS */
115 #ifdef CONFIG_SH_GENERIC
116 # define ONCHIP_NR_IRQS 144
117 #else
118 # if defined(CONFIG_CPU_SUBTYPE_SH7707)
119 # define ONCHIP_NR_IRQS 64
120 # define PINT_NR_IRQS 16
121 # elif defined(CONFIG_CPU_SUBTYPE_SH7708)
122 # define ONCHIP_NR_IRQS 32
123 # elif defined(CONFIG_CPU_SUBTYPE_SH7709)
124 # define ONCHIP_NR_IRQS 64 // Actually 61
125 # define PINT_NR_IRQS 16
126 # elif defined(CONFIG_CPU_SUBTYPE_SH7750)
127 # define ONCHIP_NR_IRQS 48 // Actually 44
128 # elif defined(CONFIG_CPU_SUBTYPE_SH7751)
129 # define ONCHIP_NR_IRQS 72
130 # elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
131 # define ONCHIP_NR_IRQS 72
132 # elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
133 # define ONCHIP_NR_IRQS 144
134 # elif defined(CONFIG_CPU_SUBTYPE_ST40GX1)
135 # define ONCHIP_NR_IRQS 176
136 # else
137 # error Unknown chip
138 # endif
139 #endif
140
141 /* 2. PINT_NR_IRQS */
142 #ifdef CONFIG_SH_GENERIC
143 # define PINT_NR_IRQS 16
144 #else
145 # ifndef PINT_NR_IRQS
146 # define PINT_NR_IRQS 0
147 # endif
148 #endif
149
150 #if PINT_NR_IRQS > 0
151 # define PINT_IRQ_BASE ONCHIP_NR_IRQS
152 #endif
153
154 /* 3. OFFCHIP_NR_IRQS */
155 #ifdef CONFIG_SH_GENERIC
156 # define OFFCHIP_NR_IRQS 16
157 #else
158 # if defined(CONFIG_HD64461)
159 # define OFFCHIP_NR_IRQS 16
160 # elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
161 # define OFFCHIP_NR_IRQS 48
162 # elif defined(CONFIG_HD64465)
163 # define OFFCHIP_NR_IRQS 16
164 # elif defined (CONFIG_SH_EC3104)
165 # define OFFCHIP_NR_IRQS 16
166 # elif defined (CONFIG_SH_DREAMCAST)
167 # define OFFCHIP_NR_IRQS 96
168 # else
169 # define OFFCHIP_NR_IRQS 0
170 # endif
171 #endif
172
173 #if OFFCHIP_NR_IRQS > 0
174 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
175 #endif
176
177 /* NR_IRQS. 1+2+3 */
178 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
179
180 /* In a generic kernel, NR_IRQS is an upper bound, and we should use
181 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
182 */
183 #ifdef CONFIG_SH_GENERIC
184 # define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
185 #else
186 # define ACTUAL_NR_IRQS NR_IRQS
187 #endif
188
189
190 extern void disable_irq(unsigned int);
191 extern void disable_irq_nosync(unsigned int);
192 extern void enable_irq(unsigned int);
193
194 /*
195 * Simple Mask Register Support
196 */
197 extern void make_maskreg_irq(unsigned int irq);
198 extern unsigned short *irq_mask_register;
199
200 /*
201 * Function for "on chip support modules".
202 */
203 extern void make_ipr_irq(unsigned int irq, unsigned int addr,
204 int pos, int priority);
205 extern void make_imask_irq(unsigned int irq);
206
207 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
208 #define INTC_IRR0 0xa4000004UL
209 #define INTC_IRR1 0xa4000006UL
210 #define INTC_IRR2 0xa4000008UL
211
212 #define INTC_ICR0 0xfffffee0UL
213 #define INTC_ICR1 0xa4000010UL
214 #define INTC_ICR2 0xa4000012UL
215 #define INTC_INTER 0xa4000014UL
216
217 #define INTC_IPRC 0xa4000016UL
218 #define INTC_IPRD 0xa4000018UL
219 #define INTC_IPRE 0xa400001aUL
220 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
221 #define INTC_IPRF 0xa400001cUL
222 #endif
223
224 #define PORT_PACR 0xa4000100UL
225 #define PORT_PBCR 0xa4000102UL
226 #define PORT_PCCR 0xa4000104UL
227 #define PORT_PFCR 0xa400010aUL
228 #define PORT_PADR 0xa4000120UL
229 #define PORT_PBDR 0xa4000122UL
230 #define PORT_PCDR 0xa4000124UL
231 #define PORT_PFDR 0xa400012aUL
232
233 #define IRQ0_IRQ 32
234 #define IRQ1_IRQ 33
235 #define IRQ2_IRQ 34
236 #define IRQ3_IRQ 35
237 #define IRQ4_IRQ 36
238 #define IRQ5_IRQ 37
239
240 #define IRQ0_IPR_ADDR INTC_IPRC
241 #define IRQ1_IPR_ADDR INTC_IPRC
242 #define IRQ2_IPR_ADDR INTC_IPRC
243 #define IRQ3_IPR_ADDR INTC_IPRC
244 #define IRQ4_IPR_ADDR INTC_IPRD
245 #define IRQ5_IPR_ADDR INTC_IPRD
246
247 #define IRQ0_IPR_POS 0
248 #define IRQ1_IPR_POS 1
249 #define IRQ2_IPR_POS 2
250 #define IRQ3_IPR_POS 3
251 #define IRQ4_IPR_POS 0
252 #define IRQ5_IPR_POS 1
253
254 #define IRQ0_PRIORITY 1
255 #define IRQ1_PRIORITY 1
256 #define IRQ2_PRIORITY 1
257 #define IRQ3_PRIORITY 1
258 #define IRQ4_PRIORITY 1
259 #define IRQ5_PRIORITY 1
260
261 #define PINT0_IRQ 40
262 #define PINT8_IRQ 41
263
264 #define PINT0_IPR_ADDR INTC_IPRD
265 #define PINT8_IPR_ADDR INTC_IPRD
266
267 #define PINT0_IPR_POS 3
268 #define PINT8_IPR_POS 2
269 #define PINT0_PRIORITY 2
270 #define PINT8_PRIORITY 2
271
272 extern int ipr_irq_demux(int irq);
273 #define __irq_demux(irq) ipr_irq_demux(irq)
274
275 #else
276 #define __irq_demux(irq) irq
277 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
278
279 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
280 defined(CONFIG_CPU_SUBTYPE_ST40) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
281 #define INTC_ICR 0xffd00000
282 #define INTC_ICR_NMIL (1<<15)
283 #define INTC_ICR_MAI (1<<14)
284 #define INTC_ICR_NMIB (1<<9)
285 #define INTC_ICR_NMIE (1<<8)
286 #define INTC_ICR_IRLM (1<<7)
287 #endif
288
289 #ifdef CONFIG_CPU_SUBTYPE_ST40
290 #define INTC2_FIRST_IRQ 64
291 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
292 #define NR_INTC2_IRQS 80
293 #elif defined(CONFIG_CPU_SUBTYPE_ST40GX1)
294 #define NR_INTC2_IRQS 112
295 #else
296 #error Unknown CPU
297 #endif
298
299 #define INTC2_BASE 0xfe080000
300 #define INTC2_INTC2MODE (INTC2_BASE+0x80)
301
302 #define INTC2_INTPRI_OFFSET 0x00
303 #define INTC2_INTREQ_OFFSET 0x20
304 #define INTC2_INTMSK_OFFSET 0x40
305 #define INTC2_INTMSKCLR_OFFSET 0x60
306
307 void make_intc2_irq(unsigned int irq,
308 unsigned int ipr_offset, unsigned int ipr_shift,
309 unsigned int msk_offset, unsigned int msk_shift,
310 unsigned int priority);
311 void init_IRQ_intc2(void);
312 void intc2_add_clear_irq(int irq, int (*fn)(int));
313 #endif
314
315 #ifdef CONFIG_SH_GENERIC
316
irq_demux(int irq)317 static __inline__ int irq_demux(int irq)
318 {
319 if (sh_mv.mv_irq_demux) {
320 irq = sh_mv.mv_irq_demux(irq);
321 }
322 return __irq_demux(irq);
323 }
324
325 #elif defined(CONFIG_SH_BIGSUR)
326
327 extern int bigsur_irq_demux(int irq);
328 #define irq_demux(irq) bigsur_irq_demux(irq)
329
330 #elif defined(CONFIG_HD64461)
331
332 extern int hd64461_irq_demux(int irq);
333 #define irq_demux(irq) hd64461_irq_demux(irq)
334
335 #elif defined(CONFIG_HD64465)
336
337 extern int hd64465_irq_demux(int irq);
338 #define irq_demux(irq) hd64465_irq_demux(irq)
339
340 #elif defined(CONFIG_SH_EC3104)
341
342 extern int ec3104_irq_demux(int irq);
343 #define irq_demux ec3104_irq_demux
344
345 #elif defined(CONFIG_SH_CAT68701)
346
347 extern int cat68701_irq_demux(int irq);
348 #define irq_demux cat68701_irq_demux
349
350 #elif defined(CONFIG_SH_DREAMCAST)
351
352 extern int systemasic_irq_demux(int irq);
353 #define irq_demux systemasic_irq_demux
354
355 #else
356
357 #define irq_demux(irq) __irq_demux(irq)
358
359 #endif
360
361
362 #endif /* !CONFIG_CPU_SUBTYPE_SH7300 */
363
364 #endif /* __ASM_SH_IRQ_H */
365