1 /* $Id$ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (c) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. 8 */ 9 #ifndef _ASM_SN_PCI_BRIDGE_H 10 #define _ASM_SN_PCI_BRIDGE_H 11 12 13 /* 14 * bridge.h - header file for bridge chip and bridge portion of xbridge chip 15 * 16 * Also including offsets for unique PIC registers. 17 * The PIC asic is a follow-on to Xbridge and most of its registers are 18 * identical to those of Xbridge. PIC is different than Xbridge in that 19 * it will accept 64 bit register access and that, in some cases, data 20 * is kept in bits 63:32. PIC registers that are identical to Xbridge 21 * may be accessed identically to the Xbridge registers, allowing for lots 22 * of code reuse. Here are the access rules as described in the PIC 23 * manual: 24 * 25 * o Read a word on a DW boundary returns D31:00 of reg. 26 * o Read a DW on a DW boundary returns D63:00 of reg. 27 * o Write a word on a DW boundary loads D31:00 of reg. 28 * o Write a DW on a DW boundary loads D63:00 of reg. 29 * o No support for word boundary access that is not double word 30 * aligned. 31 * 32 * So we can reuse a lot of bridge_s for PIC. In bridge_s are included 33 * #define tags and unions for 64 bit access to PIC registers. 34 * For a detailed PIC register layout see pic.h. 35 */ 36 37 #ifdef __KERNEL__ 38 #include <linux/config.h> 39 #include <asm/sn/xtalk/xwidget.h> 40 #include <asm/sn/pci/pic.h> 41 #else 42 #include <linux/config.h> 43 #include <xtalk/xwidget.h> 44 #include <pci/pic.h> 45 #endif 46 47 /* I/O page size */ 48 49 #if PAGE_SIZE == 4096 50 #define IOPFNSHIFT 12 /* 4K per mapped page */ 51 #else 52 #define IOPFNSHIFT 14 /* 16K per mapped page */ 53 #endif /* _PAGESZ */ 54 55 #define IOPGSIZE (1 << IOPFNSHIFT) 56 #define IOPG(x) ((x) >> IOPFNSHIFT) 57 #define IOPGOFF(x) ((x) & (IOPGSIZE-1)) 58 59 /* Bridge RAM sizes */ 60 61 #define BRIDGE_INTERNAL_ATES 128 62 #define XBRIDGE_INTERNAL_ATES 1024 63 64 #define BRIDGE_ATE_RAM_SIZE (BRIDGE_INTERNAL_ATES<<3) /* 1kB ATE */ 65 #define XBRIDGE_ATE_RAM_SIZE (XBRIDGE_INTERNAL_ATES<<3) /* 8kB ATE */ 66 67 #define PIC_WR_REQ_BUFSIZE 256 68 69 #define BRIDGE_CONFIG_BASE 0x20000 /* start of bridge's */ 70 /* map to each device's */ 71 /* config space */ 72 #define BRIDGE_CONFIG1_BASE 0x28000 /* type 1 device config space */ 73 #define BRIDGE_CONFIG_END 0x30000 74 #define BRIDGE_CONFIG_SLOT_SIZE 0x1000 /* each map == 4k */ 75 76 #define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */ 77 #define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */ 78 #define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */ 79 #define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */ 80 81 /* ======================================================================== 82 * Bridge address map 83 */ 84 85 #ifndef __ASSEMBLY__ 86 87 #ifdef __cplusplus 88 extern "C" { 89 #endif 90 91 /* 92 * All accesses to bridge hardware registers must be done 93 * using 32-bit loads and stores. 94 */ 95 typedef uint32_t bridgereg_t; 96 97 typedef uint64_t bridge_ate_t; 98 99 /* pointers to bridge ATEs 100 * are always "pointer to volatile" 101 */ 102 typedef volatile bridge_ate_t *bridge_ate_p; 103 104 /* 105 * It is generally preferred that hardware registers on the bridge 106 * are located from C code via this structure. 107 * 108 * Generated from Bridge spec dated 04oct95 109 */ 110 111 112 /* 113 * pic_widget_cfg_s is a local definition of widget_cfg_t but with 114 * a union of 64bit & 32bit registers, since PIC has 64bit widget 115 * registers but BRIDGE and XBRIDGE have 32bit. PIC registers that 116 * have valid bits (ie. not just reserved) in the upper 32bits are 117 * defined as a union so we can access them as 64bit for PIC and 118 * as 32bit for BRIDGE and XBRIDGE. 119 */ 120 typedef volatile struct pic_widget_cfg_s { 121 bridgereg_t _b_wid_id; /* 0x000004 */ 122 bridgereg_t _pad_000000; 123 124 union { 125 picreg_t _p_wid_stat; /* 0x000008 */ 126 struct { 127 bridgereg_t _b_wid_stat; /* 0x00000C */ 128 bridgereg_t _b_pad_000008; 129 } _b; 130 } u_wid_stat; 131 #define __p_wid_stat_64 u_wid_stat._p_wid_stat 132 #define __b_wid_stat u_wid_stat._b._b_wid_stat 133 134 bridgereg_t _b_wid_err_upper; /* 0x000014 */ 135 bridgereg_t _pad_000010; 136 137 union { 138 picreg_t _p_wid_err_lower; /* 0x000018 */ 139 struct { 140 bridgereg_t _b_wid_err_lower; /* 0x00001C */ 141 bridgereg_t _b_pad_000018; 142 } _b; 143 } u_wid_err_lower; 144 #define __p_wid_err_64 u_wid_err_lower._p_wid_err_lower 145 #define __b_wid_err_lower u_wid_err_lower._b._b_wid_err_lower 146 147 union { 148 picreg_t _p_wid_control; /* 0x000020 */ 149 struct { 150 bridgereg_t _b_wid_control; /* 0x000024 */ 151 bridgereg_t _b_pad_000020; 152 } _b; 153 } u_wid_control; 154 #define __p_wid_control_64 u_wid_control._p_wid_control 155 #define __b_wid_control u_wid_control._b._b_wid_control 156 157 bridgereg_t _b_wid_req_timeout; /* 0x00002C */ 158 bridgereg_t _pad_000028; 159 160 bridgereg_t _b_wid_int_upper; /* 0x000034 */ 161 bridgereg_t _pad_000030; 162 163 union { 164 picreg_t _p_wid_int_lower; /* 0x000038 */ 165 struct { 166 bridgereg_t _b_wid_int_lower; /* 0x00003C */ 167 bridgereg_t _b_pad_000038; 168 } _b; 169 } u_wid_int_lower; 170 #define __p_wid_int_64 u_wid_int_lower._p_wid_int_lower 171 #define __b_wid_int_lower u_wid_int_lower._b._b_wid_int_lower 172 173 bridgereg_t _b_wid_err_cmdword; /* 0x000044 */ 174 bridgereg_t _pad_000040; 175 176 bridgereg_t _b_wid_llp; /* 0x00004C */ 177 bridgereg_t _pad_000048; 178 179 bridgereg_t _b_wid_tflush; /* 0x000054 */ 180 bridgereg_t _pad_000050; 181 } pic_widget_cfg_t; 182 183 /* 184 * BRIDGE, XBRIDGE, PIC register definitions. NOTE: Prior to PIC, registers 185 * were a 32bit quantity and double word aligned (and only accessible as a 186 * 32bit word. PIC registers are 64bits and accessible as words or double 187 * words. PIC registers that have valid bits (ie. not just reserved) in the 188 * upper 32bits are defined as a union of one 64bit picreg_t and two 32bit 189 * bridgereg_t so we can access them both ways. 190 * 191 * It is generally preferred that hardware registers on the bridge are 192 * located from C code via this structure. 193 * 194 * Generated from Bridge spec dated 04oct95 195 */ 196 197 typedef volatile struct bridge_s { 198 199 /* 0x000000-0x00FFFF -- Local Registers */ 200 201 /* 0x000000-0x000057 -- Standard Widget Configuration */ 202 union { 203 widget_cfg_t xtalk_widget_def; /* 0x000000 */ 204 pic_widget_cfg_t local_widget_def; /* 0x000000 */ 205 } u_wid; 206 207 /* 32bit widget register access via the widget_cfg_t */ 208 #define b_widget u_wid.xtalk_widget_def 209 210 /* 32bit widget register access via the pic_widget_cfg_t */ 211 #define b_wid_id u_wid.local_widget_def._b_wid_id 212 #define b_wid_stat u_wid.local_widget_def.__b_wid_stat 213 #define b_wid_err_upper u_wid.local_widget_def._b_wid_err_upper 214 #define b_wid_err_lower u_wid.local_widget_def.__b_wid_err_lower 215 #define b_wid_control u_wid.local_widget_def.__b_wid_control 216 #define b_wid_req_timeout u_wid.local_widget_def._b_wid_req_timeout 217 #define b_wid_int_upper u_wid.local_widget_def._b_wid_int_upper 218 #define b_wid_int_lower u_wid.local_widget_def.__b_wid_int_lower 219 #define b_wid_err_cmdword u_wid.local_widget_def._b_wid_err_cmdword 220 #define b_wid_llp u_wid.local_widget_def._b_wid_llp 221 #define b_wid_tflush u_wid.local_widget_def._b_wid_tflush 222 223 /* 64bit widget register access via the pic_widget_cfg_t */ 224 #define p_wid_stat_64 u_wid.local_widget_def.__p_wid_stat_64 225 #define p_wid_err_64 u_wid.local_widget_def.__p_wid_err_64 226 #define p_wid_control_64 u_wid.local_widget_def.__p_wid_control_64 227 #define p_wid_int_64 u_wid.local_widget_def.__p_wid_int_64 228 229 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */ 230 bridgereg_t b_wid_aux_err; /* 0x00005C */ 231 bridgereg_t _pad_000058; 232 233 bridgereg_t b_wid_resp_upper; /* 0x000064 */ 234 bridgereg_t _pad_000060; 235 236 union { 237 picreg_t _p_wid_resp_lower; /* 0x000068 */ 238 struct { 239 bridgereg_t _b_wid_resp_lower; /* 0x00006C */ 240 bridgereg_t _b_pad_000068; 241 } _b; 242 } u_wid_resp_lower; 243 #define p_wid_resp_64 u_wid_resp_lower._p_wid_resp_lower 244 #define b_wid_resp_lower u_wid_resp_lower._b._b_wid_resp_lower 245 246 bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ 247 bridgereg_t _pad_000070; 248 249 union { 250 picreg_t _p_addr_lkerr; /* 0x000078 */ 251 struct { 252 bridgereg_t _b_pad_00007C; 253 bridgereg_t _b_pad_000078; 254 } _b; 255 } u_addr_lkerr; 256 #define p_addr_lkerr_64 u_addr_lkerr._p_addr_lkerr 257 258 /* 0x000080-0x00008F -- PMU */ 259 bridgereg_t b_dir_map; /* 0x000084 */ 260 bridgereg_t _pad_000080; 261 262 bridgereg_t _pad_00008C; 263 bridgereg_t _pad_000088; 264 265 /* 0x000090-0x00009F -- SSRAM */ 266 bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ 267 bridgereg_t _pad_000090; 268 #define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ 269 #define b_map_fault b_ram_perr_or_map_fault /* Xbridge & PIC */ 270 271 bridgereg_t _pad_00009C; 272 bridgereg_t _pad_000098; 273 274 /* 0x0000A0-0x0000AF -- Arbitration */ 275 bridgereg_t b_arb; /* 0x0000A4 */ 276 bridgereg_t _pad_0000A0; 277 278 bridgereg_t _pad_0000AC; 279 bridgereg_t _pad_0000A8; 280 281 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ 282 union { 283 picreg_t _p_ate_parity_err; /* 0x0000B0 */ 284 struct { 285 bridgereg_t _b_nic; /* 0x0000B4 */ 286 bridgereg_t _b_pad_0000B0; 287 } _b; 288 } u_ate_parity_err_or_nic; 289 #define p_ate_parity_err_64 u_ate_parity_err_or_nic._p_ate_parity_err 290 #define b_nic u_ate_parity_err_or_nic._b._b_nic 291 292 bridgereg_t _pad_0000BC; 293 bridgereg_t _pad_0000B8; 294 295 /* 0x0000C0-0x0000FF -- PCI/GIO */ 296 bridgereg_t b_bus_timeout; /* 0x0000C4 */ 297 bridgereg_t _pad_0000C0; 298 #define b_pci_bus_timeout b_bus_timeout 299 300 bridgereg_t b_pci_cfg; /* 0x0000CC */ 301 bridgereg_t _pad_0000C8; 302 303 bridgereg_t b_pci_err_upper; /* 0x0000D4 */ 304 bridgereg_t _pad_0000D0; 305 #define b_gio_err_upper b_pci_err_upper 306 307 union { 308 picreg_t _p_pci_err_lower; /* 0x0000D8 */ 309 struct { 310 bridgereg_t _b_pci_err_lower; /* 0x0000DC */ 311 bridgereg_t _b_pad_0000D8; 312 } _b; 313 } u_pci_err_lower; 314 #define p_pci_err_64 u_pci_err_lower._p_pci_err_lower 315 #define b_pci_err_lower u_pci_err_lower._b._b_pci_err_lower 316 #define b_gio_err_lower b_pci_err_lower 317 318 bridgereg_t _pad_0000E0[8]; 319 320 /* 0x000100-0x0001FF -- Interrupt */ 321 union { 322 picreg_t _p_int_status; /* 0x000100 */ 323 struct { 324 bridgereg_t _b_int_status; /* 0x000104 */ 325 bridgereg_t _b_pad_000100; 326 } _b; 327 } u_int_status; 328 #define p_int_status_64 u_int_status._p_int_status 329 #define b_int_status u_int_status._b._b_int_status 330 331 union { 332 picreg_t _p_int_enable; /* 0x000108 */ 333 struct { 334 bridgereg_t _b_int_enable; /* 0x00010C */ 335 bridgereg_t _b_pad_000108; 336 } _b; 337 } u_int_enable; 338 #define p_int_enable_64 u_int_enable._p_int_enable 339 #define b_int_enable u_int_enable._b._b_int_enable 340 341 union { 342 picreg_t _p_int_rst_stat; /* 0x000110 */ 343 struct { 344 bridgereg_t _b_int_rst_stat; /* 0x000114 */ 345 bridgereg_t _b_pad_000110; 346 } _b; 347 } u_int_rst_stat; 348 #define p_int_rst_stat_64 u_int_rst_stat._p_int_rst_stat 349 #define b_int_rst_stat u_int_rst_stat._b._b_int_rst_stat 350 351 bridgereg_t b_int_mode; /* 0x00011C */ 352 bridgereg_t _pad_000118; 353 354 bridgereg_t b_int_device; /* 0x000124 */ 355 bridgereg_t _pad_000120; 356 357 bridgereg_t b_int_host_err; /* 0x00012C */ 358 bridgereg_t _pad_000128; 359 360 union { 361 picreg_t _p_int_addr[8]; /* 0x0001{30,,,68} */ 362 struct { 363 bridgereg_t addr; /* 0x0001{34,,,6C} */ 364 bridgereg_t _b_pad; 365 } _b[8]; 366 } u_int_addr; 367 #define p_int_addr_64 u_int_addr._p_int_addr 368 #define b_int_addr u_int_addr._b 369 370 union { 371 picreg_t _p_err_int_view; /* 0x000170 */ 372 struct { 373 bridgereg_t _b_err_int_view; /* 0x000174 */ 374 bridgereg_t _b_pad_000170; 375 } _b; 376 } u_err_int_view; 377 #define p_err_int_view_64 u_err_int_view._p_err_int_view 378 #define b_err_int_view u_err_int_view._b._b_err_int_view 379 380 union { 381 picreg_t _p_mult_int; /* 0x000178 */ 382 struct { 383 bridgereg_t _b_mult_int; /* 0x00017C */ 384 bridgereg_t _b_pad_000178; 385 } _b; 386 } u_mult_int; 387 #define p_mult_int_64 u_mult_int._p_mult_int 388 #define b_mult_int u_mult_int._b._b_mult_int 389 390 struct { 391 bridgereg_t intr; /* 0x0001{84,,,BC} */ 392 bridgereg_t __pad; 393 } b_force_always[8]; 394 395 struct { 396 bridgereg_t intr; /* 0x0001{C4,,,FC} */ 397 bridgereg_t __pad; 398 } b_force_pin[8]; 399 400 /* 0x000200-0x0003FF -- Device */ 401 struct { 402 bridgereg_t reg; /* 0x0002{04,,,3C} */ 403 bridgereg_t __pad; 404 } b_device[8]; 405 406 struct { 407 bridgereg_t reg; /* 0x0002{44,,,7C} */ 408 bridgereg_t __pad; 409 } b_wr_req_buf[8]; 410 411 struct { 412 bridgereg_t reg; /* 0x0002{84,,,8C} */ 413 bridgereg_t __pad; 414 } b_rrb_map[2]; 415 #define b_even_resp b_rrb_map[0].reg /* 0x000284 */ 416 #define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ 417 418 bridgereg_t b_resp_status; /* 0x000294 */ 419 bridgereg_t _pad_000290; 420 421 bridgereg_t b_resp_clear; /* 0x00029C */ 422 bridgereg_t _pad_000298; 423 424 bridgereg_t _pad_0002A0[24]; 425 426 /* Xbridge/PIC only */ 427 union { 428 struct { 429 picreg_t lower; /* 0x0003{08,,,F8} */ 430 picreg_t upper; /* 0x0003{00,,,F0} */ 431 } _p[16]; 432 struct { 433 bridgereg_t upper; /* 0x0003{04,,,F4} */ 434 bridgereg_t _b_pad1; 435 bridgereg_t lower; /* 0x0003{0C,,,FC} */ 436 bridgereg_t _b_pad2; 437 } _b[16]; 438 } u_buf_addr_match; 439 #define p_buf_addr_match_64 u_buf_addr_match._p 440 #define b_buf_addr_match u_buf_addr_match._b 441 442 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ 443 struct { 444 bridgereg_t flush_w_touch; /* 0x000{404,,,5C4} */ 445 bridgereg_t __pad1; 446 bridgereg_t flush_wo_touch; /* 0x000{40C,,,5CC} */ 447 bridgereg_t __pad2; 448 bridgereg_t inflight; /* 0x000{414,,,5D4} */ 449 bridgereg_t __pad3; 450 bridgereg_t prefetch; /* 0x000{41C,,,5DC} */ 451 bridgereg_t __pad4; 452 bridgereg_t total_pci_retry; /* 0x000{424,,,5E4} */ 453 bridgereg_t __pad5; 454 bridgereg_t max_pci_retry; /* 0x000{42C,,,5EC} */ 455 bridgereg_t __pad6; 456 bridgereg_t max_latency; /* 0x000{434,,,5F4} */ 457 bridgereg_t __pad7; 458 bridgereg_t clear_all; /* 0x000{43C,,,5FC} */ 459 bridgereg_t __pad8; 460 } b_buf_count[8]; 461 462 /* 463 * "PCI/X registers that are specific to PIC". See pic.h. 464 */ 465 466 /* 0x000600-0x0009FF -- PCI/X registers */ 467 picreg_t p_pcix_bus_err_addr_64; /* 0x000600 */ 468 picreg_t p_pcix_bus_err_attr_64; /* 0x000608 */ 469 picreg_t p_pcix_bus_err_data_64; /* 0x000610 */ 470 picreg_t p_pcix_pio_split_addr_64; /* 0x000618 */ 471 picreg_t p_pcix_pio_split_attr_64; /* 0x000620 */ 472 picreg_t p_pcix_dma_req_err_attr_64; /* 0x000628 */ 473 picreg_t p_pcix_dma_req_err_addr_64; /* 0x000630 */ 474 picreg_t p_pcix_timeout_64; /* 0x000638 */ 475 476 picreg_t _pad_000600[120]; 477 478 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ 479 struct { 480 picreg_t p_buf_attr; /* 0X000{A08,,,AF8} */ 481 picreg_t p_buf_addr; /* 0x000{A00,,,AF0} */ 482 } p_pcix_read_buf_64[16]; 483 484 struct { 485 picreg_t p_buf_attr; /* 0x000{B08,,,BE8} */ 486 picreg_t p_buf_addr; /* 0x000{B00,,,BE0} */ 487 picreg_t __pad1; /* 0x000{B18,,,BF8} */ 488 picreg_t p_buf_valid; /* 0x000{B10,,,BF0} */ 489 } p_pcix_write_buf_64[8]; 490 491 /* 492 * end "PCI/X registers that are specific to PIC" 493 */ 494 495 char _pad_000c00[0x010000 - 0x000c00]; 496 497 /* 0x010000-0x011fff -- Internal Address Translation Entry RAM */ 498 /* 499 * Xbridge and PIC have 1024 internal ATE's and the Bridge has 128. 500 * Make enough room for the Xbridge/PIC ATE's and depend on runtime 501 * checks to limit access to bridge ATE's. 502 * 503 * In [X]bridge the internal ATE Ram is writen as double words only, 504 * but due to internal design issues it is read back as single words. 505 * i.e: 506 * b_int_ate_ram[index].hi.rd << 32 | xb_int_ate_ram_lo[index].rd 507 */ 508 union { 509 bridge_ate_t wr; /* write-only */ /* 0x01{0000,,,1FF8} */ 510 struct { 511 bridgereg_t rd; /* read-only */ /* 0x01{0004,,,1FFC} */ 512 bridgereg_t _p_pad; 513 } hi; 514 } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; 515 #define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd 516 517 /* 0x012000-0x013fff -- Internal Address Translation Entry RAM LOW */ 518 struct { 519 bridgereg_t rd; /* read-only */ /* 0x01{2004,,,3FFC} */ 520 bridgereg_t _p_pad; 521 } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; 522 523 char _pad_014000[0x18000 - 0x014000]; 524 525 /* 0x18000-0x197F8 -- PIC Write Request Ram */ 526 /* 0x18000 - 0x187F8 */ 527 picreg_t p_wr_req_lower[PIC_WR_REQ_BUFSIZE]; 528 /* 0x18800 - 0x18FF8 */ 529 picreg_t p_wr_req_upper[PIC_WR_REQ_BUFSIZE]; 530 /* 0x19000 - 0x197F8 */ 531 picreg_t p_wr_req_parity[PIC_WR_REQ_BUFSIZE]; 532 533 char _pad_019800[0x20000 - 0x019800]; 534 535 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */ 536 union { /* make all access sizes available. */ 537 uchar_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ 538 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ 539 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ 540 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ 541 union { 542 uchar_t c[0x100 / 1]; 543 uint16_t s[0x100 / 2]; 544 uint32_t l[0x100 / 4]; 545 uint64_t d[0x100 / 8]; 546 } f[8]; 547 } b_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */ 548 549 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ 550 union { /* make all access sizes available. */ 551 uchar_t c[0x1000 / 1]; 552 uint16_t s[0x1000 / 2]; 553 uint32_t l[0x1000 / 4]; 554 uint64_t d[0x1000 / 8]; 555 union { 556 uchar_t c[0x100 / 1]; 557 uint16_t s[0x100 / 2]; 558 uint32_t l[0x100 / 4]; 559 uint64_t d[0x100 / 8]; 560 } f[8]; 561 } b_type1_cfg; /* 0x028000-0x029000 */ 562 563 char _pad_029000[0x007000]; /* 0x029000-0x030000 */ 564 565 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ 566 union { 567 uchar_t c[8 / 1]; 568 uint16_t s[8 / 2]; 569 uint32_t l[8 / 4]; 570 uint64_t d[8 / 8]; 571 } b_pci_iack; /* 0x030000-0x030007 */ 572 573 uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ 574 575 /* 0x080000-0x0FFFFF -- External Address Translation Entry RAM */ 576 bridge_ate_t b_ext_ate_ram[0x10000]; 577 578 /* 0x100000-0x1FFFFF -- Reserved */ 579 char _pad_100000[0x200000-0x100000]; 580 581 /* 0x200000-0xBFFFFF -- PCI/GIO Device Spaces */ 582 union { /* make all access sizes available. */ 583 uchar_t c[0x100000 / 1]; 584 uint16_t s[0x100000 / 2]; 585 uint32_t l[0x100000 / 4]; 586 uint64_t d[0x100000 / 8]; 587 } b_devio_raw[10]; 588 589 /* b_devio macro is a bit strange; it reflects the 590 * fact that the Bridge ASIC provides 2M for the 591 * first two DevIO windows and 1M for the other six. 592 */ 593 #define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] 594 595 /* 0xC00000-0xFFFFFF -- External Flash Proms 1,0 */ 596 union { /* make all access sizes available. */ 597 uchar_t c[0x400000 / 1]; /* read-only */ 598 uint16_t s[0x400000 / 2]; /* read-write */ 599 uint32_t l[0x400000 / 4]; /* read-only */ 600 uint64_t d[0x400000 / 8]; /* read-only */ 601 } b_external_flash; 602 } bridge_t; 603 604 #define berr_field berr_un.berr_st 605 #endif /* __ASSEMBLY__ */ 606 607 /* 608 * The values of these macros can and should be crosschecked 609 * regularly against the offsets of the like-named fields 610 * within the "bridge_t" structure above. 611 */ 612 613 /* Byte offset macros for Bridge internal registers */ 614 615 #define BRIDGE_WID_ID WIDGET_ID 616 #define BRIDGE_WID_STAT WIDGET_STATUS 617 #define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR 618 #define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR 619 #define BRIDGE_WID_CONTROL WIDGET_CONTROL 620 #define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT 621 #define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR 622 #define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR 623 #define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD 624 #define BRIDGE_WID_LLP WIDGET_LLP_CFG 625 #define BRIDGE_WID_TFLUSH WIDGET_TFLUSH 626 627 #define BRIDGE_WID_AUX_ERR 0x00005C /* Aux Error Command Word */ 628 #define BRIDGE_WID_RESP_UPPER 0x000064 /* Response Buf Upper Addr */ 629 #define BRIDGE_WID_RESP_LOWER 0x00006C /* Response Buf Lower Addr */ 630 #define BRIDGE_WID_TST_PIN_CTRL 0x000074 /* Test pin control */ 631 632 #define BRIDGE_DIR_MAP 0x000084 /* Direct Map reg */ 633 634 /* Bridge has SSRAM Parity Error and Xbridge has Map Fault here */ 635 #define BRIDGE_RAM_PERR 0x000094 /* SSRAM Parity Error */ 636 #define BRIDGE_MAP_FAULT 0x000094 /* Map Fault */ 637 638 #define BRIDGE_ARB 0x0000A4 /* Arbitration Priority reg */ 639 640 #define BRIDGE_NIC 0x0000B4 /* Number In A Can */ 641 642 #define BRIDGE_BUS_TIMEOUT 0x0000C4 /* Bus Timeout Register */ 643 #define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT 644 #define BRIDGE_PCI_CFG 0x0000CC /* PCI Type 1 Config reg */ 645 #define BRIDGE_PCI_ERR_UPPER 0x0000D4 /* PCI error Upper Addr */ 646 #define BRIDGE_PCI_ERR_LOWER 0x0000DC /* PCI error Lower Addr */ 647 648 #define BRIDGE_INT_STATUS 0x000104 /* Interrupt Status */ 649 #define BRIDGE_INT_ENABLE 0x00010C /* Interrupt Enables */ 650 #define BRIDGE_INT_RST_STAT 0x000114 /* Reset Intr Status */ 651 #define BRIDGE_INT_MODE 0x00011C /* Interrupt Mode */ 652 #define BRIDGE_INT_DEVICE 0x000124 /* Interrupt Device */ 653 #define BRIDGE_INT_HOST_ERR 0x00012C /* Host Error Field */ 654 655 #define BRIDGE_INT_ADDR0 0x000134 /* Host Address Reg */ 656 #define BRIDGE_INT_ADDR_OFF 0x000008 /* Host Addr offset (1..7) */ 657 #define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF) 658 659 #define BRIDGE_INT_VIEW 0x000174 /* Interrupt view */ 660 #define BRIDGE_MULTIPLE_INT 0x00017c /* Multiple interrupt occurred */ 661 662 #define BRIDGE_FORCE_ALWAYS0 0x000184 /* Force an interrupt (always)*/ 663 #define BRIDGE_FORCE_ALWAYS_OFF 0x000008 /* Force Always offset */ 664 #define BRIDGE_FORCE_ALWAYS(x) (BRIDGE_FORCE_ALWAYS0+(x)*BRIDGE_FORCE_ALWAYS_OFF) 665 666 #define BRIDGE_FORCE_PIN0 0x0001c4 /* Force an interrupt */ 667 #define BRIDGE_FORCE_PIN_OFF 0x000008 /* Force Pin offset */ 668 #define BRIDGE_FORCE_PIN(x) (BRIDGE_FORCE_PIN0+(x)*BRIDGE_FORCE_PIN_OFF) 669 670 #define BRIDGE_DEVICE0 0x000204 /* Device 0 */ 671 #define BRIDGE_DEVICE_OFF 0x000008 /* Device offset (1..7) */ 672 #define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF) 673 674 #define BRIDGE_WR_REQ_BUF0 0x000244 /* Write Request Buffer 0 */ 675 #define BRIDGE_WR_REQ_BUF_OFF 0x000008 /* Buffer Offset (1..7) */ 676 #define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF) 677 678 #define BRIDGE_EVEN_RESP 0x000284 /* Even Device Response Buf */ 679 #define BRIDGE_ODD_RESP 0x00028C /* Odd Device Response Buf */ 680 681 #define BRIDGE_RESP_STATUS 0x000294 /* Read Response Status reg */ 682 #define BRIDGE_RESP_CLEAR 0x00029C /* Read Response Clear reg */ 683 684 #define BRIDGE_BUF_ADDR_UPPER0 0x000304 685 #define BRIDGE_BUF_ADDR_UPPER_OFF 0x000010 /* PCI Buffer Upper Offset */ 686 #define BRIDGE_BUF_ADDR_UPPER(x) (BRIDGE_BUF_ADDR_UPPER0+(x)*BRIDGE_BUF_ADDR_UPPER_OFF) 687 688 #define BRIDGE_BUF_ADDR_LOWER0 0x00030c 689 #define BRIDGE_BUF_ADDR_LOWER_OFF 0x000010 /* PCI Buffer Upper Offset */ 690 #define BRIDGE_BUF_ADDR_LOWER(x) (BRIDGE_BUF_ADDR_LOWER0+(x)*BRIDGE_BUF_ADDR_LOWER_OFF) 691 692 /* 693 * Performance Monitor Registers. 694 * 695 * The Performance registers are those registers which are associated with 696 * monitoring the performance of PCI generated reads to the host environ 697 * ment. Because of the size of the register file only the even registers 698 * were instrumented. 699 */ 700 701 #define BRIDGE_BUF_OFF 0x40 702 #define BRIDGE_BUF_NEXT(base, off) (base+((off)*BRIDGE_BUF_OFF)) 703 704 /* 705 * Buffer (x) Flush Count with Data Touch Register. 706 * 707 * This counter is incremented each time the corresponding response buffer 708 * is flushed after at least a single data element in the buffer is used. 709 * A word write to this address clears the count. 710 */ 711 712 #define BRIDGE_BUF_0_FLUSH_TOUCH 0x000404 713 #define BRIDGE_BUF_2_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 1) 714 #define BRIDGE_BUF_4_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 2) 715 #define BRIDGE_BUF_6_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 3) 716 #define BRIDGE_BUF_8_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 4) 717 #define BRIDGE_BUF_10_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 5) 718 #define BRIDGE_BUF_12_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 6) 719 #define BRIDGE_BUF_14_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 7) 720 721 /* 722 * Buffer (x) Flush Count w/o Data Touch Register 723 * 724 * This counter is incremented each time the corresponding response buffer 725 * is flushed without any data element in the buffer being used. A word 726 * write to this address clears the count. 727 */ 728 729 730 #define BRIDGE_BUF_0_FLUSH_NOTOUCH 0x00040c 731 #define BRIDGE_BUF_2_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 1) 732 #define BRIDGE_BUF_4_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 2) 733 #define BRIDGE_BUF_6_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 3) 734 #define BRIDGE_BUF_8_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 4) 735 #define BRIDGE_BUF_10_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 5) 736 #define BRIDGE_BUF_12_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 6) 737 #define BRIDGE_BUF_14_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 7) 738 739 /* 740 * Buffer (x) Request in Flight Count Register 741 * 742 * This counter is incremented on each bus clock while the request is in 743 * flight. A word write to this address clears the count. 744 */ 745 746 #define BRIDGE_BUF_0_INFLIGHT 0x000414 747 #define BRIDGE_BUF_2_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 1) 748 #define BRIDGE_BUF_4_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 2) 749 #define BRIDGE_BUF_6_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 3) 750 #define BRIDGE_BUF_8_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 4) 751 #define BRIDGE_BUF_10_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 5) 752 #define BRIDGE_BUF_12_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 6) 753 #define BRIDGE_BUF_14_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 7) 754 755 /* 756 * Buffer (x) Prefetch Request Count Register 757 * 758 * This counter is incremented each time the request using this buffer was 759 * generated from the prefetcher. A word write to this address clears the 760 * count. 761 */ 762 763 #define BRIDGE_BUF_0_PREFETCH 0x00041C 764 #define BRIDGE_BUF_2_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 1) 765 #define BRIDGE_BUF_4_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 2) 766 #define BRIDGE_BUF_6_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 3) 767 #define BRIDGE_BUF_8_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 4) 768 #define BRIDGE_BUF_10_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 5) 769 #define BRIDGE_BUF_12_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 6) 770 #define BRIDGE_BUF_14_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 7) 771 772 /* 773 * Buffer (x) Total PCI Retry Count Register 774 * 775 * This counter is incremented each time a PCI bus retry occurs and the ad 776 * dress matches the tag for the selected buffer. The buffer must also has 777 * this request in-flight. A word write to this address clears the count. 778 */ 779 780 #define BRIDGE_BUF_0_PCI_RETRY 0x000424 781 #define BRIDGE_BUF_2_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 1) 782 #define BRIDGE_BUF_4_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 2) 783 #define BRIDGE_BUF_6_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 3) 784 #define BRIDGE_BUF_8_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 4) 785 #define BRIDGE_BUF_10_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 5) 786 #define BRIDGE_BUF_12_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 6) 787 #define BRIDGE_BUF_14_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 7) 788 789 /* 790 * Buffer (x) Max PCI Retry Count Register 791 * 792 * This counter is contains the maximum retry count for a single request 793 * which was in-flight for this buffer. A word write to this address 794 * clears the count. 795 */ 796 797 #define BRIDGE_BUF_0_MAX_PCI_RETRY 0x00042C 798 #define BRIDGE_BUF_2_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 1) 799 #define BRIDGE_BUF_4_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 2) 800 #define BRIDGE_BUF_6_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 3) 801 #define BRIDGE_BUF_8_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 4) 802 #define BRIDGE_BUF_10_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 5) 803 #define BRIDGE_BUF_12_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 6) 804 #define BRIDGE_BUF_14_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 7) 805 806 /* 807 * Buffer (x) Max Latency Count Register 808 * 809 * This counter is contains the maximum count (in bus clocks) for a single 810 * request which was in-flight for this buffer. A word write to this 811 * address clears the count. 812 */ 813 814 #define BRIDGE_BUF_0_MAX_LATENCY 0x000434 815 #define BRIDGE_BUF_2_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 1) 816 #define BRIDGE_BUF_4_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 2) 817 #define BRIDGE_BUF_6_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 3) 818 #define BRIDGE_BUF_8_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 4) 819 #define BRIDGE_BUF_10_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 5) 820 #define BRIDGE_BUF_12_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 6) 821 #define BRIDGE_BUF_14_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 7) 822 823 /* 824 * Buffer (x) Clear All Register 825 * 826 * Any access to this register clears all the count values for the (x) 827 * registers. 828 */ 829 830 #define BRIDGE_BUF_0_CLEAR_ALL 0x00043C 831 #define BRIDGE_BUF_2_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 1) 832 #define BRIDGE_BUF_4_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 2) 833 #define BRIDGE_BUF_6_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 3) 834 #define BRIDGE_BUF_8_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 4) 835 #define BRIDGE_BUF_10_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 5) 836 #define BRIDGE_BUF_12_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 6) 837 #define BRIDGE_BUF_14_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 7) 838 839 /* end of Performance Monitor Registers */ 840 841 /* Byte offset macros for Bridge I/O space. 842 * 843 * NOTE: Where applicable please use the PCIBR_xxx or PCIBRIDGE_xxx 844 * macros (below) as they will handle [X]Bridge and PIC. For example, 845 * PCIBRIDGE_TYPE0_CFG_DEV0() vs BRIDGE_TYPE0_CFG_DEV0 846 */ 847 848 #define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */ 849 850 #define BRIDGE_TYPE0_CFG_DEV0 0x00020000 /* Type 0 Cfg, Device 0 */ 851 #define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000 /* Type 0 Cfg Slot Offset (1..7) */ 852 #define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */ 853 #define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\ 854 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) 855 #define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+\ 856 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ 857 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) 858 859 #define BRIDGE_TYPE1_CFG 0x00028000 /* Type 1 Cfg space */ 860 861 #define BRIDGE_PCI_IACK 0x00030000 /* PCI Interrupt Ack */ 862 #define BRIDGE_EXT_SSRAM 0x00080000 /* Extern SSRAM (ATE) */ 863 864 /* Byte offset macros for Bridge device IO spaces */ 865 866 #define BRIDGE_DEV_CNT 8 /* Up to 8 devices per bridge */ 867 #define BRIDGE_DEVIO0 0x00200000 /* Device IO 0 Addr */ 868 #define BRIDGE_DEVIO1 0x00400000 /* Device IO 1 Addr */ 869 #define BRIDGE_DEVIO2 0x00600000 /* Device IO 2 Addr */ 870 #define BRIDGE_DEVIO_OFF 0x00100000 /* Device IO Offset (3..7) */ 871 872 #define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */ 873 #define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */ 874 875 #ifndef __ASSEMBLY__ 876 877 #define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB) 878 879 /* 880 * The device space macros for PIC are more complicated because the PIC has 881 * two PCI/X bridges under the same widget. For PIC bus 0, the addresses are 882 * basically the same as for the [X]Bridge. For PIC bus 1, the addresses are 883 * offset by 0x800000. Here are two sets of macros. They are 884 * "PCIBRIDGE_xxx" that return the address based on the supplied bus number 885 * and also equivalent "PCIBR_xxx" macros that may be used with a 886 * pcibr_soft_s structure. Both should work with all bridges. 887 */ 888 #define PIC_BUS1_OFFSET 0x800000 889 890 #define PCIBRIDGE_TYPE0_CFG_DEV0(busnum) \ 891 ((busnum) ? BRIDGE_TYPE0_CFG_DEV0 + PIC_BUS1_OFFSET : \ 892 BRIDGE_TYPE0_CFG_DEV0) 893 #define PCIBRIDGE_TYPE1_CFG(busnum) \ 894 ((busnum) ? BRIDGE_TYPE1_CFG + PIC_BUS1_OFFSET : BRIDGE_TYPE1_CFG) 895 #define PCIBRIDGE_TYPE0_CFG_DEV(busnum, s) \ 896 (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\ 897 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) 898 #define PCIBRIDGE_TYPE0_CFG_DEVF(busnum, s, f) \ 899 (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\ 900 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ 901 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) 902 #define PCIBRIDGE_DEVIO0(busnum) ((busnum) ? \ 903 (BRIDGE_DEVIO0 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO0) 904 #define PCIBRIDGE_DEVIO1(busnum) ((busnum) ? \ 905 (BRIDGE_DEVIO1 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO1) 906 #define PCIBRIDGE_DEVIO2(busnum) ((busnum) ? \ 907 (BRIDGE_DEVIO2 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO2) 908 #define PCIBRIDGE_DEVIO(busnum, x) \ 909 ((x)<=1 ? PCIBRIDGE_DEVIO0(busnum)+(x)*BRIDGE_DEVIO_2MB : \ 910 PCIBRIDGE_DEVIO2(busnum)+((x)-2)*BRIDGE_DEVIO_1MB) 911 912 #define PCIBR_BRIDGE_DEVIO0(ps) PCIBRIDGE_DEVIO0((ps)->bs_busnum) 913 #define PCIBR_BRIDGE_DEVIO1(ps) PCIBRIDGE_DEVIO1((ps)->bs_busnum) 914 #define PCIBR_BRIDGE_DEVIO2(ps) PCIBRIDGE_DEVIO2((ps)->bs_busnum) 915 #define PCIBR_BRIDGE_DEVIO(ps, s) PCIBRIDGE_DEVIO((ps)->bs_busnum, s) 916 917 #define PCIBR_TYPE1_CFG(ps) PCIBRIDGE_TYPE1_CFG((ps)->bs_busnum) 918 #define PCIBR_BUS_TYPE0_CFG_DEV0(ps) PCIBR_TYPE0_CFG_DEV(ps, 0) 919 #define PCIBR_TYPE0_CFG_DEV(ps, s) \ 920 ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1) : \ 921 PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s)) 922 #define PCIBR_BUS_TYPE0_CFG_DEVF(ps,s,f) \ 923 ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,(s+1),f) : \ 924 PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,s,f)) 925 926 #endif /* LANGUAGE_C */ 927 928 #define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */ 929 930 /* ======================================================================== 931 * Bridge register bit field definitions 932 */ 933 934 /* Widget part number of bridge */ 935 #define BRIDGE_WIDGET_PART_NUM 0xc002 936 #define XBRIDGE_WIDGET_PART_NUM 0xd002 937 938 /* Manufacturer of bridge */ 939 #define BRIDGE_WIDGET_MFGR_NUM 0x036 940 #define XBRIDGE_WIDGET_MFGR_NUM 0x024 941 942 /* Revision numbers for known [X]Bridge revisions */ 943 #define BRIDGE_REV_A 0x1 944 #define BRIDGE_REV_B 0x2 945 #define BRIDGE_REV_C 0x3 946 #define BRIDGE_REV_D 0x4 947 #define XBRIDGE_REV_A 0x1 948 #define XBRIDGE_REV_B 0x2 949 950 /* macros to determine bridge type. 'wid' == widget identification */ 951 #define IS_BRIDGE(wid) (XWIDGET_PART_NUM(wid) == BRIDGE_WIDGET_PART_NUM && \ 952 XWIDGET_MFG_NUM(wid) == BRIDGE_WIDGET_MFGR_NUM) 953 #define IS_XBRIDGE(wid) (XWIDGET_PART_NUM(wid) == XBRIDGE_WIDGET_PART_NUM && \ 954 XWIDGET_MFG_NUM(wid) == XBRIDGE_WIDGET_MFGR_NUM) 955 #define IS_PIC_BUS0(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS0 && \ 956 XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM) 957 #define IS_PIC_BUS1(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS1 && \ 958 XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM) 959 #define IS_PIC_BRIDGE(wid) (IS_PIC_BUS0(wid) || IS_PIC_BUS1(wid)) 960 961 /* Part + Rev numbers allows distinction and acscending sequence */ 962 #define BRIDGE_PART_REV_A (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A) 963 #define BRIDGE_PART_REV_B (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B) 964 #define BRIDGE_PART_REV_C (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_C) 965 #define BRIDGE_PART_REV_D (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_D) 966 #define XBRIDGE_PART_REV_A (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_A) 967 #define XBRIDGE_PART_REV_B (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B) 968 969 /* Bridge widget status register bits definition */ 970 #define PIC_STAT_PCIX_SPEED (0x3ull << 34) 971 #define PIC_STAT_PCIX_ACTIVE (0x1ull << 33) 972 #define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24) 973 #define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16) 974 #define BRIDGE_STAT_FLASH_SELECT (0x1 << 6) 975 #define BRIDGE_STAT_PCI_GIO_N (0x1 << 5) 976 #define BRIDGE_STAT_PENDING (0x1F << 0) 977 978 /* Bridge widget control register bits definition */ 979 #define PIC_CTRL_NO_SNOOP (0x1ull << 62) 980 #define PIC_CTRL_RELAX_ORDER (0x1ull << 61) 981 #define PIC_CTRL_BUS_NUM(x) ((unsigned long long)(x) << 48) 982 #define PIC_CTRL_BUS_NUM_MASK (PIC_CTRL_BUS_NUM(0xff)) 983 #define PIC_CTRL_DEV_NUM(x) ((unsigned long long)(x) << 43) 984 #define PIC_CTRL_DEV_NUM_MASK (PIC_CTRL_DEV_NUM(0x1f)) 985 #define PIC_CTRL_FUN_NUM(x) ((unsigned long long)(x) << 40) 986 #define PIC_CTRL_FUN_NUM_MASK (PIC_CTRL_FUN_NUM(0x7)) 987 #define PIC_CTRL_PAR_EN_REQ (0x1ull << 29) 988 #define PIC_CTRL_PAR_EN_RESP (0x1ull << 30) 989 #define PIC_CTRL_PAR_EN_ATE (0x1ull << 31) 990 #define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) /* bridge only */ 991 #define BRIDGE_CTRL_EN_CLK50 (0x1 << 30) 992 #define BRIDGE_CTRL_EN_CLK40 (0x1 << 29) 993 #define BRIDGE_CTRL_EN_CLK33 (0x1 << 28) 994 #define BRIDGE_CTRL_RST(n) ((n) << 24) 995 #define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF)) 996 #define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x))) 997 #define BRIDGE_CTRL_IO_SWAP (0x1 << 23) 998 #define BRIDGE_CTRL_MEM_SWAP (0x1 << 22) 999 #define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21) 1000 #define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20) 1001 #define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19) 1002 #define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17) 1003 #define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3)) 1004 #define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3)) 1005 #define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2)) 1006 #define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1)) 1007 #define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0)) 1008 #define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16) 1009 #define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12) 1010 #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf)) 1011 #define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11) 1012 #define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10) 1013 #define BRIDGE_CTRL_SYS_END (0x1 << 9) 1014 #define BRIDGE_CTRL_PCI_SPEED (0x3 << 4) 1015 1016 #define BRIDGE_CTRL_BUS_SPEED(n) ((n) << 4) 1017 #define BRIDGE_CTRL_BUS_SPEED_MASK (BRIDGE_CTRL_BUS_SPEED(0x3)) 1018 #define BRIDGE_CTRL_BUS_SPEED_33 0x00 1019 #define BRIDGE_CTRL_BUS_SPEED_66 0x10 1020 #define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4) 1021 #define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f)) 1022 #define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0) 1023 #define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf)) 1024 1025 /* Bridge Response buffer Error Upper Register bit fields definition */ 1026 #define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20) 1027 #define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) 1028 #define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16) 1029 #define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) 1030 #define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF) 1031 1032 #define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \ 1033 (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \ 1034 BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) 1035 1036 #define BRIDGE_RESP_ERRUPPR_DEVICE(x) \ 1037 (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \ 1038 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) 1039 1040 /* Bridge direct mapping register bits definition */ 1041 #define BRIDGE_DIRMAP_W_ID_SHFT 20 1042 #define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT) 1043 #define BRIDGE_DIRMAP_RMF_64 (0x1 << 18) 1044 #define BRIDGE_DIRMAP_ADD512 (0x1 << 17) 1045 #define BRIDGE_DIRMAP_OFF (0x1ffff << 0) 1046 #define BRIDGE_DIRMAP_OFF_ADDRSHFT (31) /* lsbit of DIRMAP_OFF is xtalk address bit 31 */ 1047 1048 /* Bridge Arbitration register bits definition */ 1049 #define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16) 1050 #define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3) 1051 #define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8) 1052 #define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff) 1053 #define BRIDGE_ARB_FREEZE_GNT (1 << 6) 1054 #define BRIDGE_ARB_HPRI_RING_B2 (1 << 5) 1055 #define BRIDGE_ARB_HPRI_RING_B1 (1 << 4) 1056 #define BRIDGE_ARB_HPRI_RING_B0 (1 << 3) 1057 #define BRIDGE_ARB_LPRI_RING_B2 (1 << 2) 1058 #define BRIDGE_ARB_LPRI_RING_B1 (1 << 1) 1059 #define BRIDGE_ARB_LPRI_RING_B0 (1 << 0) 1060 1061 /* Bridge Bus time-out register bits definition */ 1062 #define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16) 1063 #define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f) 1064 #define BRIDGE_BUS_GIO_TIMEOUT (1 << 12) 1065 #define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0) 1066 #define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff) 1067 1068 /* Bridge interrupt status register bits definition */ 1069 #define PIC_ISR_PCIX_SPLIT_MSG_PE (0x1ull << 45) 1070 #define PIC_ISR_PCIX_SPLIT_EMSG (0x1ull << 44) 1071 #define PIC_ISR_PCIX_SPLIT_TO (0x1ull << 43) 1072 #define PIC_ISR_PCIX_UNEX_COMP (0x1ull << 42) 1073 #define PIC_ISR_INT_RAM_PERR (0x1ull << 41) 1074 #define PIC_ISR_PCIX_ARB_ERR (0x1ull << 40) 1075 #define PIC_ISR_PCIX_REQ_TOUT (0x1ull << 39) 1076 #define PIC_ISR_PCIX_TABORT (0x1ull << 38) 1077 #define PIC_ISR_PCIX_PERR (0x1ull << 37) 1078 #define PIC_ISR_PCIX_SERR (0x1ull << 36) 1079 #define PIC_ISR_PCIX_MRETRY (0x1ull << 35) 1080 #define PIC_ISR_PCIX_MTOUT (0x1ull << 34) 1081 #define PIC_ISR_PCIX_DA_PARITY (0x1ull << 33) 1082 #define PIC_ISR_PCIX_AD_PARITY (0x1ull << 32) 1083 #define BRIDGE_ISR_MULTI_ERR (0x1u << 31) /* bridge only */ 1084 #define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) /* bridge only */ 1085 #define BRIDGE_ISR_PAGE_FAULT (0x1 << 30) /* xbridge only */ 1086 #define BRIDGE_ISR_UNEXP_RESP (0x1 << 29) 1087 #define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28) 1088 #define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27) 1089 #define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26) 1090 #define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25) 1091 #define BRIDGE_ISR_INVLD_ADDR (0x1 << 24) 1092 #define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23) 1093 #define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22) 1094 #define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21) 1095 #define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20) 1096 #define BRIDGE_ISR_LLP_RCTY (0x1 << 19) 1097 #define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18) 1098 #define BRIDGE_ISR_LLP_TCTY (0x1 << 17) 1099 #define BRIDGE_ISR_SSRAM_PERR (0x1 << 16) 1100 #define BRIDGE_ISR_PCI_ABORT (0x1 << 15) 1101 #define BRIDGE_ISR_PCI_PARITY (0x1 << 14) 1102 #define BRIDGE_ISR_PCI_SERR (0x1 << 13) 1103 #define BRIDGE_ISR_PCI_PERR (0x1 << 12) 1104 #define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11) 1105 #define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT 1106 #define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10) 1107 #define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9) 1108 #define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8) 1109 #define BRIDGE_ISR_INT_MSK (0xff << 0) 1110 #define BRIDGE_ISR_INT(x) (0x1 << (x)) 1111 1112 #define BRIDGE_ISR_LINK_ERROR \ 1113 (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| \ 1114 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| \ 1115 BRIDGE_ISR_LLP_TCTY) 1116 1117 #define BRIDGE_ISR_PCIBUS_PIOERR \ 1118 (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT| \ 1119 PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT) 1120 1121 #define BRIDGE_ISR_PCIBUS_ERROR \ 1122 (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \ 1123 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \ 1124 BRIDGE_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR| \ 1125 PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY| \ 1126 PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY| \ 1127 PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP| \ 1128 PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG| \ 1129 PIC_ISR_PCIX_SPLIT_MSG_PE) 1130 1131 #define BRIDGE_ISR_XTALK_ERROR \ 1132 (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\ 1133 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| \ 1134 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| \ 1135 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| \ 1136 BRIDGE_ISR_UNEXP_RESP) 1137 1138 #define BRIDGE_ISR_ERRORS \ 1139 (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \ 1140 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ 1141 BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_INT_RAM_PERR) 1142 1143 /* 1144 * List of Errors which are fatal and kill the sytem 1145 */ 1146 #define BRIDGE_ISR_ERROR_FATAL \ 1147 ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\ 1148 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY| \ 1149 PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_AD_PARITY| \ 1150 PIC_ISR_PCIX_DA_PARITY| \ 1151 PIC_ISR_INT_RAM_PERR|PIC_ISR_PCIX_SPLIT_MSG_PE ) 1152 1153 #define BRIDGE_ISR_ERROR_DUMP \ 1154 (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \ 1155 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ 1156 PIC_ISR_PCIX_ARB_ERR|PIC_ISR_INT_RAM_PERR) 1157 1158 /* Bridge interrupt enable register bits definition */ 1159 #define PIC_IMR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE 1160 #define PIC_IMR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG 1161 #define PIC_IMR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO 1162 #define PIC_IMR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP 1163 #define PIC_IMR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR 1164 #define PIC_IMR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR 1165 #define PIC_IMR_PCIX_REQ_TOUR PIC_ISR_PCIX_REQ_TOUT 1166 #define PIC_IMR_PCIX_TABORT PIC_ISR_PCIX_TABORT 1167 #define PIC_IMR_PCIX_PERR PIC_ISR_PCIX_PERR 1168 #define PIC_IMR_PCIX_SERR PIC_ISR_PCIX_SERR 1169 #define PIC_IMR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY 1170 #define PIC_IMR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT 1171 #define PIC_IMR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY 1172 #define PIC_IMR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY 1173 #define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP 1174 #define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT 1175 #define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT 1176 #define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT 1177 #define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR 1178 #define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR 1179 #define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR 1180 #define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP 1181 #define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW 1182 #define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR 1183 #define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR 1184 #define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY 1185 #define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY 1186 #define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY 1187 #define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR 1188 #define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT 1189 #define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY 1190 #define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR 1191 #define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR 1192 #define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT 1193 #define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT 1194 #define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT 1195 #define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT 1196 #define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR 1197 #define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK 1198 #define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x) 1199 1200 /* 1201 * Bridge interrupt reset register bits definition. Note, PIC can 1202 * reset indiviual error interrupts, BRIDGE & XBRIDGE can only do 1203 * groups of them. 1204 */ 1205 #define PIC_IRR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE 1206 #define PIC_IRR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG 1207 #define PIC_IRR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO 1208 #define PIC_IRR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP 1209 #define PIC_IRR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR 1210 #define PIC_IRR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR 1211 #define PIC_IRR_PCIX_REQ_TOUT PIC_ISR_PCIX_REQ_TOUT 1212 #define PIC_IRR_PCIX_TABORT PIC_ISR_PCIX_TABORT 1213 #define PIC_IRR_PCIX_PERR PIC_ISR_PCIX_PERR 1214 #define PIC_IRR_PCIX_SERR PIC_ISR_PCIX_SERR 1215 #define PIC_IRR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY 1216 #define PIC_IRR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT 1217 #define PIC_IRR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY 1218 #define PIC_IRR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY 1219 #define PIC_IRR_PAGE_FAULT BRIDGE_ISR_PAGE_FAULT 1220 #define PIC_IRR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP 1221 #define PIC_IRR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT 1222 #define PIC_IRR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT 1223 #define PIC_IRR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR 1224 #define PIC_IRR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR 1225 #define PIC_IRR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR 1226 #define PIC_IRR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP 1227 #define PIC_IRR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW 1228 #define PIC_IRR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR 1229 #define PIC_IRR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR 1230 #define PIC_IRR_LLP_RCTY BRIDGE_ISR_LLP_RCTY 1231 #define PIC_IRR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY 1232 #define PIC_IRR_LLP_TCTY BRIDGE_ISR_LLP_TCTY 1233 #define PIC_IRR_PCI_ABORT BRIDGE_ISR_PCI_ABORT 1234 #define PIC_IRR_PCI_PARITY BRIDGE_ISR_PCI_PARITY 1235 #define PIC_IRR_PCI_SERR BRIDGE_ISR_PCI_SERR 1236 #define PIC_IRR_PCI_PERR BRIDGE_ISR_PCI_PERR 1237 #define PIC_IRR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT 1238 #define PIC_IRR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT 1239 #define PIC_IRR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT 1240 #define BRIDGE_IRR_MULTI_CLR (0x1 << 6) 1241 #define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5) 1242 #define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4) 1243 #define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3) 1244 #define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2) 1245 #define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1) 1246 #define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0) 1247 #define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0) 1248 #define BRIDGE_IRR_ALL_CLR 0x7f 1249 1250 #define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | \ 1251 BRIDGE_ISR_XREQ_FIFO_OFLOW) 1252 #define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | \ 1253 BRIDGE_ISR_RESP_XTLK_ERR | \ 1254 BRIDGE_ISR_XREAD_REQ_TIMEOUT) 1255 #define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | \ 1256 BRIDGE_ISR_BAD_XREQ_PKT | \ 1257 BRIDGE_ISR_REQ_XTLK_ERR | \ 1258 BRIDGE_ISR_INVLD_ADDR) 1259 #define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | \ 1260 BRIDGE_ISR_LLP_REC_CBERR | \ 1261 BRIDGE_ISR_LLP_RCTY | \ 1262 BRIDGE_ISR_LLP_TX_RETRY | \ 1263 BRIDGE_ISR_LLP_TCTY) 1264 #define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | \ 1265 BRIDGE_ISR_PMU_ESIZE_FAULT) 1266 #define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | \ 1267 BRIDGE_ISR_PCI_PARITY | \ 1268 BRIDGE_ISR_PCI_SERR | \ 1269 BRIDGE_ISR_PCI_PERR | \ 1270 BRIDGE_ISR_PCI_MST_TIMEOUT | \ 1271 BRIDGE_ISR_PCI_RETRY_CNT) 1272 1273 #define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \ 1274 BRIDGE_ISR_GIO_MST_TIMEOUT) 1275 1276 #define PIC_IRR_RAM_GRP PIC_ISR_INT_RAM_PERR 1277 1278 #define PIC_PCIX_GRP_CLR (PIC_IRR_PCIX_AD_PARITY | \ 1279 PIC_IRR_PCIX_DA_PARITY | \ 1280 PIC_IRR_PCIX_MTOUT | \ 1281 PIC_IRR_PCIX_MRETRY | \ 1282 PIC_IRR_PCIX_SERR | \ 1283 PIC_IRR_PCIX_PERR | \ 1284 PIC_IRR_PCIX_TABORT | \ 1285 PIC_ISR_PCIX_REQ_TOUT | \ 1286 PIC_ISR_PCIX_UNEX_COMP | \ 1287 PIC_ISR_PCIX_SPLIT_TO | \ 1288 PIC_ISR_PCIX_SPLIT_EMSG | \ 1289 PIC_ISR_PCIX_SPLIT_MSG_PE) 1290 1291 /* Bridge INT_DEV register bits definition */ 1292 #define BRIDGE_INT_DEV_SHFT(n) ((n)*3) 1293 #define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n)) 1294 #define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line)) 1295 1296 /* Bridge interrupt(x) register bits definition */ 1297 #define BRIDGE_INT_ADDR_HOST 0x0003FF00 1298 #define BRIDGE_INT_ADDR_FLD 0x000000FF 1299 1300 /* PIC interrupt(x) register bits definition */ 1301 #define PIC_INT_ADDR_FLD 0x00FF000000000000 1302 #define PIC_INT_ADDR_HOST 0x0000FFFFFFFFFFFF 1303 1304 #define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000 1305 #define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000 1306 #define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff 1307 1308 #define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff 1309 1310 /* Bridge device(x) register bits definition */ 1311 #define BRIDGE_DEV_ERR_LOCK_EN (1ull << 28) 1312 #define BRIDGE_DEV_PAGE_CHK_DIS (1ull << 27) 1313 #define BRIDGE_DEV_FORCE_PCI_PAR (1ull << 26) 1314 #define BRIDGE_DEV_VIRTUAL_EN (1ull << 25) 1315 #define BRIDGE_DEV_PMU_WRGA_EN (1ull << 24) 1316 #define BRIDGE_DEV_DIR_WRGA_EN (1ull << 23) 1317 #define BRIDGE_DEV_DEV_SIZE (1ull << 22) 1318 #define BRIDGE_DEV_RT (1ull << 21) 1319 #define BRIDGE_DEV_SWAP_PMU (1ull << 20) 1320 #define BRIDGE_DEV_SWAP_DIR (1ull << 19) 1321 #define BRIDGE_DEV_PREF (1ull << 18) 1322 #define BRIDGE_DEV_PRECISE (1ull << 17) 1323 #define BRIDGE_DEV_COH (1ull << 16) 1324 #define BRIDGE_DEV_BARRIER (1ull << 15) 1325 #define BRIDGE_DEV_GBR (1ull << 14) 1326 #define BRIDGE_DEV_DEV_SWAP (1ull << 13) 1327 #define BRIDGE_DEV_DEV_IO_MEM (1ull << 12) 1328 #define BRIDGE_DEV_OFF_MASK 0x00000fff 1329 #define BRIDGE_DEV_OFF_ADDR_SHFT 20 1330 1331 #define XBRIDGE_DEV_PMU_BITS BRIDGE_DEV_PMU_WRGA_EN 1332 #define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | \ 1333 BRIDGE_DEV_SWAP_PMU) 1334 #define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ 1335 BRIDGE_DEV_SWAP_DIR | \ 1336 BRIDGE_DEV_PREF | \ 1337 BRIDGE_DEV_PRECISE | \ 1338 BRIDGE_DEV_COH | \ 1339 BRIDGE_DEV_BARRIER) 1340 #define XBRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ 1341 BRIDGE_DEV_COH | \ 1342 BRIDGE_DEV_BARRIER) 1343 #define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ 1344 BRIDGE_DEV_SWAP_DIR | \ 1345 BRIDGE_DEV_COH | \ 1346 BRIDGE_DEV_BARRIER) 1347 1348 /* Bridge Error Upper register bit field definition */ 1349 #define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */ 1350 #define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */ 1351 #define BRIDGE_ERRUPPR_DEVNUM_SHFT (16) 1352 #define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT) 1353 #define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7) 1354 #define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF) 1355 1356 /* Bridge interrupt mode register bits definition */ 1357 #define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x)) 1358 1359 /* this should be written to the xbow's link_control(x) register */ 1360 #define BRIDGE_CREDIT 3 1361 1362 /* RRB assignment register */ 1363 #define BRIDGE_RRB_EN 0x8 /* after shifting down */ 1364 #define BRIDGE_RRB_DEV 0x7 /* after shifting down */ 1365 #define BRIDGE_RRB_VDEV 0x4 /* after shifting down, 2 virtual channels */ 1366 #define BRIDGE_RRB_PDEV 0x3 /* after shifting down, 8 devices */ 1367 1368 #define PIC_RRB_EN 0x8 /* after shifting down */ 1369 #define PIC_RRB_DEV 0x7 /* after shifting down */ 1370 #define PIC_RRB_VDEV 0x6 /* after shifting down, 4 virtual channels */ 1371 #define PIC_RRB_PDEV 0x1 /* after shifting down, 4 devices */ 1372 1373 /* RRB status register */ 1374 #define BRIDGE_RRB_VALID(r) (0x00010000<<(r)) 1375 #define BRIDGE_RRB_INUSE(r) (0x00000001<<(r)) 1376 1377 /* RRB clear register */ 1378 #define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r)) 1379 1380 /* Defines for the virtual channels so we don't hardcode 0-3 within code */ 1381 #define VCHAN0 0 /* virtual channel 0 (ie. the "normal" channel) */ 1382 #define VCHAN1 1 /* virtual channel 1 */ 1383 #define VCHAN2 2 /* virtual channel 2 - PIC only */ 1384 #define VCHAN3 3 /* virtual channel 3 - PIC only */ 1385 1386 /* PIC: PCI-X Read Buffer Attribute Register (RBAR) */ 1387 #define NUM_RBAR 16 /* number of RBAR registers */ 1388 1389 /* xbox system controller declarations */ 1390 #define XBOX_BRIDGE_WID 8 1391 #define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */ 1392 #define XBOX_RPS_EXISTS 1 << 6 /* RPS bit in status register */ 1393 #define XBOX_RPS_FAIL 1 << 4 /* RPS status bit in register */ 1394 1395 /* ======================================================================== 1396 */ 1397 /* 1398 * Macros for Xtalk to Bridge bus (PCI/GIO) PIO 1399 * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings 1400 */ 1401 /* XTALK addresses that map into Bridge Bus addr space */ 1402 #define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L 1403 #define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL 1404 #define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L 1405 #define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL 1406 #define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L 1407 #define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL 1408 1409 /* Ranges of PCI bus space that can be accessed via PIO from xtalk */ 1410 #define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */ 1411 #define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff 1412 #define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 /* 4G PCI IO space */ 1413 #define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff 1414 1415 /* XTALK addresses that map into PCI addresses */ 1416 #define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE 1417 #define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT 1418 #define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE 1419 #define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT 1420 #define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE 1421 #define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 1422 1423 /* 1424 * Macros for Xtalk to Bridge bus (PCI) PIO 1425 * refer to section 5.2.1 Figure 4 of the "PCI Interface Chip (PIC) Volume II 1426 * Programmer's Reference" (Revision 0.8 as of this writing). 1427 * 1428 * These are PIC bridge specific. A separate set of macros was defined 1429 * because PIC deviates from Bridge/Xbridge by not supporting a big-window 1430 * alias for PCI I/O space, and also redefines XTALK addresses 1431 * 0x0000C0000000L and 0x000100000000L to be PCI MEM aliases for the second 1432 * bus. 1433 */ 1434 1435 /* XTALK addresses that map into PIC Bridge Bus addr space */ 1436 #define PICBRIDGE0_PIO32_XTALK_ALIAS_BASE 0x000040000000L 1437 #define PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL 1438 #define PICBRIDGE0_PIO64_XTALK_ALIAS_BASE 0x000080000000L 1439 #define PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL 1440 #define PICBRIDGE1_PIO32_XTALK_ALIAS_BASE 0x0000C0000000L 1441 #define PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT 0x0000FFFFFFFFL 1442 #define PICBRIDGE1_PIO64_XTALK_ALIAS_BASE 0x000100000000L 1443 #define PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT 0x00013FFFFFFFL 1444 1445 /* XTALK addresses that map into PCI addresses */ 1446 #define PICBRIDGE0_PCI_MEM32_BASE PICBRIDGE0_PIO32_XTALK_ALIAS_BASE 1447 #define PICBRIDGE0_PCI_MEM32_LIMIT PICBRIDGE0_PIO32_XTALK_ALIAS_LIMIT 1448 #define PICBRIDGE0_PCI_MEM64_BASE PICBRIDGE0_PIO64_XTALK_ALIAS_BASE 1449 #define PICBRIDGE0_PCI_MEM64_LIMIT PICBRIDGE0_PIO64_XTALK_ALIAS_LIMIT 1450 #define PICBRIDGE1_PCI_MEM32_BASE PICBRIDGE1_PIO32_XTALK_ALIAS_BASE 1451 #define PICBRIDGE1_PCI_MEM32_LIMIT PICBRIDGE1_PIO32_XTALK_ALIAS_LIMIT 1452 #define PICBRIDGE1_PCI_MEM64_BASE PICBRIDGE1_PIO64_XTALK_ALIAS_BASE 1453 #define PICBRIDGE1_PCI_MEM64_LIMIT PICBRIDGE1_PIO64_XTALK_ALIAS_LIMIT 1454 1455 /* 1456 * Macros for Bridge bus (PCI/GIO) to Xtalk DMA 1457 */ 1458 /* Bridge Bus DMA addresses */ 1459 #define BRIDGE_LOCAL_BASE 0 1460 #define BRIDGE_DMA_MAPPED_BASE 0x40000000 1461 #define BRIDGE_DMA_MAPPED_SIZE 0x40000000 /* 1G Bytes */ 1462 #define BRIDGE_DMA_DIRECT_BASE 0x80000000 1463 #define BRIDGE_DMA_DIRECT_SIZE 0x80000000 /* 2G Bytes */ 1464 1465 #define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE 1466 1467 /* PCI addresses of regions decoded by Bridge for DMA */ 1468 #define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE 1469 #define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE 1470 1471 #ifndef __ASSEMBLY__ 1472 1473 #define IS_PCI32_LOCAL(x) ((uint64_t)(x) < PCI32_MAPPED_BASE) 1474 #define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \ 1475 (uint64_t)(x) >= PCI32_MAPPED_BASE) 1476 #define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE) 1477 #define IS_PCI64(x) ((uint64_t)(x) >= PCI64_BASE) 1478 #endif /* __ASSEMBLY__ */ 1479 1480 /* 1481 * The GIO address space. 1482 */ 1483 /* Xtalk to GIO PIO */ 1484 #define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE 1485 #define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT 1486 1487 #define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE 1488 1489 /* GIO addresses of regions decoded by Bridge for DMA */ 1490 #define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE 1491 #define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE 1492 1493 #ifndef __ASSEMBLY__ 1494 1495 #define IS_GIO_LOCAL(x) ((uint64_t)(x) < GIO_MAPPED_BASE) 1496 #define IS_GIO_MAPPED(x) ((uint64_t)(x) < GIO_DIRECT_BASE && \ 1497 (uint64_t)(x) >= GIO_MAPPED_BASE) 1498 #define IS_GIO_DIRECT(x) ((uint64_t)(x) >= GIO_MAPPED_BASE) 1499 #endif /* __ASSEMBLY__ */ 1500 1501 /* PCI to xtalk mapping */ 1502 1503 /* given a DIR_OFF value and a pci/gio 32 bits direct address, determine 1504 * which xtalk address is accessed 1505 */ 1506 #define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE 1507 #define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) \ 1508 ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \ 1509 ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE) 1510 1511 /* 64-bit address attribute masks */ 1512 #define PCI64_ATTR_TARG_MASK 0xf000000000000000 1513 #define PCI64_ATTR_TARG_SHFT 60 1514 #define PCI64_ATTR_PREF (1ull << 59) 1515 #define PCI64_ATTR_PREC (1ull << 58) 1516 #define PCI64_ATTR_VIRTUAL (1ull << 57) 1517 #define PCI64_ATTR_BAR (1ull << 56) 1518 #define PCI64_ATTR_SWAP (1ull << 55) 1519 #define PCI64_ATTR_RMF_MASK 0x00ff000000000000 1520 #define PCI64_ATTR_RMF_SHFT 48 1521 1522 #ifndef __ASSEMBLY__ 1523 /* Address translation entry for mapped pci32 accesses */ 1524 typedef union ate_u { 1525 uint64_t ent; 1526 struct xb_ate_s { /* xbridge */ 1527 uint64_t :16; 1528 uint64_t addr:36; 1529 uint64_t targ:4; 1530 uint64_t reserved:2; 1531 uint64_t swap:1; 1532 uint64_t barrier:1; 1533 uint64_t prefetch:1; 1534 uint64_t precise:1; 1535 uint64_t coherent:1; 1536 uint64_t valid:1; 1537 } xb_field; 1538 struct ate_s { /* bridge */ 1539 uint64_t rmf:16; 1540 uint64_t addr:36; 1541 uint64_t targ:4; 1542 uint64_t reserved:3; 1543 uint64_t barrier:1; 1544 uint64_t prefetch:1; 1545 uint64_t precise:1; 1546 uint64_t coherent:1; 1547 uint64_t valid:1; 1548 } field; 1549 } ate_t; 1550 #endif /* __ASSEMBLY__ */ 1551 1552 #define ATE_V (1 << 0) 1553 #define ATE_CO (1 << 1) 1554 #define ATE_PREC (1 << 2) 1555 #define ATE_PREF (1 << 3) 1556 #define ATE_BAR (1 << 4) 1557 #define ATE_SWAP (1 << 5) 1558 1559 #define ATE_PFNSHIFT 12 1560 #define ATE_TIDSHIFT 8 1561 #define ATE_RMFSHIFT 48 1562 1563 #define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \ 1564 ((xid)<<ATE_TIDSHIFT) | \ 1565 (attr) 1566 1567 /* 1568 * for xbridge, bit 29 of the pci address is the swap bit */ 1569 #define ATE_SWAPSHIFT 29 1570 #define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT)) 1571 #define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT)) 1572 1573 /* extern declarations */ 1574 1575 #ifndef __ASSEMBLY__ 1576 1577 /* ======================================================================== 1578 */ 1579 1580 #ifdef MACROFIELD_LINE 1581 /* 1582 * This table forms a relation between the byte offset macros normally 1583 * used for ASM coding and the calculated byte offsets of the fields 1584 * in the C structure. 1585 * 1586 * See bridge_check.c and bridge_html.c for further details. 1587 */ 1588 #ifndef MACROFIELD_LINE_BITFIELD 1589 #define MACROFIELD_LINE_BITFIELD(m) /* ignored */ 1590 #endif 1591 1592 struct macrofield_s bridge_macrofield[] = 1593 { 1594 1595 MACROFIELD_LINE(BRIDGE_WID_ID, b_wid_id) 1596 MACROFIELD_LINE_BITFIELD(WIDGET_REV_NUM) 1597 MACROFIELD_LINE_BITFIELD(WIDGET_PART_NUM) 1598 MACROFIELD_LINE_BITFIELD(WIDGET_MFG_NUM) 1599 MACROFIELD_LINE(BRIDGE_WID_STAT, b_wid_stat) 1600 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_REC_CNT) 1601 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_TX_CNT) 1602 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_FLASH_SELECT) 1603 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PCI_GIO_N) 1604 MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PENDING) 1605 MACROFIELD_LINE(BRIDGE_WID_ERR_UPPER, b_wid_err_upper) 1606 MACROFIELD_LINE(BRIDGE_WID_ERR_LOWER, b_wid_err_lower) 1607 MACROFIELD_LINE(BRIDGE_WID_CONTROL, b_wid_control) 1608 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_FLASH_WR_EN) 1609 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK50) 1610 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK40) 1611 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK33) 1612 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_RST_MASK) 1613 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_IO_SWAP) 1614 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MEM_SWAP) 1615 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_PAGE_SIZE) 1616 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_BAD) 1617 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_EN) 1618 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SSRAM_SIZE_MASK) 1619 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_F_BAD_PKT) 1620 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_LLP_XBAR_CRD_MASK) 1621 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_RLLP_CNT) 1622 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_TLLP_CNT) 1623 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SYS_END) 1624 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MAX_TRANS_MASK) 1625 MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_WIDGET_ID_MASK) 1626 MACROFIELD_LINE(BRIDGE_WID_REQ_TIMEOUT, b_wid_req_timeout) 1627 MACROFIELD_LINE(BRIDGE_WID_INT_UPPER, b_wid_int_upper) 1628 MACROFIELD_LINE_BITFIELD(WIDGET_INT_VECTOR) 1629 MACROFIELD_LINE_BITFIELD(WIDGET_TARGET_ID) 1630 MACROFIELD_LINE_BITFIELD(WIDGET_UPP_ADDR) 1631 MACROFIELD_LINE(BRIDGE_WID_INT_LOWER, b_wid_int_lower) 1632 MACROFIELD_LINE(BRIDGE_WID_ERR_CMDWORD, b_wid_err_cmdword) 1633 MACROFIELD_LINE_BITFIELD(WIDGET_DIDN) 1634 MACROFIELD_LINE_BITFIELD(WIDGET_SIDN) 1635 MACROFIELD_LINE_BITFIELD(WIDGET_PACTYP) 1636 MACROFIELD_LINE_BITFIELD(WIDGET_TNUM) 1637 MACROFIELD_LINE_BITFIELD(WIDGET_COHERENT) 1638 MACROFIELD_LINE_BITFIELD(WIDGET_DS) 1639 MACROFIELD_LINE_BITFIELD(WIDGET_GBR) 1640 MACROFIELD_LINE_BITFIELD(WIDGET_VBPM) 1641 MACROFIELD_LINE_BITFIELD(WIDGET_ERROR) 1642 MACROFIELD_LINE_BITFIELD(WIDGET_BARRIER) 1643 MACROFIELD_LINE(BRIDGE_WID_LLP, b_wid_llp) 1644 MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXRETRY) 1645 MACROFIELD_LINE_BITFIELD(WIDGET_LLP_NULLTIMEOUT) 1646 MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXBURST) 1647 MACROFIELD_LINE(BRIDGE_WID_TFLUSH, b_wid_tflush) 1648 MACROFIELD_LINE(BRIDGE_WID_AUX_ERR, b_wid_aux_err) 1649 MACROFIELD_LINE(BRIDGE_WID_RESP_UPPER, b_wid_resp_upper) 1650 MACROFIELD_LINE(BRIDGE_WID_RESP_LOWER, b_wid_resp_lower) 1651 MACROFIELD_LINE(BRIDGE_WID_TST_PIN_CTRL, b_wid_tst_pin_ctrl) 1652 MACROFIELD_LINE(BRIDGE_DIR_MAP, b_dir_map) 1653 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_W_ID) 1654 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_RMF_64) 1655 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_ADD512) 1656 MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_OFF) 1657 MACROFIELD_LINE(BRIDGE_RAM_PERR, b_ram_perr) 1658 MACROFIELD_LINE(BRIDGE_ARB, b_arb) 1659 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_TICK_MASK) 1660 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_EN_MASK) 1661 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_FREEZE_GNT) 1662 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B2) 1663 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B1) 1664 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B0) 1665 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B2) 1666 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B1) 1667 MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B0) 1668 MACROFIELD_LINE(BRIDGE_NIC, b_nic) 1669 MACROFIELD_LINE(BRIDGE_PCI_BUS_TIMEOUT, b_pci_bus_timeout) 1670 MACROFIELD_LINE(BRIDGE_PCI_CFG, b_pci_cfg) 1671 MACROFIELD_LINE(BRIDGE_PCI_ERR_UPPER, b_pci_err_upper) 1672 MACROFIELD_LINE(BRIDGE_PCI_ERR_LOWER, b_pci_err_lower) 1673 MACROFIELD_LINE(BRIDGE_INT_STATUS, b_int_status) 1674 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_MULTI_ERR) 1675 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PMU_ESIZE_FAULT) 1676 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNEXP_RESP) 1677 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XRESP_PKT) 1678 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XREQ_PKT) 1679 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_RESP_XTLK_ERR) 1680 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_REQ_XTLK_ERR) 1681 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INVLD_ADDR) 1682 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNSUPPORTED_XOP) 1683 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREQ_FIFO_OFLOW) 1684 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_SNERR) 1685 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_CBERR) 1686 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_RCTY) 1687 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TX_RETRY) 1688 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TCTY) 1689 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_SSRAM_PERR) 1690 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_ABORT) 1691 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PARITY) 1692 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_SERR) 1693 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PERR) 1694 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_MST_TIMEOUT) 1695 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_RETRY_CNT) 1696 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREAD_REQ_TIMEOUT) 1697 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_GIO_B_ENBL_ERR) 1698 MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INT_MSK) 1699 MACROFIELD_LINE(BRIDGE_INT_ENABLE, b_int_enable) 1700 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNEXP_RESP) 1701 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PMU_ESIZE_FAULT) 1702 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XRESP_PKT) 1703 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XREQ_PKT) 1704 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_RESP_XTLK_ERR) 1705 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_REQ_XTLK_ERR) 1706 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INVLD_ADDR) 1707 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNSUPPORTED_XOP) 1708 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREQ_FIFO_OFLOW) 1709 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_SNERR) 1710 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_CBERR) 1711 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_RCTY) 1712 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TX_RETRY) 1713 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TCTY) 1714 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_SSRAM_PERR) 1715 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_ABORT) 1716 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PARITY) 1717 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_SERR) 1718 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PERR) 1719 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_MST_TIMEOUT) 1720 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_RETRY_CNT) 1721 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREAD_REQ_TIMEOUT) 1722 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_GIO_B_ENBL_ERR) 1723 MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INT_MSK) 1724 MACROFIELD_LINE(BRIDGE_INT_RST_STAT, b_int_rst_stat) 1725 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_ALL_CLR) 1726 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_MULTI_CLR) 1727 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_CRP_GRP_CLR) 1728 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_RESP_BUF_GRP_CLR) 1729 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_REQ_DSP_GRP_CLR) 1730 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_LLP_GRP_CLR) 1731 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_SSRAM_GRP_CLR) 1732 MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_PCI_GRP_CLR) 1733 MACROFIELD_LINE(BRIDGE_INT_MODE, b_int_mode) 1734 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(7)) 1735 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(6)) 1736 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(5)) 1737 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(4)) 1738 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(3)) 1739 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(2)) 1740 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(1)) 1741 MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(0)) 1742 MACROFIELD_LINE(BRIDGE_INT_DEVICE, b_int_device) 1743 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(7)) 1744 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(6)) 1745 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(5)) 1746 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(4)) 1747 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(3)) 1748 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(2)) 1749 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(1)) 1750 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(0)) 1751 MACROFIELD_LINE(BRIDGE_INT_HOST_ERR, b_int_host_err) 1752 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_HOST) 1753 MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_FLD) 1754 MACROFIELD_LINE(BRIDGE_INT_ADDR0, b_int_addr[0].addr) 1755 MACROFIELD_LINE(BRIDGE_INT_ADDR(0), b_int_addr[0].addr) 1756 MACROFIELD_LINE(BRIDGE_INT_ADDR(1), b_int_addr[1].addr) 1757 MACROFIELD_LINE(BRIDGE_INT_ADDR(2), b_int_addr[2].addr) 1758 MACROFIELD_LINE(BRIDGE_INT_ADDR(3), b_int_addr[3].addr) 1759 MACROFIELD_LINE(BRIDGE_INT_ADDR(4), b_int_addr[4].addr) 1760 MACROFIELD_LINE(BRIDGE_INT_ADDR(5), b_int_addr[5].addr) 1761 MACROFIELD_LINE(BRIDGE_INT_ADDR(6), b_int_addr[6].addr) 1762 MACROFIELD_LINE(BRIDGE_INT_ADDR(7), b_int_addr[7].addr) 1763 MACROFIELD_LINE(BRIDGE_DEVICE0, b_device[0].reg) 1764 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_ERR_LOCK_EN) 1765 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PAGE_CHK_DIS) 1766 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_FORCE_PCI_PAR) 1767 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_VIRTUAL_EN) 1768 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PMU_WRGA_EN) 1769 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DIR_WRGA_EN) 1770 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SIZE) 1771 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_RT) 1772 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_PMU) 1773 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_DIR) 1774 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PREF) 1775 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PRECISE) 1776 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_COH) 1777 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_BARRIER) 1778 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_GBR) 1779 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SWAP) 1780 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_IO_MEM) 1781 MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_OFF_MASK) 1782 MACROFIELD_LINE(BRIDGE_DEVICE(0), b_device[0].reg) 1783 MACROFIELD_LINE(BRIDGE_DEVICE(1), b_device[1].reg) 1784 MACROFIELD_LINE(BRIDGE_DEVICE(2), b_device[2].reg) 1785 MACROFIELD_LINE(BRIDGE_DEVICE(3), b_device[3].reg) 1786 MACROFIELD_LINE(BRIDGE_DEVICE(4), b_device[4].reg) 1787 MACROFIELD_LINE(BRIDGE_DEVICE(5), b_device[5].reg) 1788 MACROFIELD_LINE(BRIDGE_DEVICE(6), b_device[6].reg) 1789 MACROFIELD_LINE(BRIDGE_DEVICE(7), b_device[7].reg) 1790 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF0, b_wr_req_buf[0].reg) 1791 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(0), b_wr_req_buf[0].reg) 1792 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(1), b_wr_req_buf[1].reg) 1793 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(2), b_wr_req_buf[2].reg) 1794 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(3), b_wr_req_buf[3].reg) 1795 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(4), b_wr_req_buf[4].reg) 1796 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(5), b_wr_req_buf[5].reg) 1797 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(6), b_wr_req_buf[6].reg) 1798 MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(7), b_wr_req_buf[7].reg) 1799 MACROFIELD_LINE(BRIDGE_EVEN_RESP, b_even_resp) 1800 MACROFIELD_LINE(BRIDGE_ODD_RESP, b_odd_resp) 1801 MACROFIELD_LINE(BRIDGE_RESP_STATUS, b_resp_status) 1802 MACROFIELD_LINE(BRIDGE_RESP_CLEAR, b_resp_clear) 1803 MACROFIELD_LINE(BRIDGE_ATE_RAM, b_int_ate_ram) 1804 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV0, b_type0_cfg_dev[0]) 1805 1806 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(0), b_type0_cfg_dev[0]) 1807 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,0), b_type0_cfg_dev[0].f[0]) 1808 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,1), b_type0_cfg_dev[0].f[1]) 1809 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,2), b_type0_cfg_dev[0].f[2]) 1810 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,3), b_type0_cfg_dev[0].f[3]) 1811 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,4), b_type0_cfg_dev[0].f[4]) 1812 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,5), b_type0_cfg_dev[0].f[5]) 1813 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,6), b_type0_cfg_dev[0].f[6]) 1814 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,7), b_type0_cfg_dev[0].f[7]) 1815 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(1), b_type0_cfg_dev[1]) 1816 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,0), b_type0_cfg_dev[1].f[0]) 1817 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,1), b_type0_cfg_dev[1].f[1]) 1818 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,2), b_type0_cfg_dev[1].f[2]) 1819 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,3), b_type0_cfg_dev[1].f[3]) 1820 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,4), b_type0_cfg_dev[1].f[4]) 1821 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,5), b_type0_cfg_dev[1].f[5]) 1822 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,6), b_type0_cfg_dev[1].f[6]) 1823 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,7), b_type0_cfg_dev[1].f[7]) 1824 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(2), b_type0_cfg_dev[2]) 1825 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,0), b_type0_cfg_dev[2].f[0]) 1826 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,1), b_type0_cfg_dev[2].f[1]) 1827 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,2), b_type0_cfg_dev[2].f[2]) 1828 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,3), b_type0_cfg_dev[2].f[3]) 1829 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,4), b_type0_cfg_dev[2].f[4]) 1830 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,5), b_type0_cfg_dev[2].f[5]) 1831 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,6), b_type0_cfg_dev[2].f[6]) 1832 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,7), b_type0_cfg_dev[2].f[7]) 1833 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(3), b_type0_cfg_dev[3]) 1834 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,0), b_type0_cfg_dev[3].f[0]) 1835 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,1), b_type0_cfg_dev[3].f[1]) 1836 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,2), b_type0_cfg_dev[3].f[2]) 1837 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,3), b_type0_cfg_dev[3].f[3]) 1838 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,4), b_type0_cfg_dev[3].f[4]) 1839 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,5), b_type0_cfg_dev[3].f[5]) 1840 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,6), b_type0_cfg_dev[3].f[6]) 1841 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,7), b_type0_cfg_dev[3].f[7]) 1842 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(4), b_type0_cfg_dev[4]) 1843 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,0), b_type0_cfg_dev[4].f[0]) 1844 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,1), b_type0_cfg_dev[4].f[1]) 1845 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,2), b_type0_cfg_dev[4].f[2]) 1846 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,3), b_type0_cfg_dev[4].f[3]) 1847 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,4), b_type0_cfg_dev[4].f[4]) 1848 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,5), b_type0_cfg_dev[4].f[5]) 1849 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,6), b_type0_cfg_dev[4].f[6]) 1850 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,7), b_type0_cfg_dev[4].f[7]) 1851 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(5), b_type0_cfg_dev[5]) 1852 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,0), b_type0_cfg_dev[5].f[0]) 1853 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,1), b_type0_cfg_dev[5].f[1]) 1854 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,2), b_type0_cfg_dev[5].f[2]) 1855 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,3), b_type0_cfg_dev[5].f[3]) 1856 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,4), b_type0_cfg_dev[5].f[4]) 1857 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,5), b_type0_cfg_dev[5].f[5]) 1858 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,6), b_type0_cfg_dev[5].f[6]) 1859 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,7), b_type0_cfg_dev[5].f[7]) 1860 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(6), b_type0_cfg_dev[6]) 1861 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,0), b_type0_cfg_dev[6].f[0]) 1862 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,1), b_type0_cfg_dev[6].f[1]) 1863 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,2), b_type0_cfg_dev[6].f[2]) 1864 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,3), b_type0_cfg_dev[6].f[3]) 1865 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,4), b_type0_cfg_dev[6].f[4]) 1866 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,5), b_type0_cfg_dev[6].f[5]) 1867 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,6), b_type0_cfg_dev[6].f[6]) 1868 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,7), b_type0_cfg_dev[6].f[7]) 1869 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(7), b_type0_cfg_dev[7]) 1870 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,0), b_type0_cfg_dev[7].f[0]) 1871 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,1), b_type0_cfg_dev[7].f[1]) 1872 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,2), b_type0_cfg_dev[7].f[2]) 1873 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,3), b_type0_cfg_dev[7].f[3]) 1874 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,4), b_type0_cfg_dev[7].f[4]) 1875 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,5), b_type0_cfg_dev[7].f[5]) 1876 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,6), b_type0_cfg_dev[7].f[6]) 1877 MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,7), b_type0_cfg_dev[7].f[7]) 1878 1879 MACROFIELD_LINE(BRIDGE_TYPE1_CFG, b_type1_cfg) 1880 MACROFIELD_LINE(BRIDGE_PCI_IACK, b_pci_iack) 1881 MACROFIELD_LINE(BRIDGE_EXT_SSRAM, b_ext_ate_ram) 1882 MACROFIELD_LINE(BRIDGE_DEVIO0, b_devio(0)) 1883 MACROFIELD_LINE(BRIDGE_DEVIO(0), b_devio(0)) 1884 MACROFIELD_LINE(BRIDGE_DEVIO(1), b_devio(1)) 1885 MACROFIELD_LINE(BRIDGE_DEVIO(2), b_devio(2)) 1886 MACROFIELD_LINE(BRIDGE_DEVIO(3), b_devio(3)) 1887 MACROFIELD_LINE(BRIDGE_DEVIO(4), b_devio(4)) 1888 MACROFIELD_LINE(BRIDGE_DEVIO(5), b_devio(5)) 1889 MACROFIELD_LINE(BRIDGE_DEVIO(6), b_devio(6)) 1890 MACROFIELD_LINE(BRIDGE_DEVIO(7), b_devio(7)) 1891 MACROFIELD_LINE(BRIDGE_EXTERNAL_FLASH, b_external_flash) 1892 }; 1893 #endif 1894 1895 #ifdef __cplusplus 1896 }; 1897 #endif 1898 #endif /* C or C++ */ 1899 1900 #endif /* _ASM_SN_PCI_BRIDGE_H */ 1901