1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #ifndef __MT76_CONNAC_MCU_H
5 #define __MT76_CONNAC_MCU_H
6
7 #include "mt76_connac.h"
8
9 #define FW_FEATURE_SET_ENCRYPT BIT(0)
10 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1)
11 #define FW_FEATURE_ENCRY_MODE BIT(4)
12 #define FW_FEATURE_OVERRIDE_ADDR BIT(5)
13 #define FW_FEATURE_NON_DL BIT(6)
14
15 #define DL_MODE_ENCRYPT BIT(0)
16 #define DL_MODE_KEY_IDX GENMASK(2, 1)
17 #define DL_MODE_RESET_SEC_IV BIT(3)
18 #define DL_MODE_WORKING_PDA_CR4 BIT(4)
19 #define DL_MODE_VALID_RAM_ENTRY BIT(5)
20 #define DL_CONFIG_ENCRY_MODE_SEL BIT(6)
21 #define DL_MODE_NEED_RSP BIT(31)
22
23 #define FW_START_OVERRIDE BIT(0)
24 #define FW_START_WORKING_PDA_CR4 BIT(2)
25 #define FW_START_WORKING_PDA_DSP BIT(3)
26
27 #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0)
28 #define PATCH_SEC_TYPE_MASK GENMASK(15, 0)
29 #define PATCH_SEC_TYPE_INFO 0x2
30
31 #define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24)
32 #define PATCH_SEC_ENC_TYPE_PLAIN 0x00
33 #define PATCH_SEC_ENC_TYPE_AES 0x01
34 #define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02
35 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0)
36 #define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0)
37
38 enum {
39 FW_TYPE_DEFAULT = 0,
40 FW_TYPE_CLC = 2,
41 FW_TYPE_MAX_NUM = 255
42 };
43
44 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
45 #define MCU_PKT_ID 0xa0
46
47 struct mt76_connac2_mcu_txd {
48 __le32 txd[8];
49
50 __le16 len;
51 __le16 pq_id;
52
53 u8 cid;
54 u8 pkt_type;
55 u8 set_query; /* FW don't care */
56 u8 seq;
57
58 u8 uc_d2b0_rev;
59 u8 ext_cid;
60 u8 s2d_index;
61 u8 ext_cid_ack;
62
63 u32 rsv[5];
64 } __packed __aligned(4);
65
66 /**
67 * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for connac2 and connac3
68 * @txd: hardware descriptor
69 * @len: total length not including txd
70 * @cid: command identifier
71 * @pkt_type: must be 0xa0 (cmd packet by long format)
72 * @frag_n: fragment number
73 * @seq: sequence number
74 * @checksum: 0 mean there is no checksum
75 * @s2d_index: index for command source and destination
76 * Definition | value | note
77 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM
78 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM
79 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA
80 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM
81 *
82 * @option: command option
83 * BIT[0]: UNI_CMD_OPT_BIT_ACK
84 * set to 1 to request a fw reply
85 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY
86 * is set, mcu firmware will send response event EID = 0x01
87 * (UNI_EVENT_ID_CMD_RESULT) to the host.
88 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD
89 * 0: original command
90 * 1: unified command
91 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY
92 * 0: QUERY command
93 * 1: SET command
94 */
95 struct mt76_connac2_mcu_uni_txd {
96 __le32 txd[8];
97
98 /* DW1 */
99 __le16 len;
100 __le16 cid;
101
102 /* DW2 */
103 u8 rsv;
104 u8 pkt_type;
105 u8 frag_n;
106 u8 seq;
107
108 /* DW3 */
109 __le16 checksum;
110 u8 s2d_index;
111 u8 option;
112
113 /* DW4 */
114 u8 rsv1[4];
115 } __packed __aligned(4);
116
117 struct mt76_connac2_mcu_rxd {
118 __le32 rxd[6];
119
120 __le16 len;
121 __le16 pkt_type_id;
122
123 u8 eid;
124 u8 seq;
125 u8 option;
126 u8 rsv;
127 u8 ext_eid;
128 u8 rsv1[2];
129 u8 s2d_index;
130
131 u8 tlv[];
132 };
133
134 struct mt76_connac2_patch_hdr {
135 char build_date[16];
136 char platform[4];
137 __be32 hw_sw_ver;
138 __be32 patch_ver;
139 __be16 checksum;
140 u16 rsv;
141 struct {
142 __be32 patch_ver;
143 __be32 subsys;
144 __be32 feature;
145 __be32 n_region;
146 __be32 crc;
147 u32 rsv[11];
148 } desc;
149 } __packed;
150
151 struct mt76_connac2_patch_sec {
152 __be32 type;
153 __be32 offs;
154 __be32 size;
155 union {
156 __be32 spec[13];
157 struct {
158 __be32 addr;
159 __be32 len;
160 __be32 sec_key_idx;
161 __be32 align_len;
162 u32 rsv[9];
163 } info;
164 };
165 } __packed;
166
167 struct mt76_connac2_fw_trailer {
168 u8 chip_id;
169 u8 eco_code;
170 u8 n_region;
171 u8 format_ver;
172 u8 format_flag;
173 u8 rsv[2];
174 char fw_ver[10];
175 char build_date[15];
176 __le32 crc;
177 } __packed;
178
179 struct mt76_connac2_fw_region {
180 __le32 decomp_crc;
181 __le32 decomp_len;
182 __le32 decomp_blk_sz;
183 u8 rsv[4];
184 __le32 addr;
185 __le32 len;
186 u8 feature_set;
187 u8 type;
188 u8 rsv1[14];
189 } __packed;
190
191 struct tlv {
192 __le16 tag;
193 __le16 len;
194 } __packed;
195
196 struct bss_info_omac {
197 __le16 tag;
198 __le16 len;
199 u8 hw_bss_idx;
200 u8 omac_idx;
201 u8 band_idx;
202 u8 rsv0;
203 __le32 conn_type;
204 u32 rsv1;
205 } __packed;
206
207 struct bss_info_basic {
208 __le16 tag;
209 __le16 len;
210 __le32 network_type;
211 u8 active;
212 u8 rsv0;
213 __le16 bcn_interval;
214 u8 bssid[ETH_ALEN];
215 u8 wmm_idx;
216 u8 dtim_period;
217 u8 bmc_wcid_lo;
218 u8 cipher;
219 u8 phy_mode;
220 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
221 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
222 u8 bmc_wcid_hi; /* high Byte and version */
223 u8 rsv[2];
224 } __packed;
225
226 struct bss_info_rf_ch {
227 __le16 tag;
228 __le16 len;
229 u8 pri_ch;
230 u8 center_ch0;
231 u8 center_ch1;
232 u8 bw;
233 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */
234 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */
235 u8 rsv[2];
236 } __packed;
237
238 struct bss_info_ext_bss {
239 __le16 tag;
240 __le16 len;
241 __le32 mbss_tsf_offset; /* in unit of us */
242 u8 rsv[8];
243 } __packed;
244
245 enum {
246 BSS_INFO_OMAC,
247 BSS_INFO_BASIC,
248 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
249 BSS_INFO_PM, /* sta only */
250 BSS_INFO_UAPSD, /* sta only */
251 BSS_INFO_ROAM_DETECT, /* obsoleted */
252 BSS_INFO_LQ_RM, /* obsoleted */
253 BSS_INFO_EXT_BSS,
254 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */
255 BSS_INFO_SYNC_MODE, /* obsoleted */
256 BSS_INFO_RA,
257 BSS_INFO_HW_AMSDU,
258 BSS_INFO_BSS_COLOR,
259 BSS_INFO_HE_BASIC,
260 BSS_INFO_PROTECT_INFO,
261 BSS_INFO_OFFLOAD,
262 BSS_INFO_11V_MBSSID,
263 BSS_INFO_MAX_NUM
264 };
265
266 /* sta_rec */
267
268 struct sta_ntlv_hdr {
269 u8 rsv[2];
270 __le16 tlv_num;
271 } __packed;
272
273 struct sta_req_hdr {
274 u8 bss_idx;
275 u8 wlan_idx_lo;
276 __le16 tlv_num;
277 u8 is_tlv_append;
278 u8 muar_idx;
279 u8 wlan_idx_hi;
280 u8 rsv;
281 } __packed;
282
283 struct sta_rec_basic {
284 __le16 tag;
285 __le16 len;
286 __le32 conn_type;
287 u8 conn_state;
288 u8 qos;
289 __le16 aid;
290 u8 peer_addr[ETH_ALEN];
291 #define EXTRA_INFO_VER BIT(0)
292 #define EXTRA_INFO_NEW BIT(1)
293 __le16 extra_info;
294 } __packed;
295
296 struct sta_rec_ht {
297 __le16 tag;
298 __le16 len;
299 __le16 ht_cap;
300 u16 rsv;
301 } __packed;
302
303 struct sta_rec_vht {
304 __le16 tag;
305 __le16 len;
306 __le32 vht_cap;
307 __le16 vht_rx_mcs_map;
308 __le16 vht_tx_mcs_map;
309 /* mt7915 - mt7921 */
310 u8 rts_bw_sig;
311 u8 rsv[3];
312 } __packed;
313
314 struct sta_rec_uapsd {
315 __le16 tag;
316 __le16 len;
317 u8 dac_map;
318 u8 tac_map;
319 u8 max_sp;
320 u8 rsv0;
321 __le16 listen_interval;
322 u8 rsv1[2];
323 } __packed;
324
325 struct sta_rec_ba {
326 __le16 tag;
327 __le16 len;
328 u8 tid;
329 u8 ba_type;
330 u8 amsdu;
331 u8 ba_en;
332 __le16 ssn;
333 __le16 winsize;
334 } __packed;
335
336 struct sta_rec_he {
337 __le16 tag;
338 __le16 len;
339
340 __le32 he_cap;
341
342 u8 t_frame_dur;
343 u8 max_ampdu_exp;
344 u8 bw_set;
345 u8 device_class;
346 u8 dcm_tx_mode;
347 u8 dcm_tx_max_nss;
348 u8 dcm_rx_mode;
349 u8 dcm_rx_max_nss;
350 u8 dcm_max_ru;
351 u8 punc_pream_rx;
352 u8 pkt_ext;
353 u8 rsv1;
354
355 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
356
357 u8 rsv2[2];
358 } __packed;
359
360 struct sta_rec_he_v2 {
361 __le16 tag;
362 __le16 len;
363 u8 he_mac_cap[6];
364 u8 he_phy_cap[11];
365 u8 pkt_ext;
366 /* 0: BW80, 1: BW160, 2: BW8080 */
367 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
368 } __packed;
369
370 struct sta_rec_amsdu {
371 __le16 tag;
372 __le16 len;
373 u8 max_amsdu_num;
374 u8 max_mpdu_size;
375 u8 amsdu_en;
376 u8 rsv;
377 } __packed;
378
379 struct sta_rec_state {
380 __le16 tag;
381 __le16 len;
382 __le32 flags;
383 u8 state;
384 u8 vht_opmode;
385 u8 action;
386 u8 rsv[1];
387 } __packed;
388
389 #define RA_LEGACY_OFDM GENMASK(13, 6)
390 #define RA_LEGACY_CCK GENMASK(3, 0)
391 #define HT_MCS_MASK_NUM 10
392 struct sta_rec_ra_info {
393 __le16 tag;
394 __le16 len;
395 __le16 legacy;
396 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
397 } __packed;
398
399 struct sta_rec_phy {
400 __le16 tag;
401 __le16 len;
402 __le16 basic_rate;
403 u8 phy_type;
404 u8 ampdu;
405 u8 rts_policy;
406 u8 rcpi;
407 u8 max_ampdu_len; /* connac3 */
408 u8 rsv[1];
409 } __packed;
410
411 struct sta_rec_he_6g_capa {
412 __le16 tag;
413 __le16 len;
414 __le16 capa;
415 u8 rsv[2];
416 } __packed;
417
418 struct sec_key {
419 u8 cipher_id;
420 u8 cipher_len;
421 u8 key_id;
422 u8 key_len;
423 u8 key[32];
424 } __packed;
425
426 struct sta_rec_sec {
427 __le16 tag;
428 __le16 len;
429 u8 add;
430 u8 n_cipher;
431 u8 rsv[2];
432
433 struct sec_key key[2];
434 } __packed;
435
436 struct sta_rec_bf {
437 __le16 tag;
438 __le16 len;
439
440 __le16 pfmu; /* 0xffff: no access right for PFMU */
441 bool su_mu; /* 0: SU, 1: MU */
442 u8 bf_cap; /* 0: iBF, 1: eBF */
443 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
444 u8 ndpa_rate;
445 u8 ndp_rate;
446 u8 rept_poll_rate;
447 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
448 u8 ncol;
449 u8 nrow;
450 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
451
452 u8 mem_total;
453 u8 mem_20m;
454 struct {
455 u8 row;
456 u8 col: 6, row_msb: 2;
457 } mem[4];
458
459 __le16 smart_ant;
460 u8 se_idx;
461 u8 auto_sounding; /* b7: low traffic indicator
462 * b6: Stop sounding for this entry
463 * b5 ~ b0: postpone sounding
464 */
465 u8 ibf_timeout;
466 u8 ibf_dbw;
467 u8 ibf_ncol;
468 u8 ibf_nrow;
469 u8 nrow_gt_bw80;
470 u8 ncol_gt_bw80;
471 u8 ru_start_idx;
472 u8 ru_end_idx;
473
474 bool trigger_su;
475 bool trigger_mu;
476 bool ng16_su;
477 bool ng16_mu;
478 bool codebook42_su;
479 bool codebook75_mu;
480
481 u8 he_ltf;
482 u8 rsv[3];
483 } __packed;
484
485 struct sta_rec_bfee {
486 __le16 tag;
487 __le16 len;
488 bool fb_identity_matrix; /* 1: feedback identity matrix */
489 bool ignore_feedback; /* 1: ignore */
490 u8 rsv[2];
491 } __packed;
492
493 struct sta_rec_muru {
494 __le16 tag;
495 __le16 len;
496
497 struct {
498 bool ofdma_dl_en;
499 bool ofdma_ul_en;
500 bool mimo_dl_en;
501 bool mimo_ul_en;
502 u8 rsv[4];
503 } cfg;
504
505 struct {
506 u8 punc_pream_rx;
507 bool he_20m_in_40m_2g;
508 bool he_20m_in_160m;
509 bool he_80m_in_160m;
510 bool lt16_sigb;
511 bool rx_su_comp_sigb;
512 bool rx_su_non_comp_sigb;
513 u8 rsv;
514 } ofdma_dl;
515
516 struct {
517 u8 t_frame_dur;
518 u8 mu_cascading;
519 u8 uo_ra;
520 u8 he_2x996_tone;
521 u8 rx_t_frame_11ac;
522 u8 rx_ctrl_frame_to_mbss;
523 u8 rsv[2];
524 } ofdma_ul;
525
526 struct {
527 bool vht_mu_bfee;
528 bool partial_bw_dl_mimo;
529 u8 rsv[2];
530 } mimo_dl;
531
532 struct {
533 bool full_ul_mimo;
534 bool partial_ul_mimo;
535 u8 rsv[2];
536 } mimo_ul;
537 } __packed;
538
539 struct sta_phy {
540 u8 type;
541 u8 flag;
542 u8 stbc;
543 u8 sgi;
544 u8 bw;
545 u8 ldpc;
546 u8 mcs;
547 u8 nss;
548 u8 he_ltf;
549 };
550
551 struct sta_rec_ra {
552 __le16 tag;
553 __le16 len;
554
555 u8 valid;
556 u8 auto_rate;
557 u8 phy_mode;
558 u8 channel;
559 u8 bw;
560 u8 disable_cck;
561 u8 ht_mcs32;
562 u8 ht_gf;
563 u8 ht_mcs[4];
564 u8 mmps_mode;
565 u8 gband_256;
566 u8 af;
567 u8 auth_wapi_mode;
568 u8 rate_len;
569
570 u8 supp_mode;
571 u8 supp_cck_rate;
572 u8 supp_ofdm_rate;
573 __le32 supp_ht_mcs;
574 __le16 supp_vht_mcs[4];
575
576 u8 op_mode;
577 u8 op_vht_chan_width;
578 u8 op_vht_rx_nss;
579 u8 op_vht_rx_nss_type;
580
581 __le32 sta_cap;
582
583 struct sta_phy phy;
584 } __packed;
585
586 struct sta_rec_ra_fixed {
587 __le16 tag;
588 __le16 len;
589
590 __le32 field;
591 u8 op_mode;
592 u8 op_vht_chan_width;
593 u8 op_vht_rx_nss;
594 u8 op_vht_rx_nss_type;
595
596 struct sta_phy phy;
597
598 u8 spe_idx;
599 u8 short_preamble;
600 u8 is_5g;
601 u8 mmps_mode;
602 } __packed;
603
604 /* wtbl_rec */
605
606 struct wtbl_req_hdr {
607 u8 wlan_idx_lo;
608 u8 operation;
609 __le16 tlv_num;
610 u8 wlan_idx_hi;
611 u8 rsv[3];
612 } __packed;
613
614 struct wtbl_generic {
615 __le16 tag;
616 __le16 len;
617 u8 peer_addr[ETH_ALEN];
618 u8 muar_idx;
619 u8 skip_tx;
620 u8 cf_ack;
621 u8 qos;
622 u8 mesh;
623 u8 adm;
624 __le16 partial_aid;
625 u8 baf_en;
626 u8 aad_om;
627 } __packed;
628
629 struct wtbl_rx {
630 __le16 tag;
631 __le16 len;
632 u8 rcid;
633 u8 rca1;
634 u8 rca2;
635 u8 rv;
636 u8 rsv[4];
637 } __packed;
638
639 struct wtbl_ht {
640 __le16 tag;
641 __le16 len;
642 u8 ht;
643 u8 ldpc;
644 u8 af;
645 u8 mm;
646 u8 rsv[4];
647 } __packed;
648
649 struct wtbl_vht {
650 __le16 tag;
651 __le16 len;
652 u8 ldpc;
653 u8 dyn_bw;
654 u8 vht;
655 u8 txop_ps;
656 u8 rsv[4];
657 } __packed;
658
659 struct wtbl_tx_ps {
660 __le16 tag;
661 __le16 len;
662 u8 txps;
663 u8 rsv[3];
664 } __packed;
665
666 struct wtbl_hdr_trans {
667 __le16 tag;
668 __le16 len;
669 u8 to_ds;
670 u8 from_ds;
671 u8 no_rx_trans;
672 u8 rsv;
673 } __packed;
674
675 struct wtbl_ba {
676 __le16 tag;
677 __le16 len;
678 /* common */
679 u8 tid;
680 u8 ba_type;
681 u8 rsv0[2];
682 /* originator only */
683 __le16 sn;
684 u8 ba_en;
685 u8 ba_winsize_idx;
686 /* originator & recipient */
687 __le16 ba_winsize;
688 /* recipient only */
689 u8 peer_addr[ETH_ALEN];
690 u8 rst_ba_tid;
691 u8 rst_ba_sel;
692 u8 rst_ba_sb;
693 u8 band_idx;
694 u8 rsv1[4];
695 } __packed;
696
697 struct wtbl_smps {
698 __le16 tag;
699 __le16 len;
700 u8 smps;
701 u8 rsv[3];
702 } __packed;
703
704 /* mt7615 only */
705
706 struct wtbl_bf {
707 __le16 tag;
708 __le16 len;
709 u8 ibf;
710 u8 ebf;
711 u8 ibf_vht;
712 u8 ebf_vht;
713 u8 gid;
714 u8 pfmu_idx;
715 u8 rsv[2];
716 } __packed;
717
718 struct wtbl_pn {
719 __le16 tag;
720 __le16 len;
721 u8 pn[6];
722 u8 rsv[2];
723 } __packed;
724
725 struct wtbl_spe {
726 __le16 tag;
727 __le16 len;
728 u8 spe_idx;
729 u8 rsv[3];
730 } __packed;
731
732 struct wtbl_raw {
733 __le16 tag;
734 __le16 len;
735 u8 wtbl_idx;
736 u8 dw;
737 u8 rsv[2];
738 __le32 msk;
739 __le32 val;
740 } __packed;
741
742 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
743 sizeof(struct wtbl_generic) + \
744 sizeof(struct wtbl_rx) + \
745 sizeof(struct wtbl_ht) + \
746 sizeof(struct wtbl_vht) + \
747 sizeof(struct wtbl_tx_ps) + \
748 sizeof(struct wtbl_hdr_trans) +\
749 sizeof(struct wtbl_ba) + \
750 sizeof(struct wtbl_bf) + \
751 sizeof(struct wtbl_smps) + \
752 sizeof(struct wtbl_pn) + \
753 sizeof(struct wtbl_spe))
754
755 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
756 sizeof(struct sta_rec_basic) + \
757 sizeof(struct sta_rec_bf) + \
758 sizeof(struct sta_rec_ht) + \
759 sizeof(struct sta_rec_he) + \
760 sizeof(struct sta_rec_ba) + \
761 sizeof(struct sta_rec_vht) + \
762 sizeof(struct sta_rec_uapsd) + \
763 sizeof(struct sta_rec_amsdu) + \
764 sizeof(struct sta_rec_muru) + \
765 sizeof(struct sta_rec_bfee) + \
766 sizeof(struct sta_rec_ra) + \
767 sizeof(struct sta_rec_sec) + \
768 sizeof(struct sta_rec_ra_fixed) + \
769 sizeof(struct sta_rec_he_6g_capa) + \
770 sizeof(struct tlv) + \
771 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
772
773 enum {
774 STA_REC_BASIC,
775 STA_REC_RA,
776 STA_REC_RA_CMM_INFO,
777 STA_REC_RA_UPDATE,
778 STA_REC_BF,
779 STA_REC_AMSDU,
780 STA_REC_BA,
781 STA_REC_STATE,
782 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
783 STA_REC_HT,
784 STA_REC_VHT,
785 STA_REC_APPS,
786 STA_REC_KEY,
787 STA_REC_WTBL,
788 STA_REC_HE,
789 STA_REC_HW_AMSDU,
790 STA_REC_WTBL_AADOM,
791 STA_REC_KEY_V2,
792 STA_REC_MURU,
793 STA_REC_MUEDCA,
794 STA_REC_BFEE,
795 STA_REC_PHY = 0x15,
796 STA_REC_HE_6G = 0x17,
797 STA_REC_HE_V2 = 0x19,
798 STA_REC_EHT = 0x22,
799 STA_REC_HDRT = 0x28,
800 STA_REC_HDR_TRANS = 0x2B,
801 STA_REC_MAX_NUM
802 };
803
804 enum {
805 WTBL_GENERIC,
806 WTBL_RX,
807 WTBL_HT,
808 WTBL_VHT,
809 WTBL_PEER_PS, /* not used */
810 WTBL_TX_PS,
811 WTBL_HDR_TRANS,
812 WTBL_SEC_KEY,
813 WTBL_BA,
814 WTBL_RDG, /* obsoleted */
815 WTBL_PROTECT, /* not used */
816 WTBL_CLEAR, /* not used */
817 WTBL_BF,
818 WTBL_SMPS,
819 WTBL_RAW_DATA, /* debug only */
820 WTBL_PN,
821 WTBL_SPE,
822 WTBL_MAX_NUM
823 };
824
825 #define STA_TYPE_STA BIT(0)
826 #define STA_TYPE_AP BIT(1)
827 #define STA_TYPE_ADHOC BIT(2)
828 #define STA_TYPE_WDS BIT(4)
829 #define STA_TYPE_BC BIT(5)
830
831 #define NETWORK_INFRA BIT(16)
832 #define NETWORK_P2P BIT(17)
833 #define NETWORK_IBSS BIT(18)
834 #define NETWORK_WDS BIT(21)
835
836 #define SCAN_FUNC_RANDOM_MAC BIT(0)
837 #define SCAN_FUNC_SPLIT_SCAN BIT(5)
838
839 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
840 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
841 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
842 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
843 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
844 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
845 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
846
847 #define CONN_STATE_DISCONNECT 0
848 #define CONN_STATE_CONNECT 1
849 #define CONN_STATE_PORT_SECURE 2
850
851 /* HE MAC */
852 #define STA_REC_HE_CAP_HTC BIT(0)
853 #define STA_REC_HE_CAP_BQR BIT(1)
854 #define STA_REC_HE_CAP_BSR BIT(2)
855 #define STA_REC_HE_CAP_OM BIT(3)
856 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
857 /* HE PHY */
858 #define STA_REC_HE_CAP_DUAL_BAND BIT(5)
859 #define STA_REC_HE_CAP_LDPC BIT(6)
860 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
861 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
862 /* STBC */
863 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
864 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
865 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
866 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
867 /* GI */
868 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
869 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
870 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
871 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
872 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
873 /* 242 TONE */
874 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
875 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
876 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
877
878 #define PHY_MODE_A BIT(0)
879 #define PHY_MODE_B BIT(1)
880 #define PHY_MODE_G BIT(2)
881 #define PHY_MODE_GN BIT(3)
882 #define PHY_MODE_AN BIT(4)
883 #define PHY_MODE_AC BIT(5)
884 #define PHY_MODE_AX_24G BIT(6)
885 #define PHY_MODE_AX_5G BIT(7)
886
887 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */
888 #define PHY_MODE_BE_24G BIT(1)
889 #define PHY_MODE_BE_5G BIT(2)
890 #define PHY_MODE_BE_6G BIT(3)
891
892 #define MODE_CCK BIT(0)
893 #define MODE_OFDM BIT(1)
894 #define MODE_HT BIT(2)
895 #define MODE_VHT BIT(3)
896 #define MODE_HE BIT(4)
897 #define MODE_EHT BIT(5)
898
899 #define STA_CAP_WMM BIT(0)
900 #define STA_CAP_SGI_20 BIT(4)
901 #define STA_CAP_SGI_40 BIT(5)
902 #define STA_CAP_TX_STBC BIT(6)
903 #define STA_CAP_RX_STBC BIT(7)
904 #define STA_CAP_VHT_SGI_80 BIT(16)
905 #define STA_CAP_VHT_SGI_160 BIT(17)
906 #define STA_CAP_VHT_TX_STBC BIT(18)
907 #define STA_CAP_VHT_RX_STBC BIT(19)
908 #define STA_CAP_VHT_LDPC BIT(23)
909 #define STA_CAP_LDPC BIT(24)
910 #define STA_CAP_HT BIT(26)
911 #define STA_CAP_VHT BIT(27)
912 #define STA_CAP_HE BIT(28)
913
914 enum {
915 PHY_TYPE_HR_DSSS_INDEX = 0,
916 PHY_TYPE_ERP_INDEX,
917 PHY_TYPE_ERP_P2P_INDEX,
918 PHY_TYPE_OFDM_INDEX,
919 PHY_TYPE_HT_INDEX,
920 PHY_TYPE_VHT_INDEX,
921 PHY_TYPE_HE_INDEX,
922 PHY_TYPE_INDEX_NUM
923 };
924
925 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX)
926 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX)
927 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX)
928 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX)
929 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX)
930 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX)
931
932 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6)
933 #define MT_WTBL_RATE_MCS GENMASK(5, 0)
934 #define MT_WTBL_RATE_NSS GENMASK(12, 10)
935 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4)
936 #define MT_WTBL_RATE_GI GENMASK(3, 0)
937
938 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
939 #define MT_WTBL_W5_SHORT_GI_20 BIT(8)
940 #define MT_WTBL_W5_SHORT_GI_40 BIT(9)
941 #define MT_WTBL_W5_SHORT_GI_80 BIT(10)
942 #define MT_WTBL_W5_SHORT_GI_160 BIT(11)
943 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
944 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
945 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
946 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
947
948 enum {
949 WTBL_RESET_AND_SET = 1,
950 WTBL_SET,
951 WTBL_QUERY,
952 WTBL_RESET_ALL
953 };
954
955 enum {
956 MT_BA_TYPE_INVALID,
957 MT_BA_TYPE_ORIGINATOR,
958 MT_BA_TYPE_RECIPIENT
959 };
960
961 enum {
962 RST_BA_MAC_TID_MATCH,
963 RST_BA_MAC_MATCH,
964 RST_BA_NO_MATCH
965 };
966
967 enum {
968 DEV_INFO_ACTIVE,
969 DEV_INFO_MAX_NUM
970 };
971
972 /* event table */
973 enum {
974 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
975 MCU_EVENT_FW_START = 0x01,
976 MCU_EVENT_GENERIC = 0x01,
977 MCU_EVENT_ACCESS_REG = 0x02,
978 MCU_EVENT_MT_PATCH_SEM = 0x04,
979 MCU_EVENT_REG_ACCESS = 0x05,
980 MCU_EVENT_LP_INFO = 0x07,
981 MCU_EVENT_SCAN_DONE = 0x0d,
982 MCU_EVENT_TX_DONE = 0x0f,
983 MCU_EVENT_ROC = 0x10,
984 MCU_EVENT_BSS_ABSENCE = 0x11,
985 MCU_EVENT_BSS_BEACON_LOSS = 0x13,
986 MCU_EVENT_CH_PRIVILEGE = 0x18,
987 MCU_EVENT_SCHED_SCAN_DONE = 0x23,
988 MCU_EVENT_DBG_MSG = 0x27,
989 MCU_EVENT_TXPWR = 0xd0,
990 MCU_EVENT_EXT = 0xed,
991 MCU_EVENT_RESTART_DL = 0xef,
992 MCU_EVENT_COREDUMP = 0xf0,
993 };
994
995 /* ext event table */
996 enum {
997 MCU_EXT_EVENT_PS_SYNC = 0x5,
998 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
999 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
1000 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
1001 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
1002 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
1003 MCU_EXT_EVENT_WA_TX_STAT = 0x74,
1004 MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
1005 MCU_EXT_EVENT_MURU_CTRL = 0x9f,
1006 };
1007
1008 /* unified event table */
1009 enum {
1010 MCU_UNI_EVENT_RESULT = 0x01,
1011 MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04,
1012 MCU_UNI_EVENT_IE_COUNTDOWN = 0x09,
1013 MCU_UNI_EVENT_RDD_REPORT = 0x11,
1014 };
1015
1016 #define MCU_UNI_CMD_EVENT BIT(1)
1017 #define MCU_UNI_CMD_UNSOLICITED_EVENT BIT(2)
1018
1019 enum {
1020 MCU_Q_QUERY,
1021 MCU_Q_SET,
1022 MCU_Q_RESERVED,
1023 MCU_Q_NA
1024 };
1025
1026 enum {
1027 MCU_S2D_H2N,
1028 MCU_S2D_C2N,
1029 MCU_S2D_H2C,
1030 MCU_S2D_H2CN
1031 };
1032
1033 enum {
1034 PATCH_NOT_DL_SEM_FAIL,
1035 PATCH_IS_DL,
1036 PATCH_NOT_DL_SEM_SUCCESS,
1037 PATCH_REL_SEM_SUCCESS
1038 };
1039
1040 enum {
1041 FW_STATE_INITIAL,
1042 FW_STATE_FW_DOWNLOAD,
1043 FW_STATE_NORMAL_OPERATION,
1044 FW_STATE_NORMAL_TRX,
1045 FW_STATE_RDY = 7
1046 };
1047
1048 enum {
1049 CH_SWITCH_NORMAL = 0,
1050 CH_SWITCH_SCAN = 3,
1051 CH_SWITCH_MCC = 4,
1052 CH_SWITCH_DFS = 5,
1053 CH_SWITCH_BACKGROUND_SCAN_START = 6,
1054 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1055 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1056 CH_SWITCH_SCAN_BYPASS_DPD = 9
1057 };
1058
1059 enum {
1060 THERMAL_SENSOR_TEMP_QUERY,
1061 THERMAL_SENSOR_MANUAL_CTRL,
1062 THERMAL_SENSOR_INFO_QUERY,
1063 THERMAL_SENSOR_TASK_CTRL,
1064 };
1065
1066 enum mcu_cipher_type {
1067 MCU_CIPHER_NONE = 0,
1068 MCU_CIPHER_WEP40,
1069 MCU_CIPHER_WEP104,
1070 MCU_CIPHER_WEP128,
1071 MCU_CIPHER_TKIP,
1072 MCU_CIPHER_AES_CCMP,
1073 MCU_CIPHER_CCMP_256,
1074 MCU_CIPHER_GCMP,
1075 MCU_CIPHER_GCMP_256,
1076 MCU_CIPHER_WAPI,
1077 MCU_CIPHER_BIP_CMAC_128,
1078 };
1079
1080 enum {
1081 EE_MODE_EFUSE,
1082 EE_MODE_BUFFER,
1083 };
1084
1085 enum {
1086 EE_FORMAT_BIN,
1087 EE_FORMAT_WHOLE,
1088 EE_FORMAT_MULTIPLE,
1089 };
1090
1091 enum {
1092 MCU_PHY_STATE_TX_RATE,
1093 MCU_PHY_STATE_RX_RATE,
1094 MCU_PHY_STATE_RSSI,
1095 MCU_PHY_STATE_CONTENTION_RX_RATE,
1096 MCU_PHY_STATE_OFDMLQ_CNINFO,
1097 };
1098
1099 #define MCU_CMD_ACK BIT(0)
1100 #define MCU_CMD_UNI BIT(1)
1101 #define MCU_CMD_SET BIT(2)
1102
1103 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \
1104 MCU_CMD_SET)
1105 #define MCU_CMD_UNI_QUERY_ACK (MCU_CMD_ACK | MCU_CMD_UNI)
1106
1107 #define __MCU_CMD_FIELD_ID GENMASK(7, 0)
1108 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8)
1109 #define __MCU_CMD_FIELD_QUERY BIT(16)
1110 #define __MCU_CMD_FIELD_UNI BIT(17)
1111 #define __MCU_CMD_FIELD_CE BIT(18)
1112 #define __MCU_CMD_FIELD_WA BIT(19)
1113 #define __MCU_CMD_FIELD_WM BIT(20)
1114
1115 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \
1116 MCU_CMD_##_t)
1117 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \
1118 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1119 MCU_EXT_CMD_##_t))
1120 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1121 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \
1122 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1123 MCU_UNI_CMD_##_t))
1124 #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \
1125 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1126 MCU_CE_CMD_##_t))
1127 #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1128
1129 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
1130 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
1131 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \
1132 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1133 MCU_WA_PARAM_CMD_##_t))
1134
1135 #define MCU_WM_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1136 __MCU_CMD_FIELD_WM)
1137 #define MCU_WM_UNI_CMD_QUERY(_t) (MCU_UNI_CMD(_t) | \
1138 __MCU_CMD_FIELD_QUERY | \
1139 __MCU_CMD_FIELD_WM)
1140 #define MCU_WA_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1141 __MCU_CMD_FIELD_WA)
1142 #define MCU_WMWA_UNI_CMD(_t) (MCU_WM_UNI_CMD(_t) | \
1143 __MCU_CMD_FIELD_WA)
1144
1145 enum {
1146 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
1147 MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
1148 MCU_EXT_CMD_RF_TEST = 0x04,
1149 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
1150 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
1151 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
1152 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
1153 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
1154 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
1155 MCU_EXT_CMD_THERMAL_PROT = 0x23,
1156 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
1157 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
1158 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
1159 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
1160 MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
1161 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
1162 MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
1163 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
1164 MCU_EXT_CMD_ATE_CTRL = 0x3d,
1165 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
1166 MCU_EXT_CMD_DBDC_CTRL = 0x45,
1167 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
1168 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
1169 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
1170 MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
1171 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a,
1172 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
1173 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f,
1174 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
1175 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
1176 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
1177 MCU_EXT_CMD_TXDPD_CAL = 0x60,
1178 MCU_EXT_CMD_CAL_CACHE = 0x67,
1179 MCU_EXT_CMD_RED_ENABLE = 0x68,
1180 MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
1181 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
1182 MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
1183 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
1184 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94,
1185 MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
1186 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
1187 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
1188 MCU_EXT_CMD_MURU_CTRL = 0x9f,
1189 MCU_EXT_CMD_SET_SPR = 0xa8,
1190 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
1191 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
1192 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
1193 };
1194
1195 enum {
1196 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01,
1197 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02,
1198 MCU_UNI_CMD_STA_REC_UPDATE = 0x03,
1199 MCU_UNI_CMD_EDCA_UPDATE = 0x04,
1200 MCU_UNI_CMD_SUSPEND = 0x05,
1201 MCU_UNI_CMD_OFFLOAD = 0x06,
1202 MCU_UNI_CMD_HIF_CTRL = 0x07,
1203 MCU_UNI_CMD_BAND_CONFIG = 0x08,
1204 MCU_UNI_CMD_REPT_MUAR = 0x09,
1205 MCU_UNI_CMD_WSYS_CONFIG = 0x0b,
1206 MCU_UNI_CMD_REG_ACCESS = 0x0d,
1207 MCU_UNI_CMD_CHIP_CONFIG = 0x0e,
1208 MCU_UNI_CMD_POWER_CTRL = 0x0f,
1209 MCU_UNI_CMD_RX_HDR_TRANS = 0x12,
1210 MCU_UNI_CMD_SER = 0x13,
1211 MCU_UNI_CMD_TWT = 0x14,
1212 MCU_UNI_CMD_RDD_CTRL = 0x19,
1213 MCU_UNI_CMD_GET_MIB_INFO = 0x22,
1214 MCU_UNI_CMD_SNIFFER = 0x24,
1215 MCU_UNI_CMD_SR = 0x25,
1216 MCU_UNI_CMD_ROC = 0x27,
1217 MCU_UNI_CMD_TXPOWER = 0x2b,
1218 MCU_UNI_CMD_EFUSE_CTRL = 0x2d,
1219 MCU_UNI_CMD_RA = 0x2f,
1220 MCU_UNI_CMD_MURU = 0x31,
1221 MCU_UNI_CMD_BF = 0x33,
1222 MCU_UNI_CMD_CHANNEL_SWITCH = 0x34,
1223 MCU_UNI_CMD_THERMAL = 0x35,
1224 MCU_UNI_CMD_VOW = 0x37,
1225 MCU_UNI_CMD_RRO = 0x57,
1226 MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58,
1227 MCU_UNI_CMD_ASSERT_DUMP = 0x6f,
1228 };
1229
1230 enum {
1231 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
1232 MCU_CMD_FW_START_REQ = 0x02,
1233 MCU_CMD_INIT_ACCESS_REG = 0x3,
1234 MCU_CMD_NIC_POWER_CTRL = 0x4,
1235 MCU_CMD_PATCH_START_REQ = 0x05,
1236 MCU_CMD_PATCH_FINISH_REQ = 0x07,
1237 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
1238 MCU_CMD_WA_PARAM = 0xc4,
1239 MCU_CMD_EXT_CID = 0xed,
1240 MCU_CMD_FW_SCATTER = 0xee,
1241 MCU_CMD_RESTART_DL_REQ = 0xef,
1242 };
1243
1244 /* offload mcu commands */
1245 enum {
1246 MCU_CE_CMD_TEST_CTRL = 0x01,
1247 MCU_CE_CMD_START_HW_SCAN = 0x03,
1248 MCU_CE_CMD_SET_PS_PROFILE = 0x05,
1249 MCU_CE_CMD_SET_RX_FILTER = 0x0a,
1250 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f,
1251 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16,
1252 MCU_CE_CMD_SET_BSS_ABORT = 0x17,
1253 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b,
1254 MCU_CE_CMD_SET_ROC = 0x1c,
1255 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d,
1256 MCU_CE_CMD_SET_P2P_OPPPS = 0x33,
1257 MCU_CE_CMD_SET_CLC = 0x5c,
1258 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d,
1259 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61,
1260 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62,
1261 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a,
1262 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0,
1263 MCU_CE_CMD_REG_WRITE = 0xc0,
1264 MCU_CE_CMD_REG_READ = 0xc0,
1265 MCU_CE_CMD_CHIP_CONFIG = 0xca,
1266 MCU_CE_CMD_FWLOG_2_HOST = 0xc5,
1267 MCU_CE_CMD_GET_WTBL = 0xcd,
1268 MCU_CE_CMD_GET_TXPWR = 0xd0,
1269 };
1270
1271 enum {
1272 PATCH_SEM_RELEASE,
1273 PATCH_SEM_GET
1274 };
1275
1276 enum {
1277 UNI_BSS_INFO_BASIC = 0,
1278 UNI_BSS_INFO_RA = 1,
1279 UNI_BSS_INFO_RLM = 2,
1280 UNI_BSS_INFO_BSS_COLOR = 4,
1281 UNI_BSS_INFO_HE_BASIC = 5,
1282 UNI_BSS_INFO_BCN_CONTENT = 7,
1283 UNI_BSS_INFO_BCN_CSA = 8,
1284 UNI_BSS_INFO_BCN_BCC = 9,
1285 UNI_BSS_INFO_BCN_MBSSID = 10,
1286 UNI_BSS_INFO_RATE = 11,
1287 UNI_BSS_INFO_QBSS = 15,
1288 UNI_BSS_INFO_SEC = 16,
1289 UNI_BSS_INFO_TXCMD = 18,
1290 UNI_BSS_INFO_UAPSD = 19,
1291 UNI_BSS_INFO_PS = 21,
1292 UNI_BSS_INFO_BCNFT = 22,
1293 UNI_BSS_INFO_IFS_TIME = 23,
1294 UNI_BSS_INFO_OFFLOAD = 25,
1295 UNI_BSS_INFO_MLD = 26,
1296 };
1297
1298 enum {
1299 UNI_OFFLOAD_OFFLOAD_ARP,
1300 UNI_OFFLOAD_OFFLOAD_ND,
1301 UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
1302 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
1303 };
1304
1305 enum {
1306 MT_NIC_CAP_TX_RESOURCE,
1307 MT_NIC_CAP_TX_EFUSE_ADDR,
1308 MT_NIC_CAP_COEX,
1309 MT_NIC_CAP_SINGLE_SKU,
1310 MT_NIC_CAP_CSUM_OFFLOAD,
1311 MT_NIC_CAP_HW_VER,
1312 MT_NIC_CAP_SW_VER,
1313 MT_NIC_CAP_MAC_ADDR,
1314 MT_NIC_CAP_PHY,
1315 MT_NIC_CAP_MAC,
1316 MT_NIC_CAP_FRAME_BUF,
1317 MT_NIC_CAP_BEAM_FORM,
1318 MT_NIC_CAP_LOCATION,
1319 MT_NIC_CAP_MUMIMO,
1320 MT_NIC_CAP_BUFFER_MODE_INFO,
1321 MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
1322 MT_NIC_CAP_ANTSWP = 0x16,
1323 MT_NIC_CAP_WFDMA_REALLOC,
1324 MT_NIC_CAP_6G,
1325 };
1326
1327 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0)
1328 #define UNI_WOW_DETECT_TYPE_ANY BIT(1)
1329 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2)
1330 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3)
1331 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4)
1332 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5)
1333 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6)
1334
1335 enum {
1336 UNI_SUSPEND_MODE_SETTING,
1337 UNI_SUSPEND_WOW_CTRL,
1338 UNI_SUSPEND_WOW_GPIO_PARAM,
1339 UNI_SUSPEND_WOW_WAKEUP_PORT,
1340 UNI_SUSPEND_WOW_PATTERN,
1341 };
1342
1343 enum {
1344 WOW_USB = 1,
1345 WOW_PCIE = 2,
1346 WOW_GPIO = 3,
1347 };
1348
1349 struct mt76_connac_bss_basic_tlv {
1350 __le16 tag;
1351 __le16 len;
1352 u8 active;
1353 u8 omac_idx;
1354 u8 hw_bss_idx;
1355 u8 band_idx;
1356 __le32 conn_type;
1357 u8 conn_state;
1358 u8 wmm_idx;
1359 u8 bssid[ETH_ALEN];
1360 __le16 bmc_tx_wlan_idx;
1361 __le16 bcn_interval;
1362 u8 dtim_period;
1363 u8 phymode; /* bit(0): A
1364 * bit(1): B
1365 * bit(2): G
1366 * bit(3): GN
1367 * bit(4): AN
1368 * bit(5): AC
1369 * bit(6): AX2
1370 * bit(7): AX5
1371 * bit(8): AX6
1372 */
1373 __le16 sta_idx;
1374 __le16 nonht_basic_phy;
1375 u8 phymode_ext; /* bit(0) AX_6G */
1376 u8 pad[1];
1377 } __packed;
1378
1379 struct mt76_connac_bss_qos_tlv {
1380 __le16 tag;
1381 __le16 len;
1382 u8 qos;
1383 u8 pad[3];
1384 } __packed;
1385
1386 struct mt76_connac_beacon_loss_event {
1387 u8 bss_idx;
1388 u8 reason;
1389 u8 pad[2];
1390 } __packed;
1391
1392 struct mt76_connac_mcu_bss_event {
1393 u8 bss_idx;
1394 u8 is_absent;
1395 u8 free_quota;
1396 u8 pad;
1397 } __packed;
1398
1399 struct mt76_connac_mcu_scan_ssid {
1400 __le32 ssid_len;
1401 u8 ssid[IEEE80211_MAX_SSID_LEN];
1402 } __packed;
1403
1404 struct mt76_connac_mcu_scan_channel {
1405 u8 band; /* 1: 2.4GHz
1406 * 2: 5.0GHz
1407 * Others: Reserved
1408 */
1409 u8 channel_num;
1410 } __packed;
1411
1412 struct mt76_connac_mcu_scan_match {
1413 __le32 rssi_th;
1414 u8 ssid[IEEE80211_MAX_SSID_LEN];
1415 u8 ssid_len;
1416 u8 rsv[3];
1417 } __packed;
1418
1419 struct mt76_connac_hw_scan_req {
1420 u8 seq_num;
1421 u8 bss_idx;
1422 u8 scan_type; /* 0: PASSIVE SCAN
1423 * 1: ACTIVE SCAN
1424 */
1425 u8 ssid_type; /* BIT(0) wildcard SSID
1426 * BIT(1) P2P wildcard SSID
1427 * BIT(2) specified SSID + wildcard SSID
1428 * BIT(2) + ssid_type_ext BIT(0) specified SSID only
1429 */
1430 u8 ssids_num;
1431 u8 probe_req_num; /* Number of probe request for each SSID */
1432 u8 scan_func; /* BIT(0) Enable random MAC scan
1433 * BIT(1) Disable DBDC scan type 1~3.
1434 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
1435 */
1436 u8 version; /* 0: Not support fields after ies.
1437 * 1: Support fields after ies.
1438 */
1439 struct mt76_connac_mcu_scan_ssid ssids[4];
1440 __le16 probe_delay_time;
1441 __le16 channel_dwell_time; /* channel Dwell interval */
1442 __le16 timeout_value;
1443 u8 channel_type; /* 0: Full channels
1444 * 1: Only 2.4GHz channels
1445 * 2: Only 5GHz channels
1446 * 3: P2P social channel only (channel #1, #6 and #11)
1447 * 4: Specified channels
1448 * Others: Reserved
1449 */
1450 u8 channels_num; /* valid when channel_type is 4 */
1451 /* valid when channels_num is set */
1452 struct mt76_connac_mcu_scan_channel channels[32];
1453 __le16 ies_len;
1454 u8 ies[MT76_CONNAC_SCAN_IE_LEN];
1455 /* following fields are valid if version > 0 */
1456 u8 ext_channels_num;
1457 u8 ext_ssids_num;
1458 __le16 channel_min_dwell_time;
1459 struct mt76_connac_mcu_scan_channel ext_channels[32];
1460 struct mt76_connac_mcu_scan_ssid ext_ssids[6];
1461 u8 bssid[ETH_ALEN];
1462 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
1463 u8 pad[63];
1464 u8 ssid_type_ext;
1465 } __packed;
1466
1467 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64
1468
1469 struct mt76_connac_hw_scan_done {
1470 u8 seq_num;
1471 u8 sparse_channel_num;
1472 struct mt76_connac_mcu_scan_channel sparse_channel;
1473 u8 complete_channel_num;
1474 u8 current_state;
1475 u8 version;
1476 u8 pad;
1477 __le32 beacon_scan_num;
1478 u8 pno_enabled;
1479 u8 pad2[3];
1480 u8 sparse_channel_valid_num;
1481 u8 pad3[3];
1482 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1483 /* idle format for channel_idle_time
1484 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
1485 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
1486 * 2: dwell time (16us)
1487 */
1488 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1489 /* beacon and probe response count */
1490 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1491 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1492 __le32 beacon_2g_num;
1493 __le32 beacon_5g_num;
1494 } __packed;
1495
1496 struct mt76_connac_sched_scan_req {
1497 u8 version;
1498 u8 seq_num;
1499 u8 stop_on_match;
1500 u8 ssids_num;
1501 u8 match_num;
1502 u8 pad;
1503 __le16 ie_len;
1504 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
1505 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
1506 u8 channel_type;
1507 u8 channels_num;
1508 u8 intervals_num;
1509 u8 scan_func; /* MT7663: BIT(0) eable random mac address */
1510 struct mt76_connac_mcu_scan_channel channels[64];
1511 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
1512 union {
1513 struct {
1514 u8 random_mac[ETH_ALEN];
1515 u8 pad2[58];
1516 } mt7663;
1517 struct {
1518 u8 bss_idx;
1519 u8 pad1[3];
1520 __le32 delay;
1521 u8 pad2[12];
1522 u8 random_mac[ETH_ALEN];
1523 u8 pad3[38];
1524 } mt7921;
1525 };
1526 } __packed;
1527
1528 struct mt76_connac_sched_scan_done {
1529 u8 seq_num;
1530 u8 status; /* 0: ssid found */
1531 __le16 pad;
1532 } __packed;
1533
1534 struct bss_info_uni_bss_color {
1535 __le16 tag;
1536 __le16 len;
1537 u8 enable;
1538 u8 bss_color;
1539 u8 rsv[2];
1540 } __packed;
1541
1542 struct bss_info_uni_he {
1543 __le16 tag;
1544 __le16 len;
1545 __le16 he_rts_thres;
1546 u8 he_pe_duration;
1547 u8 su_disable;
1548 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
1549 u8 rsv[2];
1550 } __packed;
1551
1552 struct mt76_connac_gtk_rekey_tlv {
1553 __le16 tag;
1554 __le16 len;
1555 u8 kek[NL80211_KEK_LEN];
1556 u8 kck[NL80211_KCK_LEN];
1557 u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
1558 u8 rekey_mode; /* 0: rekey offload enable
1559 * 1: rekey offload disable
1560 * 2: rekey update
1561 */
1562 u8 keyid;
1563 u8 option; /* 1: rekey data update without enabling offload */
1564 u8 pad[1];
1565 __le32 proto; /* WPA-RSN-WAPI-OPSN */
1566 __le32 pairwise_cipher;
1567 __le32 group_cipher;
1568 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
1569 __le32 mgmt_group_cipher;
1570 u8 reserverd[4];
1571 } __packed;
1572
1573 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16
1574 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128
1575
1576 struct mt76_connac_wow_pattern_tlv {
1577 __le16 tag;
1578 __le16 len;
1579 u8 index; /* pattern index */
1580 u8 enable; /* 0: disable
1581 * 1: enable
1582 */
1583 u8 data_len; /* pattern length */
1584 u8 pad;
1585 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
1586 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
1587 u8 rsv[4];
1588 } __packed;
1589
1590 struct mt76_connac_wow_ctrl_tlv {
1591 __le16 tag;
1592 __le16 len;
1593 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
1594 * 0x2: PM_WOWLAN_REQ_STOP
1595 * 0x3: PM_WOWLAN_PARAM_CLEAR
1596 */
1597 u8 trigger; /* 0: NONE
1598 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
1599 * BIT(1): NL80211_WOWLAN_TRIG_ANY
1600 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
1601 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
1602 * BIT(4): BEACON_LOST
1603 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
1604 */
1605 u8 wakeup_hif; /* 0x0: HIF_SDIO
1606 * 0x1: HIF_USB
1607 * 0x2: HIF_PCIE
1608 * 0x3: HIF_GPIO
1609 */
1610 u8 pad;
1611 u8 rsv[4];
1612 } __packed;
1613
1614 struct mt76_connac_wow_gpio_param_tlv {
1615 __le16 tag;
1616 __le16 len;
1617 u8 gpio_pin;
1618 u8 trigger_lvl;
1619 u8 pad[2];
1620 __le32 gpio_interval;
1621 u8 rsv[4];
1622 } __packed;
1623
1624 struct mt76_connac_arpns_tlv {
1625 __le16 tag;
1626 __le16 len;
1627 u8 mode;
1628 u8 ips_num;
1629 u8 option;
1630 u8 pad[1];
1631 } __packed;
1632
1633 struct mt76_connac_suspend_tlv {
1634 __le16 tag;
1635 __le16 len;
1636 u8 enable; /* 0: suspend mode disabled
1637 * 1: suspend mode enabled
1638 */
1639 u8 mdtim; /* LP parameter */
1640 u8 wow_suspend; /* 0: update by origin policy
1641 * 1: update by wow dtim
1642 */
1643 u8 pad[5];
1644 } __packed;
1645
1646 enum mt76_sta_info_state {
1647 MT76_STA_INFO_STATE_NONE,
1648 MT76_STA_INFO_STATE_AUTH,
1649 MT76_STA_INFO_STATE_ASSOC
1650 };
1651
1652 struct mt76_sta_cmd_info {
1653 struct ieee80211_sta *sta;
1654 struct mt76_wcid *wcid;
1655
1656 struct ieee80211_vif *vif;
1657
1658 bool offload_fw;
1659 bool enable;
1660 bool newly;
1661 int cmd;
1662 u8 rcpi;
1663 u8 state;
1664 };
1665
1666 #define MT_SKU_POWER_LIMIT 161
1667
1668 struct mt76_connac_sku_tlv {
1669 u8 channel;
1670 s8 pwr_limit[MT_SKU_POWER_LIMIT];
1671 } __packed;
1672
1673 struct mt76_connac_tx_power_limit_tlv {
1674 /* DW0 - common info*/
1675 u8 ver;
1676 u8 pad0;
1677 __le16 len;
1678 /* DW1 - cmd hint */
1679 u8 n_chan; /* # channel */
1680 u8 band; /* 2.4GHz - 5GHz - 6GHz */
1681 u8 last_msg;
1682 u8 pad1;
1683 /* DW3 */
1684 u8 alpha2[4]; /* regulatory_request.alpha2 */
1685 u8 pad2[32];
1686 } __packed;
1687
1688 struct mt76_connac_config {
1689 __le16 id;
1690 u8 type;
1691 u8 resp_type;
1692 __le16 data_size;
1693 __le16 resv;
1694 u8 data[320];
1695 } __packed;
1696
1697 struct mt76_connac_mcu_uni_event {
1698 u8 cid;
1699 u8 pad[3];
1700 __le32 status; /* 0: success, others: fail */
1701 } __packed;
1702
1703 struct mt76_connac_mcu_reg_event {
1704 __le32 reg;
1705 __le32 val;
1706 } __packed;
1707
1708 static inline enum mcu_cipher_type
mt76_connac_mcu_get_cipher(int cipher)1709 mt76_connac_mcu_get_cipher(int cipher)
1710 {
1711 switch (cipher) {
1712 case WLAN_CIPHER_SUITE_WEP40:
1713 return MCU_CIPHER_WEP40;
1714 case WLAN_CIPHER_SUITE_WEP104:
1715 return MCU_CIPHER_WEP104;
1716 case WLAN_CIPHER_SUITE_TKIP:
1717 return MCU_CIPHER_TKIP;
1718 case WLAN_CIPHER_SUITE_AES_CMAC:
1719 return MCU_CIPHER_BIP_CMAC_128;
1720 case WLAN_CIPHER_SUITE_CCMP:
1721 return MCU_CIPHER_AES_CCMP;
1722 case WLAN_CIPHER_SUITE_CCMP_256:
1723 return MCU_CIPHER_CCMP_256;
1724 case WLAN_CIPHER_SUITE_GCMP:
1725 return MCU_CIPHER_GCMP;
1726 case WLAN_CIPHER_SUITE_GCMP_256:
1727 return MCU_CIPHER_GCMP_256;
1728 case WLAN_CIPHER_SUITE_SMS4:
1729 return MCU_CIPHER_WAPI;
1730 default:
1731 return MCU_CIPHER_NONE;
1732 }
1733 }
1734
1735 static inline u32
mt76_connac_mcu_gen_dl_mode(struct mt76_dev * dev,u8 feature_set,bool is_wa)1736 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa)
1737 {
1738 u32 ret = 0;
1739
1740 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ?
1741 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0;
1742 if (is_mt7921(dev))
1743 ret |= feature_set & FW_FEATURE_ENCRY_MODE ?
1744 DL_CONFIG_ENCRY_MODE_SEL : 0;
1745 ret |= FIELD_PREP(DL_MODE_KEY_IDX,
1746 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set));
1747 ret |= DL_MODE_NEED_RSP;
1748 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0;
1749
1750 return ret;
1751 }
1752
1753 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1754 #define to_wcid_hi(id) FIELD_GET(GENMASK(10, 8), (u16)id)
1755
1756 static inline void
mt76_connac_mcu_get_wlan_idx(struct mt76_dev * dev,struct mt76_wcid * wcid,u8 * wlan_idx_lo,u8 * wlan_idx_hi)1757 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1758 u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1759 {
1760 *wlan_idx_hi = 0;
1761
1762 if (!is_connac_v1(dev)) {
1763 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1764 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1765 } else {
1766 *wlan_idx_lo = wcid ? wcid->idx : 0;
1767 }
1768 }
1769
1770 struct sk_buff *
1771 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1772 struct mt76_wcid *wcid, int len);
1773 static inline struct sk_buff *
mt76_connac_mcu_alloc_sta_req(struct mt76_dev * dev,struct mt76_vif * mvif,struct mt76_wcid * wcid)1774 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1775 struct mt76_wcid *wcid)
1776 {
1777 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid,
1778 MT76_CONNAC_STA_UPDATE_MAX_SIZE);
1779 }
1780
1781 struct wtbl_req_hdr *
1782 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1783 int cmd, void *sta_wtbl, struct sk_buff **skb);
1784 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1785 int len, void *sta_ntlv,
1786 void *sta_wtbl);
1787 static inline struct tlv *
mt76_connac_mcu_add_tlv(struct sk_buff * skb,int tag,int len)1788 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1789 {
1790 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1791 }
1792
1793 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
1794 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
1795 void mt76_connac_mcu_sta_basic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1796 struct ieee80211_vif *vif,
1797 struct ieee80211_sta *sta, bool enable,
1798 bool newly);
1799 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1800 struct ieee80211_vif *vif,
1801 struct ieee80211_sta *sta, void *sta_wtbl,
1802 void *wtbl_tlv);
1803 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
1804 struct ieee80211_vif *vif,
1805 struct mt76_wcid *wcid,
1806 void *sta_wtbl, void *wtbl_tlv);
1807 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
1808 struct ieee80211_vif *vif,
1809 struct mt76_wcid *wcid, int cmd);
1810 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev,
1811 struct ieee80211_vif *vif,
1812 struct ieee80211_sta *sta);
1813 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
1814 struct ieee80211_sta *sta,
1815 struct ieee80211_vif *vif,
1816 u8 rcpi, u8 state);
1817 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1818 struct ieee80211_sta *sta, void *sta_wtbl,
1819 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc);
1820 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1821 struct ieee80211_ampdu_params *params,
1822 bool enable, bool tx, void *sta_wtbl,
1823 void *wtbl_tlv);
1824 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
1825 struct ieee80211_ampdu_params *params,
1826 bool enable, bool tx);
1827 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
1828 struct ieee80211_vif *vif,
1829 struct mt76_wcid *wcid,
1830 bool enable);
1831 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
1832 struct ieee80211_ampdu_params *params,
1833 int cmd, bool enable, bool tx);
1834 int mt76_connac_mcu_uni_set_chctx(struct mt76_phy *phy,
1835 struct mt76_vif *vif,
1836 struct ieee80211_chanctx_conf *ctx);
1837 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
1838 struct ieee80211_vif *vif,
1839 struct mt76_wcid *wcid,
1840 bool enable,
1841 struct ieee80211_chanctx_conf *ctx);
1842 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
1843 struct mt76_sta_cmd_info *info);
1844 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
1845 struct ieee80211_vif *vif);
1846 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
1847 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
1848 bool hdr_trans);
1849 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
1850 u32 mode);
1851 int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
1852 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
1853 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
1854 int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy);
1855
1856 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
1857 struct ieee80211_scan_request *scan_req);
1858 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
1859 struct ieee80211_vif *vif);
1860 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
1861 struct ieee80211_vif *vif,
1862 struct cfg80211_sched_scan_request *sreq);
1863 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
1864 struct ieee80211_vif *vif,
1865 bool enable);
1866 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
1867 struct mt76_vif *vif,
1868 struct ieee80211_bss_conf *info);
1869 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
1870 struct ieee80211_vif *vif,
1871 struct cfg80211_gtk_rekey_data *key);
1872 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend);
1873 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
1874 struct ieee80211_vif *vif);
1875 int mt76_connac_sta_state_dp(struct mt76_dev *dev,
1876 enum ieee80211_sta_state old_state,
1877 enum ieee80211_sta_state new_state);
1878 int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
1879 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
1880 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
1881 struct mt76_connac_coredump *coredump);
1882 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
1883 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
1884 struct ieee80211_vif *vif);
1885 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
1886 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
1887
1888 const struct ieee80211_sta_he_cap *
1889 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
1890 const struct ieee80211_sta_eht_cap *
1891 mt76_connac_get_eht_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
1892 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif,
1893 enum nl80211_band band, struct ieee80211_sta *sta);
1894 u8 mt76_connac_get_phy_mode_ext(struct mt76_phy *phy, struct ieee80211_vif *vif,
1895 enum nl80211_band band);
1896
1897 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
1898 struct mt76_connac_sta_key_conf *sta_key_conf,
1899 struct ieee80211_key_conf *key, int mcu_cmd,
1900 struct mt76_wcid *wcid, enum set_key_cmd cmd);
1901
1902 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif);
1903 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb,
1904 struct ieee80211_vif *vif);
1905 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
1906 struct ieee80211_vif *vif,
1907 struct ieee80211_sta *sta,
1908 struct mt76_phy *phy, u16 wlan_idx,
1909 bool enable);
1910 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif,
1911 struct ieee80211_sta *sta);
1912 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb,
1913 struct ieee80211_sta *sta,
1914 void *sta_wtbl, void *wtbl_tlv);
1915 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter);
1916 int mt76_connac_mcu_restart(struct mt76_dev *dev);
1917 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index,
1918 u8 rx_sel, u8 val);
1919 int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb);
1920 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm,
1921 const char *fw_wa);
1922 int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name);
1923 int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
1924 int cmd, int *wait_seq);
1925 #endif /* __MT76_CONNAC_MCU_H */
1926