1 /****************************************************************************** 2 * 3 * Name: xmac_ii.h 4 * Project: Gigabit Ethernet Adapters, Common Modules 5 * Purpose: Defines and Macros for Gigabit Ethernet Controller 6 * 7 ******************************************************************************/ 8 9 /****************************************************************************** 10 * 11 * (C)Copyright 1998-2002 SysKonnect. 12 * (C)Copyright 2002-2003 Marvell. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * The information in this file is provided "AS IS" without warranty. 20 * 21 ******************************************************************************/ 22 23 #ifndef __INC_XMAC_H 24 #define __INC_XMAC_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif /* __cplusplus */ 29 30 /* defines ********************************************************************/ 31 32 /* 33 * XMAC II registers 34 * 35 * The XMAC registers are 16 or 32 bits wide. 36 * The XMACs host processor interface is set to 16 bit mode, 37 * therefore ALL registers will be addressed with 16 bit accesses. 38 * 39 * The following macros are provided to access the XMAC registers 40 * XM_IN16(), XM_OUT16, XM_IN32(), XM_OUT32(), XM_INADR(), XM_OUTADR(), 41 * XM_INHASH(), and XM_OUTHASH(). 42 * The macros are defined in SkGeHw.h. 43 * 44 * Note: NA reg = Network Address e.g DA, SA etc. 45 * 46 */ 47 #define XM_MMU_CMD 0x0000 /* 16 bit r/w MMU Command Register */ 48 /* 0x0004: reserved */ 49 #define XM_POFF 0x0008 /* 32 bit r/w Packet Offset Register */ 50 #define XM_BURST 0x000c /* 32 bit r/w Burst Register for half duplex*/ 51 #define XM_1L_VLAN_TAG 0x0010 /* 16 bit r/w One Level VLAN Tag ID */ 52 #define XM_2L_VLAN_TAG 0x0014 /* 16 bit r/w Two Level VLAN Tag ID */ 53 /* 0x0018 - 0x001e: reserved */ 54 #define XM_TX_CMD 0x0020 /* 16 bit r/w Transmit Command Register */ 55 #define XM_TX_RT_LIM 0x0024 /* 16 bit r/w Transmit Retry Limit Register */ 56 #define XM_TX_STIME 0x0028 /* 16 bit r/w Transmit Slottime Register */ 57 #define XM_TX_IPG 0x002c /* 16 bit r/w Transmit Inter Packet Gap */ 58 #define XM_RX_CMD 0x0030 /* 16 bit r/w Receive Command Register */ 59 #define XM_PHY_ADDR 0x0034 /* 16 bit r/w PHY Address Register */ 60 #define XM_PHY_DATA 0x0038 /* 16 bit r/w PHY Data Register */ 61 /* 0x003c: reserved */ 62 #define XM_GP_PORT 0x0040 /* 32 bit r/w General Purpose Port Register */ 63 #define XM_IMSK 0x0044 /* 16 bit r/w Interrupt Mask Register */ 64 #define XM_ISRC 0x0048 /* 16 bit r/o Interrupt Status Register */ 65 #define XM_HW_CFG 0x004c /* 16 bit r/w Hardware Config Register */ 66 /* 0x0050 - 0x005e: reserved */ 67 #define XM_TX_LO_WM 0x0060 /* 16 bit r/w Tx FIFO Low Water Mark */ 68 #define XM_TX_HI_WM 0x0062 /* 16 bit r/w Tx FIFO High Water Mark */ 69 #define XM_TX_THR 0x0064 /* 16 bit r/w Tx Request Threshold */ 70 #define XM_HT_THR 0x0066 /* 16 bit r/w Host Request Threshold */ 71 #define XM_PAUSE_DA 0x0068 /* NA reg r/w Pause Destination Address */ 72 /* 0x006e: reserved */ 73 #define XM_CTL_PARA 0x0070 /* 32 bit r/w Control Parameter Register */ 74 #define XM_MAC_OPCODE 0x0074 /* 16 bit r/w Opcode for MAC control frames */ 75 #define XM_MAC_PTIME 0x0076 /* 16 bit r/w Pause time for MAC ctrl frames*/ 76 #define XM_TX_STAT 0x0078 /* 32 bit r/o Tx Status LIFO Register */ 77 78 /* 0x0080 - 0x00fc: 16 NA reg r/w Exact Match Address Registers */ 79 /* use the XM_EXM() macro to address */ 80 #define XM_EXM_START 0x0080 /* r/w Start Address of the EXM Regs */ 81 82 /* 83 * XM_EXM(Reg) 84 * 85 * returns the XMAC address offset of specified Exact Match Addr Reg 86 * 87 * para: Reg EXM register to addr (0 .. 15) 88 * 89 * usage: XM_INADDR(IoC, MAC_1, XM_EXM(i), &val[i]); 90 */ 91 #define XM_EXM(Reg) (XM_EXM_START + ((Reg) << 3)) 92 93 #define XM_SRC_CHK 0x0100 /* NA reg r/w Source Check Address Register */ 94 #define XM_SA 0x0108 /* NA reg r/w Station Address Register */ 95 #define XM_HSM 0x0110 /* 64 bit r/w Hash Match Address Registers */ 96 #define XM_RX_LO_WM 0x0118 /* 16 bit r/w Receive Low Water Mark */ 97 #define XM_RX_HI_WM 0x011a /* 16 bit r/w Receive High Water Mark */ 98 #define XM_RX_THR 0x011c /* 32 bit r/w Receive Request Threshold */ 99 #define XM_DEV_ID 0x0120 /* 32 bit r/o Device ID Register */ 100 #define XM_MODE 0x0124 /* 32 bit r/w Mode Register */ 101 #define XM_LSA 0x0128 /* NA reg r/o Last Source Register */ 102 /* 0x012e: reserved */ 103 #define XM_TS_READ 0x0130 /* 32 bit r/o Time Stamp Read Register */ 104 #define XM_TS_LOAD 0x0134 /* 32 bit r/o Time Stamp Load Value */ 105 /* 0x0138 - 0x01fe: reserved */ 106 #define XM_STAT_CMD 0x0200 /* 16 bit r/w Statistics Command Register */ 107 #define XM_RX_CNT_EV 0x0204 /* 32 bit r/o Rx Counter Event Register */ 108 #define XM_TX_CNT_EV 0x0208 /* 32 bit r/o Tx Counter Event Register */ 109 #define XM_RX_EV_MSK 0x020c /* 32 bit r/w Rx Counter Event Mask */ 110 #define XM_TX_EV_MSK 0x0210 /* 32 bit r/w Tx Counter Event Mask */ 111 /* 0x0204 - 0x027e: reserved */ 112 #define XM_TXF_OK 0x0280 /* 32 bit r/o Frames Transmitted OK Conuter */ 113 #define XM_TXO_OK_HI 0x0284 /* 32 bit r/o Octets Transmitted OK High Cnt*/ 114 #define XM_TXO_OK_LO 0x0288 /* 32 bit r/o Octets Transmitted OK Low Cnt */ 115 #define XM_TXF_BC_OK 0x028c /* 32 bit r/o Broadcast Frames Xmitted OK */ 116 #define XM_TXF_MC_OK 0x0290 /* 32 bit r/o Multicast Frames Xmitted OK */ 117 #define XM_TXF_UC_OK 0x0294 /* 32 bit r/o Unicast Frames Xmitted OK */ 118 #define XM_TXF_LONG 0x0298 /* 32 bit r/o Tx Long Frame Counter */ 119 #define XM_TXE_BURST 0x029c /* 32 bit r/o Tx Burst Event Counter */ 120 #define XM_TXF_MPAUSE 0x02a0 /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */ 121 #define XM_TXF_MCTRL 0x02a4 /* 32 bit r/o Tx MAC Ctrl Frame Counter */ 122 #define XM_TXF_SNG_COL 0x02a8 /* 32 bit r/o Tx Single Collision Counter */ 123 #define XM_TXF_MUL_COL 0x02ac /* 32 bit r/o Tx Multiple Collision Counter */ 124 #define XM_TXF_ABO_COL 0x02b0 /* 32 bit r/o Tx aborted due to Exces. Col. */ 125 #define XM_TXF_LAT_COL 0x02b4 /* 32 bit r/o Tx Late Collision Counter */ 126 #define XM_TXF_DEF 0x02b8 /* 32 bit r/o Tx Deferred Frame Counter */ 127 #define XM_TXF_EX_DEF 0x02bc /* 32 bit r/o Tx Excessive Deferall Counter */ 128 #define XM_TXE_FIFO_UR 0x02c0 /* 32 bit r/o Tx FIFO Underrun Event Cnt */ 129 #define XM_TXE_CS_ERR 0x02c4 /* 32 bit r/o Tx Carrier Sense Error Cnt */ 130 #define XM_TXP_UTIL 0x02c8 /* 32 bit r/o Tx Utilization in % */ 131 /* 0x02cc - 0x02ce: reserved */ 132 #define XM_TXF_64B 0x02d0 /* 32 bit r/o 64 Byte Tx Frame Counter */ 133 #define XM_TXF_127B 0x02d4 /* 32 bit r/o 65-127 Byte Tx Frame Counter */ 134 #define XM_TXF_255B 0x02d8 /* 32 bit r/o 128-255 Byte Tx Frame Counter */ 135 #define XM_TXF_511B 0x02dc /* 32 bit r/o 256-511 Byte Tx Frame Counter */ 136 #define XM_TXF_1023B 0x02e0 /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/ 137 #define XM_TXF_MAX_SZ 0x02e4 /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/ 138 /* 0x02e8 - 0x02fe: reserved */ 139 #define XM_RXF_OK 0x0300 /* 32 bit r/o Frames Received OK */ 140 #define XM_RXO_OK_HI 0x0304 /* 32 bit r/o Octets Received OK High Cnt */ 141 #define XM_RXO_OK_LO 0x0308 /* 32 bit r/o Octets Received OK Low Counter*/ 142 #define XM_RXF_BC_OK 0x030c /* 32 bit r/o Broadcast Frames Received OK */ 143 #define XM_RXF_MC_OK 0x0310 /* 32 bit r/o Multicast Frames Received OK */ 144 #define XM_RXF_UC_OK 0x0314 /* 32 bit r/o Unicast Frames Received OK */ 145 #define XM_RXF_MPAUSE 0x0318 /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */ 146 #define XM_RXF_MCTRL 0x031c /* 32 bit r/o Rx MAC Ctrl Frame Counter */ 147 #define XM_RXF_INV_MP 0x0320 /* 32 bit r/o Rx invalid Pause Frame Cnt */ 148 #define XM_RXF_INV_MOC 0x0324 /* 32 bit r/o Rx Frames with inv. MAC Opcode*/ 149 #define XM_RXE_BURST 0x0328 /* 32 bit r/o Rx Burst Event Counter */ 150 #define XM_RXE_FMISS 0x032c /* 32 bit r/o Rx Missed Frames Event Cnt */ 151 #define XM_RXF_FRA_ERR 0x0330 /* 32 bit r/o Rx Framing Error Counter */ 152 #define XM_RXE_FIFO_OV 0x0334 /* 32 bit r/o Rx FIFO overflow Event Cnt */ 153 #define XM_RXF_JAB_PKT 0x0338 /* 32 bit r/o Rx Jabber Packet Frame Cnt */ 154 #define XM_RXE_CAR_ERR 0x033c /* 32 bit r/o Rx Carrier Event Error Cnt */ 155 #define XM_RXF_LEN_ERR 0x0340 /* 32 bit r/o Rx in Range Length Error */ 156 #define XM_RXE_SYM_ERR 0x0344 /* 32 bit r/o Rx Symbol Error Counter */ 157 #define XM_RXE_SHT_ERR 0x0348 /* 32 bit r/o Rx Short Event Error Cnt */ 158 #define XM_RXE_RUNT 0x034c /* 32 bit r/o Rx Runt Event Counter */ 159 #define XM_RXF_LNG_ERR 0x0350 /* 32 bit r/o Rx Frame too Long Error Cnt */ 160 #define XM_RXF_FCS_ERR 0x0354 /* 32 bit r/o Rx Frame Check Seq. Error Cnt */ 161 /* 0x0358 - 0x035a: reserved */ 162 #define XM_RXF_CEX_ERR 0x035c /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/ 163 #define XM_RXP_UTIL 0x0360 /* 32 bit r/o Rx Utilization in % */ 164 /* 0x0364 - 0x0366: reserved */ 165 #define XM_RXF_64B 0x0368 /* 32 bit r/o 64 Byte Rx Frame Counter */ 166 #define XM_RXF_127B 0x036c /* 32 bit r/o 65-127 Byte Rx Frame Counter */ 167 #define XM_RXF_255B 0x0370 /* 32 bit r/o 128-255 Byte Rx Frame Counter */ 168 #define XM_RXF_511B 0x0374 /* 32 bit r/o 256-511 Byte Rx Frame Counter */ 169 #define XM_RXF_1023B 0x0378 /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/ 170 #define XM_RXF_MAX_SZ 0x037c /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/ 171 /* 0x02e8 - 0x02fe: reserved */ 172 173 174 /*----------------------------------------------------------------------------*/ 175 /* 176 * XMAC Bit Definitions 177 * 178 * If the bit access behaviour differs from the register access behaviour 179 * (r/w, r/o) this is documented after the bit number. 180 * The following bit access behaviours are used: 181 * (sc) self clearing 182 * (ro) read only 183 */ 184 185 /* XM_MMU_CMD 16 bit r/w MMU Command Register */ 186 /* Bit 15..13: reserved */ 187 #define XM_MMU_PHY_RDY (1<<12) /* Bit 12: PHY Read Ready */ 188 #define XM_MMU_PHY_BUSY (1<<11) /* Bit 11: PHY Busy */ 189 #define XM_MMU_IGN_PF (1<<10) /* Bit 10: Ignore Pause Frame */ 190 #define XM_MMU_MAC_LB (1<<9) /* Bit 9: Enable MAC Loopback */ 191 /* Bit 8: reserved */ 192 #define XM_MMU_FRC_COL (1<<7) /* Bit 7: Force Collision */ 193 #define XM_MMU_SIM_COL (1<<6) /* Bit 6: Simulate Collision */ 194 #define XM_MMU_NO_PRE (1<<5) /* Bit 5: No MDIO Preamble */ 195 #define XM_MMU_GMII_FD (1<<4) /* Bit 4: GMII uses Full Duplex */ 196 #define XM_MMU_RAT_CTRL (1<<3) /* Bit 3: Enable Rate Control */ 197 #define XM_MMU_GMII_LOOP (1<<2) /* Bit 2: PHY is in Loopback Mode */ 198 #define XM_MMU_ENA_RX (1<<1) /* Bit 1: Enable Receiver */ 199 #define XM_MMU_ENA_TX (1<<0) /* Bit 0: Enable Transmitter */ 200 201 202 /* XM_TX_CMD 16 bit r/w Transmit Command Register */ 203 /* Bit 15..7: reserved */ 204 #define XM_TX_BK2BK (1<<6) /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/ 205 #define XM_TX_ENC_BYP (1<<5) /* Bit 5: Set Encoder in Bypass Mode */ 206 #define XM_TX_SAM_LINE (1<<4) /* Bit 4: (sc) Start utilization calculation */ 207 #define XM_TX_NO_GIG_MD (1<<3) /* Bit 3: Disable Carrier Extension */ 208 #define XM_TX_NO_PRE (1<<2) /* Bit 2: Disable Preamble Generation */ 209 #define XM_TX_NO_CRC (1<<1) /* Bit 1: Disable CRC Generation */ 210 #define XM_TX_AUTO_PAD (1<<0) /* Bit 0: Enable Automatic Padding */ 211 212 213 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */ 214 /* Bit 15..5: reserved */ 215 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */ 216 217 218 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */ 219 /* Bit 15..7: reserved */ 220 #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */ 221 222 223 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */ 224 /* Bit 15..8: reserved */ 225 #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */ 226 227 228 /* XM_RX_CMD 16 bit r/w Receive Command Register */ 229 /* Bit 15..9: reserved */ 230 #define XM_RX_LENERR_OK (1<<8) /* Bit 8 don't set Rx Err bit for */ 231 /* inrange error packets */ 232 #define XM_RX_BIG_PK_OK (1<<7) /* Bit 7 don't set Rx Err bit for */ 233 /* jumbo packets */ 234 #define XM_RX_IPG_CAP (1<<6) /* Bit 6 repl. type field with IPG */ 235 #define XM_RX_TP_MD (1<<5) /* Bit 5: Enable transparent Mode */ 236 #define XM_RX_STRIP_FCS (1<<4) /* Bit 4: Enable FCS Stripping */ 237 #define XM_RX_SELF_RX (1<<3) /* Bit 3: Enable Rx of own packets */ 238 #define XM_RX_SAM_LINE (1<<2) /* Bit 2: (sc) Start utilization calculation */ 239 #define XM_RX_STRIP_PAD (1<<1) /* Bit 1: Strip pad bytes of Rx frames */ 240 #define XM_RX_DIS_CEXT (1<<0) /* Bit 0: Disable carrier ext. check */ 241 242 243 /* XM_PHY_ADDR 16 bit r/w PHY Address Register */ 244 /* Bit 15..5: reserved */ 245 #define XM_PHY_ADDR_SZ 0x1f /* Bit 4..0: PHY Address bits */ 246 247 248 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */ 249 /* Bit 31..7: reserved */ 250 #define XM_GP_ANIP (1L<<6) /* Bit 6: (ro) Auto-Neg. in progress */ 251 #define XM_GP_FRC_INT (1L<<5) /* Bit 5: (sc) Force Interrupt */ 252 /* Bit 4: reserved */ 253 #define XM_GP_RES_MAC (1L<<3) /* Bit 3: (sc) Reset MAC and FIFOs */ 254 #define XM_GP_RES_STAT (1L<<2) /* Bit 2: (sc) Reset the statistics module */ 255 /* Bit 1: reserved */ 256 #define XM_GP_INP_ASS (1L<<0) /* Bit 0: (ro) GP Input Pin asserted */ 257 258 259 /* XM_IMSK 16 bit r/w Interrupt Mask Register */ 260 /* XM_ISRC 16 bit r/o Interrupt Status Register */ 261 /* Bit 15: reserved */ 262 #define XM_IS_LNK_AE (1<<14) /* Bit 14: Link Asynchronous Event */ 263 #define XM_IS_TX_ABORT (1<<13) /* Bit 13: Transmit Abort, late Col. etc */ 264 #define XM_IS_FRC_INT (1<<12) /* Bit 12: Force INT bit set in GP */ 265 #define XM_IS_INP_ASS (1<<11) /* Bit 11: Input Asserted, GP bit 0 set */ 266 #define XM_IS_LIPA_RC (1<<10) /* Bit 10: Link Partner requests config */ 267 #define XM_IS_RX_PAGE (1<<9) /* Bit 9: Page Received */ 268 #define XM_IS_TX_PAGE (1<<8) /* Bit 8: Next Page Loaded for Transmit */ 269 #define XM_IS_AND (1<<7) /* Bit 7: Auto-Negotiation Done */ 270 #define XM_IS_TSC_OV (1<<6) /* Bit 6: Time Stamp Counter Overflow */ 271 #define XM_IS_RXC_OV (1<<5) /* Bit 5: Rx Counter Event Overflow */ 272 #define XM_IS_TXC_OV (1<<4) /* Bit 4: Tx Counter Event Overflow */ 273 #define XM_IS_RXF_OV (1<<3) /* Bit 3: Receive FIFO Overflow */ 274 #define XM_IS_TXF_UR (1<<2) /* Bit 2: Transmit FIFO Underrun */ 275 #define XM_IS_TX_COMP (1<<1) /* Bit 1: Frame Tx Complete */ 276 #define XM_IS_RX_COMP (1<<0) /* Bit 0: Frame Rx Complete */ 277 278 #define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE |\ 279 XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | XM_IS_TXF_UR)) 280 281 282 /* XM_HW_CFG 16 bit r/w Hardware Config Register */ 283 /* Bit 15.. 4: reserved */ 284 #define XM_HW_GEN_EOP (1<<3) /* Bit 3: generate End of Packet pulse */ 285 #define XM_HW_COM4SIG (1<<2) /* Bit 2: use Comma Detect for Sig. Det.*/ 286 /* Bit 1: reserved */ 287 #define XM_HW_GMII_MD (1<<0) /* Bit 0: GMII Interface selected */ 288 289 290 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */ 291 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */ 292 /* Bit 15..10 reserved */ 293 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */ 294 295 /* XM_TX_THR 16 bit r/w Tx Request Threshold */ 296 /* XM_HT_THR 16 bit r/w Host Request Threshold */ 297 /* XM_RX_THR 16 bit r/w Rx Request Threshold */ 298 /* Bit 15..11 reserved */ 299 #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */ 300 301 302 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */ 303 #define XM_ST_VALID (1UL<<31) /* Bit 31: Status Valid */ 304 #define XM_ST_BYTE_CNT (0x3fffL<<17) /* Bit 30..17: Tx frame Length */ 305 #define XM_ST_RETRY_CNT (0x1fL<<12) /* Bit 16..12: Retry Count */ 306 #define XM_ST_EX_COL (1L<<11) /* Bit 11: Excessive Collisions */ 307 #define XM_ST_EX_DEF (1L<<10) /* Bit 10: Excessive Deferral */ 308 #define XM_ST_BURST (1L<<9) /* Bit 9: p. xmitted in burst md*/ 309 #define XM_ST_DEFER (1L<<8) /* Bit 8: packet was defered */ 310 #define XM_ST_BC (1L<<7) /* Bit 7: Broadcast packet */ 311 #define XM_ST_MC (1L<<6) /* Bit 6: Multicast packet */ 312 #define XM_ST_UC (1L<<5) /* Bit 5: Unicast packet */ 313 #define XM_ST_TX_UR (1L<<4) /* Bit 4: FIFO Underrun occured */ 314 #define XM_ST_CS_ERR (1L<<3) /* Bit 3: Carrier Sense Error */ 315 #define XM_ST_LAT_COL (1L<<2) /* Bit 2: Late Collision Error */ 316 #define XM_ST_MUL_COL (1L<<1) /* Bit 1: Multiple Collisions */ 317 #define XM_ST_SGN_COL (1L<<0) /* Bit 0: Single Collision */ 318 319 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */ 320 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */ 321 /* Bit 15..11: reserved */ 322 #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */ 323 324 325 /* XM_DEV_ID 32 bit r/o Device ID Register */ 326 #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */ 327 #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */ 328 329 330 /* XM_MODE 32 bit r/w Mode Register */ 331 /* Bit 31..27: reserved */ 332 #define XM_MD_ENA_REJ (1L<<26) /* Bit 26: Enable Frame Reject */ 333 #define XM_MD_SPOE_E (1L<<25) /* Bit 25: Send Pause on Edge */ 334 /* extern generated */ 335 #define XM_MD_TX_REP (1L<<24) /* Bit 24: Transmit Repeater Mode */ 336 #define XM_MD_SPOFF_I (1L<<23) /* Bit 23: Send Pause on FIFO full */ 337 /* intern generated */ 338 #define XM_MD_LE_STW (1L<<22) /* Bit 22: Rx Stat Word in Little Endian */ 339 #define XM_MD_TX_CONT (1L<<21) /* Bit 21: Send Continuous */ 340 #define XM_MD_TX_PAUSE (1L<<20) /* Bit 20: (sc) Send Pause Frame */ 341 #define XM_MD_ATS (1L<<19) /* Bit 19: Append Time Stamp */ 342 #define XM_MD_SPOL_I (1L<<18) /* Bit 18: Send Pause on Low */ 343 /* intern generated */ 344 #define XM_MD_SPOH_I (1L<<17) /* Bit 17: Send Pause on High */ 345 /* intern generated */ 346 #define XM_MD_CAP (1L<<16) /* Bit 16: Check Address Pair */ 347 #define XM_MD_ENA_HASH (1L<<15) /* Bit 15: Enable Hashing */ 348 #define XM_MD_CSA (1L<<14) /* Bit 14: Check Station Address */ 349 #define XM_MD_CAA (1L<<13) /* Bit 13: Check Address Array */ 350 #define XM_MD_RX_MCTRL (1L<<12) /* Bit 12: Rx MAC Control Frame */ 351 #define XM_MD_RX_RUNT (1L<<11) /* Bit 11: Rx Runt Frames */ 352 #define XM_MD_RX_IRLE (1L<<10) /* Bit 10: Rx in Range Len Err Frame */ 353 #define XM_MD_RX_LONG (1L<<9) /* Bit 9: Rx Long Frame */ 354 #define XM_MD_RX_CRCE (1L<<8) /* Bit 8: Rx CRC Error Frame */ 355 #define XM_MD_RX_ERR (1L<<7) /* Bit 7: Rx Error Frame */ 356 #define XM_MD_DIS_UC (1L<<6) /* Bit 6: Disable Rx Unicast */ 357 #define XM_MD_DIS_MC (1L<<5) /* Bit 5: Disable Rx Multicast */ 358 #define XM_MD_DIS_BC (1L<<4) /* Bit 4: Disable Rx Broadcast */ 359 #define XM_MD_ENA_PROM (1L<<3) /* Bit 3: Enable Promiscuous */ 360 #define XM_MD_ENA_BE (1L<<2) /* Bit 2: Enable Big Endian */ 361 #define XM_MD_FTF (1L<<1) /* Bit 1: (sc) Flush Tx FIFO */ 362 #define XM_MD_FRF (1L<<0) /* Bit 0: (sc) Flush Rx FIFO */ 363 364 #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I) 365 #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\ 366 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA) 367 368 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */ 369 /* Bit 16..6: reserved */ 370 #define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */ 371 #define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */ 372 #define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */ 373 #define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */ 374 #define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */ 375 #define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */ 376 377 378 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */ 379 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */ 380 #define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/ 381 #define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/ 382 #define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/ 383 #define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/ 384 #define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */ 385 #define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */ 386 #define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */ 387 #define XMR_UTIL_UR (1L<<24) /* Bit 24: Rx Util Cnt Underrun */ 388 #define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */ 389 /* Bit 22: reserved */ 390 #define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */ 391 #define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/ 392 #define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */ 393 #define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/ 394 #define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */ 395 /* Bit 16: reserved */ 396 #define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */ 397 #define XMR_JAB_PKT_OV (1L<<14) /* Bit 14: Rx Jabb Packet Cnt Ov */ 398 #define XMR_FIFO_OV (1L<<13) /* Bit 13: Rx FIFO Ov Ev Cnt Ov */ 399 #define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */ 400 #define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */ 401 #define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */ 402 #define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/ 403 #define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */ 404 #define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */ 405 #define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/ 406 #define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/ 407 #define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */ 408 #define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */ 409 #define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/ 410 #define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/ 411 #define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */ 412 413 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV) 414 415 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */ 416 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */ 417 /* Bit 31..26: reserved */ 418 #define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/ 419 #define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/ 420 #define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/ 421 #define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/ 422 #define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */ 423 #define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */ 424 #define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */ 425 #define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */ 426 #define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/ 427 #define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */ 428 #define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */ 429 #define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */ 430 #define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */ 431 #define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/ 432 #define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */ 433 #define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */ 434 #define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/ 435 #define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/ 436 #define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */ 437 #define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */ 438 #define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */ 439 #define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */ 440 #define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */ 441 #define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/ 442 #define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/ 443 #define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */ 444 445 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV) 446 447 /* 448 * Receive Frame Status Encoding 449 */ 450 #define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */ 451 #define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/ 452 #define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/ 453 #define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */ 454 #define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */ 455 #define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */ 456 /* Bit 12: reserved */ 457 #define XMR_FS_BURST (1L<<11) /* Bit 11: Burst Mode */ 458 #define XMR_FS_CEX_ERR (1L<<10) /* Bit 10: Carrier Ext. Error */ 459 #define XMR_FS_802_3 (1L<<9) /* Bit 9: 802.3 Frame */ 460 #define XMR_FS_COL_ERR (1L<<8) /* Bit 8: Collision Error */ 461 #define XMR_FS_CAR_ERR (1L<<7) /* Bit 7: Carrier Event Error */ 462 #define XMR_FS_LEN_ERR (1L<<6) /* Bit 6: In-Range Length Error */ 463 #define XMR_FS_FRA_ERR (1L<<5) /* Bit 5: Framing Error */ 464 #define XMR_FS_RUNT (1L<<4) /* Bit 4: Runt Frame */ 465 #define XMR_FS_LNG_ERR (1L<<3) /* Bit 3: Giant (Jumbo) Frame */ 466 #define XMR_FS_FCS_ERR (1L<<2) /* Bit 2: Frame Check Sequ Err */ 467 #define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */ 468 #define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */ 469 470 /* 471 * XMR_FS_ERR will be set if 472 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT, 473 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR 474 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue 475 * XMR_FS_ERR unless the corresponding bit in the Receive Command 476 * Register is set. 477 */ 478 #define XMR_FS_ANY_ERR XMR_FS_ERR 479 480 /*----------------------------------------------------------------------------*/ 481 /* 482 * XMAC-PHY Registers, indirect addressed over the XMAC 483 */ 484 #define PHY_XMAC_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 485 #define PHY_XMAC_STAT 0x01 /* 16 bit r/w PHY Status Register */ 486 #define PHY_XMAC_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 487 #define PHY_XMAC_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 488 #define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 489 #define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Abi Reg */ 490 #define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 491 #define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */ 492 #define PHY_XMAC_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ 493 /* 0x09 - 0x0e: reserved */ 494 #define PHY_XMAC_EXT_STAT 0x0f /* 16 bit r/o Ext Status Register */ 495 #define PHY_XMAC_RES_ABI 0x10 /* 16 bit r/o PHY Resolved Ability */ 496 497 /*----------------------------------------------------------------------------*/ 498 /* 499 * Broadcom-PHY Registers, indirect addressed over XMAC 500 */ 501 #define PHY_BCOM_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 502 #define PHY_BCOM_STAT 0x01 /* 16 bit r/o PHY Status Register */ 503 #define PHY_BCOM_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 504 #define PHY_BCOM_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 505 #define PHY_BCOM_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 506 #define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ 507 #define PHY_BCOM_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 508 #define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */ 509 #define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ 510 /* Broadcom-specific registers */ 511 #define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */ 512 #define PHY_BCOM_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ 513 /* 0x0b - 0x0e: reserved */ 514 #define PHY_BCOM_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ 515 #define PHY_BCOM_P_EXT_CTRL 0x10 /* 16 bit r/w PHY Extended Ctrl Reg */ 516 #define PHY_BCOM_P_EXT_STAT 0x11 /* 16 bit r/o PHY Extended Stat Reg */ 517 #define PHY_BCOM_RE_CTR 0x12 /* 16 bit r/w Receive Error Counter */ 518 #define PHY_BCOM_FC_CTR 0x13 /* 16 bit r/w False Carrier Sense Cnt */ 519 #define PHY_BCOM_RNO_CTR 0x14 /* 16 bit r/w Receiver NOT_OK Cnt */ 520 /* 0x15 - 0x17: reserved */ 521 #define PHY_BCOM_AUX_CTRL 0x18 /* 16 bit r/w Auxiliary Control Reg */ 522 #define PHY_BCOM_AUX_STAT 0x19 /* 16 bit r/o Auxiliary Stat Summary */ 523 #define PHY_BCOM_INT_STAT 0x1a /* 16 bit r/o Interrupt Status Reg */ 524 #define PHY_BCOM_INT_MASK 0x1b /* 16 bit r/w Interrupt Mask Reg */ 525 /* 0x1c: reserved */ 526 /* 0x1d - 0x1f: test registers */ 527 528 /*----------------------------------------------------------------------------*/ 529 /* 530 * Marvel-PHY Registers, indirect addressed over GMAC 531 */ 532 #define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 533 #define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ 534 #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 535 #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 536 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 537 #define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ 538 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 539 #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ 540 #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ 541 /* Marvel-specific registers */ 542 #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */ 543 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ 544 /* 0x0b - 0x0e: reserved */ 545 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ 546 #define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Ctrl Reg */ 547 #define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Stat Reg */ 548 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ 549 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ 550 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ 551 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ 552 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ 553 /* 0x17: reserved */ 554 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ 555 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ 556 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 557 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ 558 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ 559 /* 0x1d - 0x1f: reserved */ 560 561 /*----------------------------------------------------------------------------*/ 562 /* 563 * Level One-PHY Registers, indirect addressed over XMAC 564 */ 565 #define PHY_LONE_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 566 #define PHY_LONE_STAT 0x01 /* 16 bit r/o PHY Status Register */ 567 #define PHY_LONE_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 568 #define PHY_LONE_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 569 #define PHY_LONE_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 570 #define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ 571 #define PHY_LONE_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 572 #define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */ 573 #define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ 574 /* Level One-specific registers */ 575 #define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/ 576 #define PHY_LONE_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ 577 /* 0x0b -0x0e: reserved */ 578 #define PHY_LONE_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ 579 #define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/ 580 #define PHY_LONE_Q_STAT 0x11 /* 16 bit r/o Quick Status Reg */ 581 #define PHY_LONE_INT_ENAB 0x12 /* 16 bit r/w Interrupt Enable Reg */ 582 #define PHY_LONE_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ 583 #define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */ 584 #define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */ 585 #define PHY_LONE_CIM 0x16 /* 16 bit r/o CIM Reg */ 586 /* 0x17 -0x1c: reserved */ 587 588 /*----------------------------------------------------------------------------*/ 589 /* 590 * National-PHY Registers, indirect addressed over XMAC 591 */ 592 #define PHY_NAT_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 593 #define PHY_NAT_STAT 0x01 /* 16 bit r/w PHY Status Register */ 594 #define PHY_NAT_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 595 #define PHY_NAT_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 596 #define PHY_NAT_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 597 #define PHY_NAT_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */ 598 #define PHY_NAT_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 599 #define PHY_NAT_NEPG 0x07 /* 16 bit r/w Next Page Register */ 600 #define PHY_NAT_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner Reg */ 601 /* National-specific registers */ 602 #define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ 603 #define PHY_NAT_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ 604 /* 0x0b -0x0e: reserved */ 605 #define PHY_NAT_EXT_STAT 0x0f /* 16 bit r/o Extended Status Register */ 606 #define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit r/o Extended Control Reg1 */ 607 #define PHY_NAT_Q_STAT1 0x11 /* 16 bit r/o Quick Status Reg1 */ 608 #define PHY_NAT_10B_OP 0x12 /* 16 bit r/o 10Base-T Operations Reg */ 609 #define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit r/o Extended Control Reg1 */ 610 #define PHY_NAT_Q_STAT2 0x14 /* 16 bit r/o Quick Status Reg2 */ 611 /* 0x15 -0x18: reserved */ 612 #define PHY_NAT_PHY_ADDR 0x19 /* 16 bit r/o PHY Address Register */ 613 614 615 /*----------------------------------------------------------------------------*/ 616 617 /* 618 * PHY bit definitions 619 * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are 620 * XMAC/Broadcom/LevelOne/National/Marvell-specific. 621 * All other are general. 622 */ 623 624 /***** PHY_XMAC_CTRL 16 bit r/w PHY Control Register *****/ 625 /***** PHY_BCOM_CTRL 16 bit r/w PHY Control Register *****/ 626 /***** PHY_MARV_CTRL 16 bit r/w PHY Status Register *****/ 627 /***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/ 628 #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ 629 #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ 630 #define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */ 631 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ 632 #define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */ 633 #define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */ 634 #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ 635 #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ 636 #define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collision Test enabled */ 637 #define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */ 638 /* Bit 5..0: reserved */ 639 640 #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ 641 #define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ 642 #define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ 643 644 645 /***** PHY_XMAC_STAT 16 bit r/w PHY Status Register *****/ 646 /***** PHY_BCOM_STAT 16 bit r/w PHY Status Register *****/ 647 /***** PHY_MARV_STAT 16 bit r/w PHY Status Register *****/ 648 /***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/ 649 /* Bit 15..9: reserved */ 650 /* (BC/L1) 100/10 Mbps cap bits ignored*/ 651 #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ 652 /* Bit 7: reserved */ 653 #define PHY_ST_PRE_SUP (1<<6) /* Bit 6: (BC/L1) preamble suppression */ 654 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ 655 #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */ 656 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ 657 #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ 658 #define PHY_ST_JAB_DET (1<<1) /* Bit 1: (BC/L1) Jabber Detected */ 659 #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ 660 661 662 /***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */ 663 /***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */ 664 /***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */ 665 /***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */ 666 #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ 667 #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ 668 #define PHY_I1_REV_MSK 0x0f /* Bit 3.. 0: Revision Number */ 669 670 /* different Broadcom PHY Ids */ 671 #define PHY_BCOM_ID1_A1 0x6041 672 #define PHY_BCOM_ID1_B2 0x6043 673 #define PHY_BCOM_ID1_C0 0x6044 674 #define PHY_BCOM_ID1_C5 0x6047 675 676 677 /***** PHY_XMAC_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 678 /***** PHY_XMAC_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ 679 #define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */ 680 #define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */ 681 #define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remote Fault Bits */ 682 /* Bit 11.. 9: reserved */ 683 #define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */ 684 #define PHY_X_AN_HD (1<<6) /* Bit 6: Half Duplex */ 685 #define PHY_X_AN_FD (1<<5) /* Bit 5: Full Duplex */ 686 /* Bit 4.. 0: reserved */ 687 688 /***** PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 689 /***** PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ 690 /* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ 691 /* Bit 14: reserved */ 692 #define PHY_B_AN_RF (1<<13) /* Bit 13: Remote Fault */ 693 /* Bit 12: reserved */ 694 #define PHY_B_AN_ASP (1<<11) /* Bit 11: Asymmetric Pause */ 695 #define PHY_B_AN_PC (1<<10) /* Bit 10: Pause Capable */ 696 /* Bit 9..5: 100/10 BT cap bits ingnored */ 697 #define PHY_B_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/ 698 699 /***** PHY_LONE_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 700 /***** PHY_LONE_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ 701 /* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ 702 /* Bit 14: reserved */ 703 #define PHY_L_AN_RF (1<<13) /* Bit 13: Remote Fault */ 704 /* Bit 12: reserved */ 705 #define PHY_L_AN_ASP (1<<11) /* Bit 11: Asymmetric Pause */ 706 #define PHY_L_AN_PC (1<<10) /* Bit 10: Pause Capable */ 707 /* Bit 9..5: 100/10 BT cap bits ingnored */ 708 #define PHY_L_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/ 709 710 /***** PHY_NAT_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 711 /***** PHY_NAT_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ 712 /* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ 713 /* Bit 14: reserved */ 714 #define PHY_N_AN_RF (1<<13) /* Bit 13: Remote Fault */ 715 /* Bit 12: reserved */ 716 #define PHY_N_AN_100F (1<<11) /* Bit 11: 100Base-T2 FD Support */ 717 #define PHY_N_AN_100H (1<<10) /* Bit 10: 100Base-T2 HD Support */ 718 /* Bit 9..5: 100/10 BT cap bits ingnored */ 719 #define PHY_N_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/ 720 721 /* field type definition for PHY_x_AN_SEL */ 722 #define PHY_SEL_TYPE 0x01 /* 00001 = Ethernet */ 723 724 /***** PHY_XMAC_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ 725 /* Bit 15..4: reserved */ 726 #define PHY_ANE_LP_NP (1<<3) /* Bit 3: Link Partner can Next Page */ 727 #define PHY_ANE_LOC_NP (1<<2) /* Bit 2: Local PHY can Next Page */ 728 #define PHY_ANE_RX_PG (1<<1) /* Bit 1: Page Received */ 729 /* Bit 0: reserved */ 730 731 /***** PHY_BCOM_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ 732 /***** PHY_LONE_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ 733 /***** PHY_MARV_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ 734 /* Bit 15..5: reserved */ 735 #define PHY_ANE_PAR_DF (1<<4) /* Bit 4: Parallel Detection Fault */ 736 /* PHY_ANE_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */ 737 /* PHY_ANE_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */ 738 /* PHY_ANE_RX_PG (see XMAC) Bit 1: Page Received */ 739 #define PHY_ANE_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */ 740 741 /***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/ 742 /***** PHY_BCOM_NEPG 16 bit r/w Next Page Register *****/ 743 /***** PHY_LONE_NEPG 16 bit r/w Next Page Register *****/ 744 /***** PHY_XMAC_NEPG_LP 16 bit r/o Next Page Link Partner *****/ 745 /***** PHY_BCOM_NEPG_LP 16 bit r/o Next Page Link Partner *****/ 746 /***** PHY_LONE_NEPG_LP 16 bit r/o Next Page Link Partner *****/ 747 #define PHY_NP_MORE (1<<15) /* Bit 15: More, Next Pages to follow */ 748 #define PHY_NP_ACK1 (1<<14) /* Bit 14: (ro) Ack1, for receiving a message */ 749 #define PHY_NP_MSG_VAL (1<<13) /* Bit 13: Message Page valid */ 750 #define PHY_NP_ACK2 (1<<12) /* Bit 12: Ack2, comply with msg content */ 751 #define PHY_NP_TOG (1<<11) /* Bit 11: Toggle Bit, ensure sync */ 752 #define PHY_NP_MSG 0x07ff /* Bit 10..0: Message from/to Link Partner */ 753 754 /* 755 * XMAC-Specific 756 */ 757 /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/ 758 #define PHY_X_EX_FD (1<<15) /* Bit 15: Device Supports Full Duplex */ 759 #define PHY_X_EX_HD (1<<14) /* Bit 14: Device Supports Half Duplex */ 760 /* Bit 13..0: reserved */ 761 762 /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/ 763 /* Bit 15..9: reserved */ 764 #define PHY_X_RS_PAUSE (3<<7) /* Bit 8..7: selected Pause Mode */ 765 #define PHY_X_RS_HD (1<<6) /* Bit 6: Half Duplex Mode selected */ 766 #define PHY_X_RS_FD (1<<5) /* Bit 5: Full Duplex Mode selected */ 767 #define PHY_X_RS_ABLMIS (1<<4) /* Bit 4: duplex or pause cap mismatch */ 768 #define PHY_X_RS_PAUMIS (1<<3) /* Bit 3: pause capability mismatch */ 769 /* Bit 2..0: reserved */ 770 /* 771 * Remote Fault Bits (PHY_X_AN_RFB) encoding 772 */ 773 #define X_RFB_OK (0<<12) /* Bit 13..12 No errors, Link OK */ 774 #define X_RFB_LF (1<<12) /* Bit 13..12 Link Failure */ 775 #define X_RFB_OFF (2<<12) /* Bit 13..12 Offline */ 776 #define X_RFB_AN_ERR (3<<12) /* Bit 13..12 Auto-Negotiation Error */ 777 778 /* 779 * Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding 780 */ 781 #define PHY_X_P_NO_PAUSE (0<<7) /* Bit 8..7: no Pause Mode */ 782 #define PHY_X_P_SYM_MD (1<<7) /* Bit 8..7: symmetric Pause Mode */ 783 #define PHY_X_P_ASYM_MD (2<<7) /* Bit 8..7: asymmetric Pause Mode */ 784 #define PHY_X_P_BOTH_MD (3<<7) /* Bit 8..7: both Pause Mode */ 785 786 787 /* 788 * Broadcom-Specific 789 */ 790 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 791 #define PHY_B_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 792 #define PHY_B_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ 793 #define PHY_B_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ 794 #define PHY_B_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ 795 #define PHY_B_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ 796 #define PHY_B_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ 797 /* Bit 7..0: reserved */ 798 799 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 800 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 801 #define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 802 #define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 803 #define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 804 #define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ 805 #define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 806 #define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 807 /* Bit 9..8: reserved */ 808 #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ 809 810 /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/ 811 #define PHY_B_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ 812 #define PHY_B_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ 813 #define PHY_B_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ 814 #define PHY_B_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ 815 /* Bit 11..0: reserved */ 816 817 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/ 818 #define PHY_B_PEC_MAC_PHY (1<<15) /* Bit 15: 10BIT/GMI-Interface */ 819 #define PHY_B_PEC_DIS_CROSS (1<<14) /* Bit 14: Disable MDI Crossover */ 820 #define PHY_B_PEC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */ 821 #define PHY_B_PEC_INT_DIS (1<<12) /* Bit 12: Interrupts Disabled */ 822 #define PHY_B_PEC_F_INT (1<<11) /* Bit 11: Force Interrupt */ 823 #define PHY_B_PEC_BY_45 (1<<10) /* Bit 10: Bypass 4B5B-Decoder */ 824 #define PHY_B_PEC_BY_SCR (1<<9) /* Bit 9: Bypass Scrambler */ 825 #define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */ 826 #define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */ 827 #define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */ 828 #define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */ 829 #define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */ 830 #define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */ 831 #define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */ 832 #define PHY_B_PEC_3_LED (1<<1) /* Bit 1: Three Link LED mode */ 833 #define PHY_B_PEC_HIGH_LA (1<<0) /* Bit 0: GMII FIFO Elasticy */ 834 835 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/ 836 /* Bit 15..14: reserved */ 837 #define PHY_B_PES_CROSS_STAT (1<<13) /* Bit 13: MDI Crossover Status */ 838 #define PHY_B_PES_INT_STAT (1<<12) /* Bit 12: Interrupt Status */ 839 #define PHY_B_PES_RRS (1<<11) /* Bit 11: Remote Receiver Stat. */ 840 #define PHY_B_PES_LRS (1<<10) /* Bit 10: Local Receiver Stat. */ 841 #define PHY_B_PES_LOCKED (1<<9) /* Bit 9: Locked */ 842 #define PHY_B_PES_LS (1<<8) /* Bit 8: Link Status */ 843 #define PHY_B_PES_RF (1<<7) /* Bit 7: Remote Fault */ 844 #define PHY_B_PES_CE_ER (1<<6) /* Bit 6: Carrier Ext Error */ 845 #define PHY_B_PES_BAD_SSD (1<<5) /* Bit 5: Bad SSD */ 846 #define PHY_B_PES_BAD_ESD (1<<4) /* Bit 4: Bad ESD */ 847 #define PHY_B_PES_RX_ER (1<<3) /* Bit 3: Receive Error */ 848 #define PHY_B_PES_TX_ER (1<<2) /* Bit 2: Transmit Error */ 849 #define PHY_B_PES_LOCK_ER (1<<1) /* Bit 1: Lock Error */ 850 #define PHY_B_PES_MLT3_ER (1<<0) /* Bit 0: MLT3 code Error */ 851 852 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/ 853 /* Bit 15..8: reserved */ 854 #define PHY_B_FC_CTR 0xff /* Bit 7..0: False Carrier Counter */ 855 856 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/ 857 #define PHY_B_RC_LOC_MSK 0xff00 /* Bit 15..8: Local Rx NOT_OK cnt */ 858 #define PHY_B_RC_REM_MSK 0x00ff /* Bit 7..0: Remote Rx NOT_OK cnt */ 859 860 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/ 861 #define PHY_B_AC_L_SQE (1<<15) /* Bit 15: Low Squelch */ 862 #define PHY_B_AC_LONG_PACK (1<<14) /* Bit 14: Rx Long Packets */ 863 #define PHY_B_AC_ER_CTRL (3<<12) /* Bit 13..12: Edgerate Control */ 864 /* Bit 11: reserved */ 865 #define PHY_B_AC_TX_TST (1<<10) /* Bit 10: Tx test bit, always 1 */ 866 /* Bit 9.. 8: reserved */ 867 #define PHY_B_AC_DIS_PRF (1<<7) /* Bit 7: dis part resp filter */ 868 /* Bit 6: reserved */ 869 #define PHY_B_AC_DIS_PM (1<<5) /* Bit 5: dis power management */ 870 /* Bit 4: reserved */ 871 #define PHY_B_AC_DIAG (1<<3) /* Bit 3: Diagnostic Mode */ 872 /* Bit 2.. 0: reserved */ 873 874 /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/ 875 #define PHY_B_AS_AN_C (1<<15) /* Bit 15: AutoNeg complete */ 876 #define PHY_B_AS_AN_CA (1<<14) /* Bit 14: AN Complete Ack */ 877 #define PHY_B_AS_ANACK_D (1<<13) /* Bit 13: AN Ack Detect */ 878 #define PHY_B_AS_ANAB_D (1<<12) /* Bit 12: AN Ability Detect */ 879 #define PHY_B_AS_NPW (1<<11) /* Bit 11: AN Next Page Wait */ 880 #define PHY_B_AS_AN_RES_MSK (7<<8) /* Bit 10..8: AN HDC */ 881 #define PHY_B_AS_PDF (1<<7) /* Bit 7: Parallel Detect. Fault */ 882 #define PHY_B_AS_RF (1<<6) /* Bit 6: Remote Fault */ 883 #define PHY_B_AS_ANP_R (1<<5) /* Bit 5: AN Page Received */ 884 #define PHY_B_AS_LP_ANAB (1<<4) /* Bit 4: LP AN Ability */ 885 #define PHY_B_AS_LP_NPAB (1<<3) /* Bit 3: LP Next Page Ability */ 886 #define PHY_B_AS_LS (1<<2) /* Bit 2: Link Status */ 887 #define PHY_B_AS_PRR (1<<1) /* Bit 1: Pause Resolution-Rx */ 888 #define PHY_B_AS_PRT (1<<0) /* Bit 0: Pause Resolution-Tx */ 889 890 #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT) 891 892 /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/ 893 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ 894 /* Bit 15: reserved */ 895 #define PHY_B_IS_PSE (1<<14) /* Bit 14: Pair Swap Error */ 896 #define PHY_B_IS_MDXI_SC (1<<13) /* Bit 13: MDIX Status Change */ 897 #define PHY_B_IS_HCT (1<<12) /* Bit 12: counter above 32k */ 898 #define PHY_B_IS_LCT (1<<11) /* Bit 11: counter above 128 */ 899 #define PHY_B_IS_AN_PR (1<<10) /* Bit 10: Page Received */ 900 #define PHY_B_IS_NO_HDCL (1<<9) /* Bit 9: No HCD Link */ 901 #define PHY_B_IS_NO_HDC (1<<8) /* Bit 8: No HCD */ 902 #define PHY_B_IS_NEG_USHDC (1<<7) /* Bit 7: Negotiated Unsup. HCD */ 903 #define PHY_B_IS_SCR_S_ER (1<<6) /* Bit 6: Scrambler Sync Error */ 904 #define PHY_B_IS_RRS_CHANGE (1<<5) /* Bit 5: Remote Rx Stat Change */ 905 #define PHY_B_IS_LRS_CHANGE (1<<4) /* Bit 4: Local Rx Stat Change */ 906 #define PHY_B_IS_DUP_CHANGE (1<<3) /* Bit 3: Duplex Mode Change */ 907 #define PHY_B_IS_LSP_CHANGE (1<<2) /* Bit 2: Link Speed Change */ 908 #define PHY_B_IS_LST_CHANGE (1<<1) /* Bit 1: Link Status Changed */ 909 #define PHY_B_IS_CRC_ER (1<<0) /* Bit 0: CRC Error */ 910 911 #define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) 912 913 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */ 914 #define PHY_B_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */ 915 #define PHY_B_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */ 916 #define PHY_B_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */ 917 #define PHY_B_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */ 918 919 /* 920 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg) 921 */ 922 #define PHY_B_RES_1000FD (7<<8) /* Bit 10..8: 1000Base-T Full Dup. */ 923 #define PHY_B_RES_1000HD (6<<8) /* Bit 10..8: 1000Base-T Half Dup. */ 924 /* others: 100/10: invalid for us */ 925 926 /* 927 * Level One-Specific 928 */ 929 /***** PHY_LONE_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 930 #define PHY_L_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 931 #define PHY_L_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ 932 #define PHY_L_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ 933 #define PHY_L_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ 934 #define PHY_L_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ 935 #define PHY_L_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ 936 /* Bit 7..0: reserved */ 937 938 /***** PHY_LONE_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 939 #define PHY_L_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 940 #define PHY_L_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 941 #define PHY_L_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 942 #define PHY_L_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ 943 #define PHY_L_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 944 #define PHY_L_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 945 /* Bit 9..8: reserved */ 946 #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ 947 948 /***** PHY_LONE_EXT_STAT 16 bit r/o Extended Status Register *****/ 949 #define PHY_L_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ 950 #define PHY_L_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ 951 #define PHY_L_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ 952 #define PHY_L_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ 953 /* Bit 11..0: reserved */ 954 955 /***** PHY_LONE_PORT_CFG 16 bit r/w Port Configuration Reg *****/ 956 #define PHY_L_PC_REP_MODE (1<<15) /* Bit 15: Repeater Mode */ 957 /* Bit 14: reserved */ 958 #define PHY_L_PC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */ 959 #define PHY_L_PC_BY_SCR (1<<12) /* Bit 12: Bypass Scrambler */ 960 #define PHY_L_PC_BY_45 (1<<11) /* Bit 11: Bypass 4B5B-Decoder */ 961 #define PHY_L_PC_JAB_DIS (1<<10) /* Bit 10: Jabber Disabled */ 962 #define PHY_L_PC_SQE (1<<9) /* Bit 9: Enable Heartbeat */ 963 #define PHY_L_PC_TP_LOOP (1<<8) /* Bit 8: TP Loopback */ 964 #define PHY_L_PC_SSS (1<<7) /* Bit 7: Smart Speed Selection */ 965 #define PHY_L_PC_FIFO_SIZE (1<<6) /* Bit 6: FIFO Size */ 966 #define PHY_L_PC_PRE_EN (1<<5) /* Bit 5: Preamble Enable */ 967 #define PHY_L_PC_CIM (1<<4) /* Bit 4: Carrier Integrity Mon */ 968 #define PHY_L_PC_10_SER (1<<3) /* Bit 3: Use Serial Output */ 969 #define PHY_L_PC_ANISOL (1<<2) /* Bit 2: Unisolate Port */ 970 #define PHY_L_PC_TEN_BIT (1<<1) /* Bit 1: 10bit iface mode on */ 971 #define PHY_L_PC_ALTCLOCK (1<<0) /* Bit 0: (ro) ALTCLOCK Mode on */ 972 973 /***** PHY_LONE_Q_STAT 16 bit r/o Quick Status Reg *****/ 974 #define PHY_L_QS_D_RATE (3<<14) /* Bit 15..14: Data Rate */ 975 #define PHY_L_QS_TX_STAT (1<<13) /* Bit 13: Transmitting */ 976 #define PHY_L_QS_RX_STAT (1<<12) /* Bit 12: Receiving */ 977 #define PHY_L_QS_COL_STAT (1<<11) /* Bit 11: Collision */ 978 #define PHY_L_QS_L_STAT (1<<10) /* Bit 10: Link is up */ 979 #define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */ 980 #define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */ 981 #define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */ 982 #define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */ 983 #define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */ 984 #define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */ 985 #define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */ 986 #define PHY_L_QS_EVENT (1<<0) /* Bit 0: Event has occurred */ 987 988 /***** PHY_LONE_INT_ENAB 16 bit r/w Interrupt Enable Reg *****/ 989 /***** PHY_LONE_INT_STAT 16 bit r/o Interrupt Status Reg *****/ 990 /* Bit 15..14: reserved */ 991 #define PHY_L_IS_AN_F (1<<13) /* Bit 13: Auto-Negotiation fault */ 992 /* Bit 12: not described */ 993 #define PHY_L_IS_CROSS (1<<11) /* Bit 11: Crossover used */ 994 #define PHY_L_IS_POL (1<<10) /* Bit 10: Polarity correct. used */ 995 #define PHY_L_IS_SS (1<<9) /* Bit 9: Smart Speed Downgrade */ 996 #define PHY_L_IS_CFULL (1<<8) /* Bit 8: Counter Full */ 997 #define PHY_L_IS_AN_C (1<<7) /* Bit 7: AutoNeg Complete */ 998 #define PHY_L_IS_SPEED (1<<6) /* Bit 6: Speed Changed */ 999 #define PHY_L_IS_DUP (1<<5) /* Bit 5: Duplex Changed */ 1000 #define PHY_L_IS_LS (1<<4) /* Bit 4: Link Status Changed */ 1001 #define PHY_L_IS_ISOL (1<<3) /* Bit 3: Isolate Occured */ 1002 #define PHY_L_IS_MDINT (1<<2) /* Bit 2: (ro) STAT: MII Int Pending */ 1003 #define PHY_L_IS_INTEN (1<<1) /* Bit 1: ENAB: Enable IRQs */ 1004 #define PHY_L_IS_FORCE (1<<0) /* Bit 0: ENAB: Force Interrupt */ 1005 1006 /* int. mask */ 1007 #define PHY_L_DEF_MSK (PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN) 1008 1009 /***** PHY_LONE_LED_CFG 16 bit r/w LED Configuration Reg *****/ 1010 #define PHY_L_LC_LEDC (3<<14) /* Bit 15..14: Col/Blink/On/Off */ 1011 #define PHY_L_LC_LEDR (3<<12) /* Bit 13..12: Rx/Blink/On/Off */ 1012 #define PHY_L_LC_LEDT (3<<10) /* Bit 11..10: Tx/Blink/On/Off */ 1013 #define PHY_L_LC_LEDG (3<<8) /* Bit 9..8: Giga/Blink/On/Off */ 1014 #define PHY_L_LC_LEDS (3<<6) /* Bit 7..6: 10-100/Blink/On/Off */ 1015 #define PHY_L_LC_LEDL (3<<4) /* Bit 5..4: Link/Blink/On/Off */ 1016 #define PHY_L_LC_LEDF (3<<2) /* Bit 3..2: Duplex/Blink/On/Off */ 1017 #define PHY_L_LC_PSTRECH (1<<1) /* Bit 1: Strech LED Pulses */ 1018 #define PHY_L_LC_FREQ (1<<0) /* Bit 0: 30/100 ms */ 1019 1020 /***** PHY_LONE_PORT_CTRL 16 bit r/w Port Control Reg *****/ 1021 #define PHY_L_PC_TX_TCLK (1<<15) /* Bit 15: Enable TX_TCLK */ 1022 /* Bit 14: reserved */ 1023 #define PHY_L_PC_ALT_NP (1<<13) /* Bit 14: Alternate Next Page */ 1024 #define PHY_L_PC_GMII_ALT (1<<12) /* Bit 13: Alternate GMII driver */ 1025 /* Bit 11: reserved */ 1026 #define PHY_L_PC_TEN_CRS (1<<10) /* Bit 10: Extend CRS*/ 1027 /* Bit 9..0: not described */ 1028 1029 /***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/ 1030 #define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */ 1031 #define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */ 1032 1033 1034 /* 1035 * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding 1036 */ 1037 #define PHY_L_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */ 1038 #define PHY_L_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */ 1039 #define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */ 1040 #define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */ 1041 1042 1043 /* 1044 * National-Specific 1045 */ 1046 /***** PHY_NAT_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1047 #define PHY_N_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 1048 #define PHY_N_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ 1049 #define PHY_N_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ 1050 #define PHY_N_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ 1051 #define PHY_N_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ 1052 #define PHY_N_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ 1053 #define PHY_N_1000C_APC (1<<7) /* Bit 7: Asymmetric Pause Cap. */ 1054 /* Bit 6..0: reserved */ 1055 1056 /***** PHY_NAT_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1057 #define PHY_N_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 1058 #define PHY_N_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 1059 #define PHY_N_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 1060 #define PHY_N_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/ 1061 #define PHY_N_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 1062 #define PHY_N_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 1063 #define PHY_N_1000C_LP_APC (1<<9) /* Bit 9: LP Asym. Pause Cap. */ 1064 /* Bit 8: reserved */ 1065 #define PHY_N_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ 1066 1067 /***** PHY_NAT_EXT_STAT 16 bit r/o Extended Status Register *****/ 1068 #define PHY_N_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ 1069 #define PHY_N_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ 1070 #define PHY_N_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ 1071 #define PHY_N_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ 1072 /* Bit 11..0: reserved */ 1073 1074 /* todo: those are still missing */ 1075 /***** PHY_NAT_EXT_CTRL1 16 bit r/o Extended Control Reg1 *****/ 1076 /***** PHY_NAT_Q_STAT1 16 bit r/o Quick Status Reg1 *****/ 1077 /***** PHY_NAT_10B_OP 16 bit r/o 10Base-T Operations Reg *****/ 1078 /***** PHY_NAT_EXT_CTRL2 16 bit r/o Extended Control Reg1 *****/ 1079 /***** PHY_NAT_Q_STAT2 16 bit r/o Quick Status Reg2 *****/ 1080 /***** PHY_NAT_PHY_ADDR 16 bit r/o PHY Address Register *****/ 1081 1082 /* 1083 * Marvell-Specific 1084 */ 1085 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 1086 /***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ 1087 #define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ 1088 #define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ 1089 #define PHY_M_AN_RF BIT_13 /* Remote Fault */ 1090 /* Bit 12: reserved */ 1091 #define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ 1092 #define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ 1093 #define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ 1094 #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ 1095 #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ 1096 #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ 1097 1098 /* special defines for FIBER (88E1011S only) */ 1099 #define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ 1100 #define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ 1101 #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ 1102 #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ 1103 1104 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ 1105 #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ 1106 #define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ 1107 #define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ 1108 #define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ 1109 1110 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1111 #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 1112 #define PHY_M_1000C_MSE (1<<12) /* Bit 12: Manual Master/Slave Enable */ 1113 #define PHY_M_1000C_MSC (1<<11) /* Bit 11: M/S Configuration (1=Master) */ 1114 #define PHY_M_1000C_MPD (1<<10) /* Bit 10: Multi-Port Device */ 1115 #define PHY_M_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ 1116 #define PHY_M_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ 1117 /* Bit 7..0: reserved */ 1118 1119 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ 1120 #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ 1121 #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ 1122 #define PHY_M_PC_ASS_CRS_TX (1<<11) /* Bit 11: Assert CRS on Transmit */ 1123 #define PHY_M_PC_FL_GOOD (1<<10) /* Bit 10: Force Link Good */ 1124 #define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ 1125 #define PHY_M_PC_ENA_EXT_D (1<<7) /* Bit 7: Enable Ext. Distance (10BT) */ 1126 #define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ 1127 #define PHY_M_PC_DIS_125CLK (1<<4) /* Bit 4: Disable 125 CLK */ 1128 #define PHY_M_PC_MAC_POW_UP (1<<3) /* Bit 3: MAC Power up */ 1129 #define PHY_M_PC_SQE_T_ENA (1<<2) /* Bit 2: SQE Test Enabled */ 1130 #define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */ 1131 #define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */ 1132 1133 #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ 1134 #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ 1135 1136 #define PHY_M_PC_MDI_XMODE(x) SHIFT5(x) 1137 #define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ 1138 #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ 1139 #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ 1140 1141 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ 1142 #define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ 1143 #define PHY_M_PS_SPEED_1000 (1<<15) /* 10 = 1000 Mbps */ 1144 #define PHY_M_PS_SPEED_100 (1<<14) /* 01 = 100 Mbps */ 1145 #define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ 1146 #define PHY_M_PS_FULL_DUP (1<<13) /* Bit 13: Full Duplex */ 1147 #define PHY_M_PS_PAGE_REC (1<<12) /* Bit 12: Page Received */ 1148 #define PHY_M_PS_SPDUP_RES (1<<11) /* Bit 11: Speed & Duplex Resolved */ 1149 #define PHY_M_PS_LINK_UP (1<<10) /* Bit 10: Link Up */ 1150 #define PHY_M_PS_CABLE_MSK (3<<7) /* Bit 9.. 7: Cable Length Mask */ 1151 #define PHY_M_PS_MDI_X_STAT (1<<6) /* Bit 6: MDI Crossover Stat (1=MDIX) */ 1152 #define PHY_M_PS_DOWNS_STAT (1<<5) /* Bit 5: Downshift Status (1=downsh.) */ 1153 #define PHY_M_PS_ENDET_STAT (1<<4) /* Bit 4: Energy Detect Status (1=act) */ 1154 #define PHY_M_PS_TX_P_EN (1<<3) /* Bit 3: Tx Pause Enabled */ 1155 #define PHY_M_PS_RX_P_EN (1<<2) /* Bit 2: Rx Pause Enabled */ 1156 #define PHY_M_PS_POL_REV (1<<1) /* Bit 1: Polarity Reversed */ 1157 #define PHY_M_PC_JABBER (1<<0) /* Bit 0: Jabber */ 1158 1159 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 1160 1161 /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ 1162 /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ 1163 #define PHY_M_IS_AN_ERROR (1<<15) /* Bit 15: Auto-Negotiation Error */ 1164 #define PHY_M_IS_LSP_CHANGE (1<<14) /* Bit 14: Link Speed Changed */ 1165 #define PHY_M_IS_DUP_CHANGE (1<<13) /* Bit 13: Duplex Mode Changed */ 1166 #define PHY_M_IS_AN_PR (1<<12) /* Bit 12: Page Received */ 1167 #define PHY_M_IS_AN_COMPL (1<<11) /* Bit 11: Auto-Negotiation Completed */ 1168 #define PHY_M_IS_LST_CHANGE (1<<10) /* Bit 10: Link Status Changed */ 1169 #define PHY_M_IS_SYMB_ERROR (1<<9) /* Bit 9: Symbol Error */ 1170 #define PHY_M_IS_FALSE_CARR (1<<8) /* Bit 8: False Carrier */ 1171 #define PHY_M_IS_FIFO_ERROR (1<<7) /* Bit 7: FIFO Overflow/Underrun Error */ 1172 #define PHY_M_IS_MDI_CHANGE (1<<6) /* Bit 6: MDI Crossover Changed */ 1173 #define PHY_M_IS_DOWNSH_DET (1<<5) /* Bit 5: Downshift Detected */ 1174 #define PHY_M_IS_END_CHANGE (1<<4) /* Bit 4: Energy Detect Changed */ 1175 /* Bit 3..2: reserved */ 1176 #define PHY_M_IS_POL_CHANGE (1<<1) /* Bit 1: Polarity Changed */ 1177 #define PHY_M_IS_JABBER (1<<0) /* Bit 0: Jabber */ 1178 1179 #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ 1180 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) 1181 1182 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ 1183 #define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master downshift counter */ 1184 #define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave downshift counter */ 1185 #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ 1186 #define PHY_M_EC_FIB_AN_ENA (1<<3) /* Bit 3: Fiber Auto-Neg. Enable */ 1187 1188 #define PHY_M_EC_M_DSC(x) SHIFT10(x) /* 00=1x; 01=2x; 10=3x; 11=4x */ 1189 #define PHY_M_EC_S_DSC(x) SHIFT8(x) /* 00=dis; 01=1x; 10=2x; 11=3x */ 1190 #define PHY_M_EC_MAC_S(x) SHIFT4(x) /* 01X=0; 110=2.5; 111=25 (MHz) */ 1191 1192 #define MAC_TX_CLK_0_MHZ 2 1193 #define MAC_TX_CLK_2_5_MHZ 6 1194 #define MAC_TX_CLK_25_MHZ 7 1195 1196 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ 1197 #define PHY_M_LEDC_DIS_LED (1<<15) /* Bit 15: Disable LED */ 1198 #define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ 1199 #define PHY_M_LEDC_F_INT (1<<11) /* Bit 11: Force Interrupt */ 1200 #define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ 1201 /* Bit 7.. 5: reserved */ 1202 #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ 1203 #define PHY_M_LEDC_DP_CTRL (1<<2) /* Bit 2: Duplex Control */ 1204 #define PHY_M_LEDC_RX_CTRL (1<<1) /* Bit 1: Rx activity / Link */ 1205 #define PHY_M_LEDC_TX_CTRL (1<<0) /* Bit 0: Tx activity / Link */ 1206 1207 #define PHY_M_LED_PULS_DUR(x) SHIFT12(x) /* Pulse Stretch Duration */ 1208 1209 #define PULS_NO_STR 0 /* no pulse stretching */ 1210 #define PULS_21MS 1 /* 21 ms to 42 ms */ 1211 #define PULS_42MS 2 /* 42 ms to 84 ms */ 1212 #define PULS_84MS 3 /* 84 ms to 170 ms */ 1213 #define PULS_170MS 4 /* 170 ms to 340 ms */ 1214 #define PULS_340MS 5 /* 340 ms to 670 ms */ 1215 #define PULS_670MS 6 /* 670 ms to 1.3 s */ 1216 #define PULS_1300MS 7 /* 1.3 s to 2.7 s */ 1217 1218 #define PHY_M_LED_BLINK_RT(x) SHIFT8(x) /* Blink Rate */ 1219 1220 #define BLINK_42MS 0 /* 42 ms */ 1221 #define BLINK_84MS 1 /* 84 ms */ 1222 #define BLINK_170MS 2 /* 170 ms */ 1223 #define BLINK_340MS 3 /* 340 ms */ 1224 #define BLINK_670MS 4 /* 670 ms */ 1225 /* values 5 - 7: reserved */ 1226 1227 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ 1228 #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ 1229 #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ 1230 #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ 1231 #define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */ 1232 #define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ 1233 #define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ 1234 1235 #define MO_LED_NORM 0 1236 #define MO_LED_BLINK 1 1237 #define MO_LED_OFF 2 1238 #define MO_LED_ON 3 1239 1240 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ 1241 /* Bit 15.. 7: reserved */ 1242 #define PHY_M_EC2_FI_IMPED (1<<6) /* Bit 6: Fiber Input Impedance */ 1243 #define PHY_M_EC2_FO_IMPED (1<<5) /* Bit 5: Fiber Output Impedance */ 1244 #define PHY_M_EC2_FO_M_CLK (1<<4) /* Bit 4: Fiber Mode Clock Enable */ 1245 #define PHY_M_EC2_FO_BOOST (1<<3) /* Bit 3: Fiber Output Boost */ 1246 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ 1247 1248 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 1249 #define PHY_M_FC_AUTO_SEL (1<<15) /* Bit 15: Fiber/Copper Auto Sel. dis. */ 1250 #define PHY_M_FC_AN_REG_ACC (1<<14) /* Bit 14: Fiber/Copper Autoneg. reg acc */ 1251 #define PHY_M_FC_RESULUTION (1<<13) /* Bit 13: Fiber/Copper Resulution */ 1252 #define PHY_M_SER_IF_AN_BP (1<<12) /* Bit 12: Ser IF autoneg. bypass enable */ 1253 #define PHY_M_SER_IF_BP_ST (1<<11) /* Bit 11: Ser IF autoneg. bypass status */ 1254 #define PHY_M_IRQ_POLARITY (1<<10) /* Bit 10: IRQ polarity */ 1255 /* Bit 9..4: reserved */ 1256 #define PHY_M_UNDOC1 (1<< 7) /* undocumented bit !! */ 1257 #define PHY_M_MODE_MASK (0xf<<0)/* Bit 3..0: copy of HWCFG MODE[3:0] */ 1258 1259 1260 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ 1261 #define PHY_M_CABD_ENA_TEST (1<<15) /* Bit 15: Enable Test */ 1262 #define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status */ 1263 /* Bit 12.. 8: reserved */ 1264 #define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance */ 1265 1266 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ 1267 #define CABD_STAT_NORMAL 0 1268 #define CABD_STAT_SHORT 1 1269 #define CABD_STAT_OPEN 2 1270 #define CABD_STAT_FAIL 3 1271 1272 1273 /* 1274 * GMAC registers 1275 * 1276 * The GMAC registers are 16 or 32 bits wide. 1277 * The GMACs host processor interface is 16 bits wide, 1278 * therefore ALL registers will be addressed with 16 bit accesses. 1279 * 1280 * The following macros are provided to access the GMAC registers 1281 * GM_IN16(), GM_OUT16, GM_IN32(), GM_OUT32(), GM_INADR(), GM_OUTADR(), 1282 * GM_INHASH(), and GM_OUTHASH(). 1283 * The macros are defined in SkGeHw.h. 1284 * 1285 * Note: NA reg = Network Address e.g DA, SA etc. 1286 * 1287 */ 1288 1289 /* Port Registers */ 1290 #define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ 1291 #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ 1292 #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ 1293 #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ 1294 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */ 1295 #define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ 1296 #define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ 1297 1298 /* Source Address Registers */ 1299 #define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ 1300 #define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ 1301 #define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ 1302 #define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ 1303 #define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ 1304 #define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ 1305 1306 /* Multicast Address Hash Registers */ 1307 #define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ 1308 #define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ 1309 #define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ 1310 #define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ 1311 1312 /* Interrupt Source Registers */ 1313 #define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ 1314 #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ 1315 #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ 1316 1317 /* Interrupt Mask Registers */ 1318 #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ 1319 #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ 1320 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ 1321 1322 /* Serial Management Interface (SMI) Registers */ 1323 #define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ 1324 #define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ 1325 #define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ 1326 1327 /* MIB Counters */ 1328 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ 1329 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ 1330 1331 /* 1332 * MIB Counters base address definitions (low word) - 1333 * use offset 4 for access to high word (32 bit r/o) 1334 */ 1335 #define GM_RXF_UC_OK \ 1336 (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ 1337 #define GM_RXF_BC_OK \ 1338 (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ 1339 #define GM_RXF_MPAUSE \ 1340 (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ 1341 #define GM_RXF_MC_OK \ 1342 (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ 1343 #define GM_RXF_FCS_ERR \ 1344 (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ 1345 /* GM_MIB_CNT_BASE + 40: reserved */ 1346 #define GM_RXO_OK_LO \ 1347 (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ 1348 #define GM_RXO_OK_HI \ 1349 (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ 1350 #define GM_RXO_ERR_LO \ 1351 (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ 1352 #define GM_RXO_ERR_HI \ 1353 (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ 1354 #define GM_RXF_SHT \ 1355 (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ 1356 #define GM_RXE_FRAG \ 1357 (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */ 1358 #define GM_RXF_64B \ 1359 (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ 1360 #define GM_RXF_127B \ 1361 (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ 1362 #define GM_RXF_255B \ 1363 (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ 1364 #define GM_RXF_511B \ 1365 (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ 1366 #define GM_RXF_1023B \ 1367 (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ 1368 #define GM_RXF_1518B \ 1369 (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ 1370 #define GM_RXF_MAX_SZ \ 1371 (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ 1372 #define GM_RXF_LNG_ERR \ 1373 (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ 1374 #define GM_RXF_JAB_PKT \ 1375 (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ 1376 /* GM_MIB_CNT_BASE + 168: reserved */ 1377 #define GM_RXE_FIFO_OV \ 1378 (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ 1379 /* GM_MIB_CNT_BASE + 184: reserved */ 1380 #define GM_TXF_UC_OK \ 1381 (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ 1382 #define GM_TXF_BC_OK \ 1383 (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ 1384 #define GM_TXF_MPAUSE \ 1385 (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ 1386 #define GM_TXF_MC_OK \ 1387 (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ 1388 #define GM_TXO_OK_LO \ 1389 (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ 1390 #define GM_TXO_OK_HI \ 1391 (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ 1392 #define GM_TXF_64B \ 1393 (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ 1394 #define GM_TXF_127B \ 1395 (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ 1396 #define GM_TXF_255B \ 1397 (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ 1398 #define GM_TXF_511B \ 1399 (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ 1400 #define GM_TXF_1023B \ 1401 (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ 1402 #define GM_TXF_1518B \ 1403 (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ 1404 #define GM_TXF_MAX_SZ \ 1405 (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ 1406 /* GM_MIB_CNT_BASE + 296: reserved */ 1407 #define GM_TXF_COL \ 1408 (GM_MIB_CNT_BASE + 304) /* Tx Collision */ 1409 #define GM_TXF_LAT_COL \ 1410 (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ 1411 #define GM_TXF_ABO_COL \ 1412 (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ 1413 #define GM_TXF_MUL_COL \ 1414 (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ 1415 #define GM_TXF_SNG_COL \ 1416 (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ 1417 #define GM_TXE_FIFO_UR \ 1418 (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ 1419 1420 /*----------------------------------------------------------------------------*/ 1421 /* 1422 * GMAC Bit Definitions 1423 * 1424 * If the bit access behaviour differs from the register access behaviour 1425 * (r/w, r/o) this is documented after the bit number. 1426 * The following bit access behaviours are used: 1427 * (sc) self clearing 1428 * (r/o) read only 1429 */ 1430 1431 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ 1432 #define GM_GPSR_SPEED (1<<15) /* Bit 15: Port Speed (1 = 100 Mbps) */ 1433 #define GM_GPSR_DUPLEX (1<<14) /* Bit 14: Duplex Mode (1 = Full) */ 1434 #define GM_GPSR_FC_TX_DIS (1<<13) /* Bit 13: Tx Flow-Control Mode Disabled */ 1435 #define GM_GPSR_LINK_UP (1<<12) /* Bit 12: Link Up Status */ 1436 #define GM_GPSR_PAUSE (1<<11) /* Bit 11: Pause State */ 1437 #define GM_GPSR_TX_ACTIVE (1<<10) /* Bit 10: Tx in Progress */ 1438 #define GM_GPSR_EXC_COL (1<<9) /* Bit 9: Excessive Collisions Occured */ 1439 #define GM_GPSR_LAT_COL (1<<8) /* Bit 8: Late Collisions Occured */ 1440 /* Bit 7..6: reserved */ 1441 #define GM_GPSR_PHY_ST_CH (1<<5) /* Bit 5: PHY Status Change */ 1442 #define GM_GPSR_GIG_SPEED (1<<4) /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ 1443 #define GM_GPSR_PART_MODE (1<<3) /* Bit 3: Partition mode */ 1444 #define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow-Control Mode Disabled */ 1445 #define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */ 1446 /* Bit 0: reserved */ 1447 1448 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 1449 /* Bit 15: reserved */ 1450 #define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */ 1451 #define GM_GPCR_FC_TX_DIS (1<<13) /* Bit 13: Disable Tx Flow-Control Mode */ 1452 #define GM_GPCR_TX_ENA (1<<12) /* Bit 12: Enable Transmit */ 1453 #define GM_GPCR_RX_ENA (1<<11) /* Bit 11: Enable Receive */ 1454 #define GM_GPCR_BURST_ENA (1<<10) /* Bit 10: Enable Burst Mode */ 1455 #define GM_GPCR_LOOP_ENA (1<<9) /* Bit 9: Enable MAC Loopback Mode */ 1456 #define GM_GPCR_PART_ENA (1<<8) /* Bit 8: Enable Partition Mode */ 1457 #define GM_GPCR_GIGS_ENA (1<<7) /* Bit 7: Gigabit Speed (1000 Mbps) */ 1458 #define GM_GPCR_FL_PASS (1<<6) /* Bit 6: Force Link Pass */ 1459 #define GM_GPCR_DUP_FULL (1<<5) /* Bit 5: Full Duplex Mode */ 1460 #define GM_GPCR_FC_RX_DIS (1<<4) /* Bit 4: Disable Rx Flow-Control Mode */ 1461 #define GM_GPCR_SPEED_100 (1<<3) /* Bit 3: Port Speed 100 Mbps */ 1462 #define GM_GPCR_AU_DUP_DIS (1<<2) /* Bit 2: Disable Auto-Update Duplex */ 1463 #define GM_GPCR_AU_FCT_DIS (1<<1) /* Bit 1: Disable Auto-Update Flow-C. */ 1464 #define GM_GPCR_AU_SPD_DIS (1<<0) /* Bit 0: Disable Auto-Update Speed */ 1465 1466 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1467 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ 1468 GM_GPCR_AU_SPD_DIS) 1469 1470 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 1471 #define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */ 1472 #define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */ 1473 #define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */ 1474 #define GM_TXCR_COL_THR_MSK (1<<10) /* Bit 12..10: Collision Threshold */ 1475 1476 #define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) 1477 1478 #define TX_COL_DEF 0x04 1479 1480 /* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1481 #define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */ 1482 #define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */ 1483 #define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */ 1484 #define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */ 1485 1486 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 1487 #define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */ 1488 #define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */ 1489 #define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8..4: IPG Jam to Data */ 1490 /* Bit 3..0: reserved */ 1491 1492 #define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) 1493 #define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) 1494 #define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) 1495 1496 #define TX_JAM_LEN_DEF 0x03 1497 #define TX_JAM_IPG_DEF 0x0b 1498 #define TX_IPG_JAM_DEF 0x1c 1499 1500 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ 1501 #define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder (r/o) */ 1502 #define GM_SMOD_LIMIT_4 (1<<10) /* Bit 10: 4 consecutive Tx trials */ 1503 #define GM_SMOD_VLAN_ENA (1<<9) /* Bit 9: Enable VLAN (Max. Frame Len) */ 1504 #define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Len) */ 1505 /* Bit 7..5: reserved */ 1506 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ 1507 1508 #define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK) 1509 #define DATA_BLIND_DEF 0x04 1510 1511 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK) 1512 #define IPG_DATA_DEF 0x1e 1513 1514 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 1515 #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ 1516 #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ 1517 #define GM_SMI_CT_OP_RD (1<<5) /* Bit 5: OpCode Read (0=Write)*/ 1518 #define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */ 1519 #define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */ 1520 /* Bit 2..0: reserved */ 1521 1522 #define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) 1523 #define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) 1524 1525 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ 1526 /* Bit 15..6: reserved */ 1527 #define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */ 1528 #define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */ 1529 /* Bit 3..0: reserved */ 1530 1531 /* Receive Frame Status Encoding */ 1532 #define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */ 1533 /* Bit 15..14: reserved */ 1534 #define GMR_FS_VLAN (1L<<13) /* Bit 13: VLAN Packet */ 1535 #define GMR_FS_JABBER (1L<<12) /* Bit 12: Jabber Packet */ 1536 #define GMR_FS_UN_SIZE (1L<<11) /* Bit 11: Undersize Packet */ 1537 #define GMR_FS_MC (1L<<10) /* Bit 10: Multicast Packet */ 1538 #define GMR_FS_BC (1L<<9) /* Bit 9: Broadcast Packet */ 1539 #define GMR_FS_RX_OK (1L<<8) /* Bit 8: Receive OK (Good Packet) */ 1540 #define GMR_FS_GOOD_FC (1L<<7) /* Bit 7: Good Flow-Control Packet */ 1541 #define GMR_FS_BAD_FC (1L<<6) /* Bit 6: Bad Flow-Control Packet */ 1542 #define GMR_FS_MII_ERR (1L<<5) /* Bit 5: MII Error */ 1543 #define GMR_FS_LONG_ERR (1L<<4) /* Bit 4: Too Long Packet */ 1544 #define GMR_FS_FRAGMENT (1L<<3) /* Bit 3: Fragment */ 1545 /* Bit 2: reserved */ 1546 #define GMR_FS_CRC_ERR (1L<<1) /* Bit 1: CRC Error */ 1547 #define GMR_FS_RX_FF_OV (1L<<0) /* Bit 0: Rx FIFO Overflow */ 1548 1549 /* 1550 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR) 1551 */ 1552 #define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \ 1553 GMR_FS_LONG_ERR | \ 1554 GMR_FS_MII_ERR | \ 1555 GMR_FS_BAD_FC | \ 1556 GMR_FS_GOOD_FC | \ 1557 GMR_FS_JABBER) 1558 1559 /* Rx GMAC FIFO Flush Mask (default) */ 1560 #define RX_FF_FL_DEF_MSK (GMR_FS_CRC_ERR | \ 1561 GMR_FS_RX_FF_OV | \ 1562 GMR_FS_MII_ERR | \ 1563 GMR_FS_BAD_FC | \ 1564 GMR_FS_GOOD_FC | \ 1565 GMR_FS_UN_SIZE | \ 1566 GMR_FS_JABBER) 1567 1568 /* typedefs *******************************************************************/ 1569 1570 1571 /* function prototypes ********************************************************/ 1572 1573 #ifdef __cplusplus 1574 } 1575 #endif /* __cplusplus */ 1576 1577 #endif /* __INC_XMAC_H */ 1578