1 /******************************************************************************* 2 3 4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 2 of the License, or (at your option) 9 any later version. 10 11 This program is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 59 18 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 20 The full GNU General Public License is included in this distribution in the 21 file called LICENSE. 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 *******************************************************************************/ 27 28 #ifndef _E100_PHY_INC_ 29 #define _E100_PHY_INC_ 30 31 #include "e100.h" 32 33 /* 34 * Auto-polarity enable/disable 35 * e100_autopolarity = 0 => disable auto-polarity 36 * e100_autopolarity = 1 => enable auto-polarity 37 * e100_autopolarity = 2 => let software determine 38 */ 39 #define E100_AUTOPOLARITY 2 40 41 #define IS_NC3133(bdp) (((bdp)->pdev->subsystem_vendor == 0x0E11) && \ 42 ((bdp)->pdev->subsystem_device == 0xB0E1)) 43 44 #define PHY_503 0 45 #define PHY_100_A 0x000003E0 46 #define PHY_100_C 0x035002A8 47 #define PHY_NSC_TX 0x5c002000 48 #define PHY_82562ET 0x033002A8 49 #define PHY_82562EM 0x032002A8 50 #define PHY_82562EH 0x017002A8 51 #define PHY_82555_TX 0x015002a8 /* added this for 82555 */ 52 #define PHY_OTHER 0xFFFF 53 #define MAX_PHY_ADDR 31 54 #define MIN_PHY_ADDR 0 55 56 #define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF 57 58 #define PHY_DEFAULT_ADDRESS 1 59 #define PHY_ADDRESS_503 32 60 61 /* MDI Control register bit definitions */ 62 #define MDI_PHY_READY BIT_28 /* PHY is ready for next MDI cycle */ 63 64 #define MDI_NC3133_CONFIG_REG 0x19 65 #define MDI_NC3133_100FX_ENABLE BIT_2 66 #define MDI_NC3133_INT_ENABLE_REG 0x17 67 #define MDI_NC3133_INT_ENABLE BIT_1 68 69 /* MDI Control register opcode definitions */ 70 #define MDI_WRITE 1 /* Phy Write */ 71 #define MDI_READ 2 /* Phy read */ 72 73 /* MDI register set*/ 74 #define AUTO_NEG_NEXT_PAGE_REG 0x07 /* Auto-negotiation next page xmit */ 75 #define EXTENDED_REG_0 0x10 /* Extended reg 0 (Phy 100 modes) */ 76 #define EXTENDED_REG_1 0x14 /* Extended reg 1 (Phy 100 error indications) */ 77 #define NSC_CONG_CONTROL_REG 0x17 /* National (TX) congestion control */ 78 #define NSC_SPEED_IND_REG 0x19 /* National (TX) speed indication */ 79 80 #define HWI_CONTROL_REG 0x1D /* HWI Control register */ 81 /* MDI/MDI-X Control Register bit definitions */ 82 #define MDI_MDIX_RES_TIMER BIT_0_3 /* minimum slot time for resolution timer */ 83 #define MDI_MDIX_CONFIG_IS_OK BIT_4 /* 1 = resolution algorithm completes OK */ 84 #define MDI_MDIX_STATUS BIT_5 /* 1 = MDIX (croos over), 0 = MDI (straight through) */ 85 #define MDI_MDIX_SWITCH BIT_6 /* 1 = Forces to MDIX, 0 = Forces to MDI */ 86 #define MDI_MDIX_AUTO_SWITCH_ENABLE BIT_7 /* 1 = MDI/MDI-X feature enabled */ 87 #define MDI_MDIX_CONCT_CONFIG BIT_8 /* Sets the MDI/MDI-X connectivity configuration (test prupose only) */ 88 #define MDI_MDIX_CONCT_TEST_ENABLE BIT_9 /* 1 = Enables connectivity testing */ 89 #define MDI_MDIX_RESET_ALL_MASK 0x0000 90 91 /* HWI Control Register bit definitions */ 92 #define HWI_TEST_DISTANCE BIT_0_8 /* distance to cable problem */ 93 #define HWI_TEST_HIGHZ_PROBLEM BIT_9 /* 1 = Open Circuit */ 94 #define HWI_TEST_LOWZ_PROBLEM BIT_10 /* 1 = Short Circuit */ 95 #define HWI_TEST_RESERVED (BIT_11 | BIT_12) /* reserved */ 96 #define HWI_TEST_EXECUTE BIT_13 /* 1 = Execute the HWI test on the PHY */ 97 #define HWI_TEST_ABILITY BIT_14 /* 1 = test passed */ 98 #define HWI_TEST_ENABLE BIT_15 /* 1 = Enables the HWI feature */ 99 #define HWI_RESET_ALL_MASK 0x0000 100 101 /* ############Start of 82555 specific defines################## */ 102 103 /* Intel 82555 specific registers */ 104 #define PHY_82555_CSR 0x10 /* 82555 CSR */ 105 #define PHY_82555_SPECIAL_CONTROL 0x11 /* 82555 special control register */ 106 107 #define PHY_82555_RCV_ERR 0x15 /* 82555 100BaseTx Receive Error 108 * Frame Counter */ 109 #define PHY_82555_SYMBOL_ERR 0x16 /* 82555 RCV Symbol Error Counter */ 110 #define PHY_82555_PREM_EOF_ERR 0x17 /* 82555 100BaseTx RCV Premature End 111 * of Frame Error Counter */ 112 #define PHY_82555_EOF_COUNTER 0x18 /* 82555 end of frame error counter */ 113 #define PHY_82555_MDI_EQUALIZER_CSR 0x1a /* 82555 specific equalizer reg. */ 114 115 /* 82555 CSR bits */ 116 #define PHY_82555_SPEED_BIT BIT_1 117 #define PHY_82555_POLARITY_BIT BIT_8 118 119 /* 82555 equalizer reg. opcodes */ 120 #define ENABLE_ZERO_FORCING 0x2010 /* write to ASD conf. reg. 0 */ 121 #define DISABLE_ZERO_FORCING 0x2000 /* write to ASD conf. reg. 0 */ 122 123 /* 82555 special control reg. opcodes */ 124 #define DISABLE_AUTO_POLARITY 0x0010 125 #define EXTENDED_SQUELCH_BIT BIT_2 126 127 /* ############End of 82555 specific defines##################### */ 128 129 /* Auto-Negotiation advertisement register bit definitions*/ 130 #define NWAY_AD_FC_SUPPORTED 0x0400 /* Flow Control supported */ 131 132 /* Auto-Negotiation link partner ability register bit definitions*/ 133 #define NWAY_LP_ABILITY 0x07e0 /* technologies supported */ 134 135 /* PHY 100 Extended Register 0 bit definitions*/ 136 #define PHY_100_ER0_FDX_INDIC BIT_0 /* 1 = FDX, 0 = half duplex */ 137 #define PHY_100_ER0_SPEED_INDIC BIT_1 /* 1 = 100Mbps, 0= 10Mbps */ 138 139 /* National Semiconductor TX phy congestion control register bit definitions*/ 140 #define NSC_TX_CONG_TXREADY BIT_10 /* Makes TxReady an input */ 141 #define NSC_TX_CONG_ENABLE BIT_8 /* Enables congestion control */ 142 143 /* National Semiconductor TX phy speed indication register bit definitions*/ 144 #define NSC_TX_SPD_INDC_SPEED BIT_6 /* 0 = 100Mbps, 1=10Mbps */ 145 146 /************* function prototypes ************/ 147 extern unsigned char e100_phy_init(struct e100_private *bdp); 148 extern unsigned char e100_update_link_state(struct e100_private *bdp); 149 extern unsigned char e100_phy_check(struct e100_private *bdp); 150 extern void e100_phy_set_speed_duplex(struct e100_private *bdp, 151 unsigned char force_restart); 152 extern void e100_phy_autoneg(struct e100_private *bdp); 153 extern void e100_phy_reset(struct e100_private *bdp); 154 extern void e100_phy_set_loopback(struct e100_private *bdp); 155 extern int e100_mdi_write(struct e100_private *, u32, u32, u16); 156 extern int e100_mdi_read(struct e100_private *, u32, u32, u16 *); 157 158 #endif 159