1 #ifndef __ASM_SH_PGTABLE_H
2 #define __ASM_SH_PGTABLE_H
3
4 /* Copyright (C) 1999 Niibe Yutaka */
5
6 #include <asm/pgtable-2level.h>
7
8 /*
9 * This file contains the functions and defines necessary to modify and use
10 * the SuperH page table tree.
11 */
12 #ifndef __ASSEMBLY__
13 #include <asm/processor.h>
14 #include <asm/addrspace.h>
15 #include <linux/threads.h>
16
17 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
18 extern void paging_init(void);
19
20 #if defined(__sh3__)
21 /* Cache flushing:
22 *
23 * - flush_cache_all() flushes entire cache
24 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
25 * - flush_cache_page(mm, vmaddr) flushes a single page
26 * - flush_cache_range(mm, start, end) flushes a range of pages
27 *
28 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
29 * - flush_page_to_ram(page) write back kernel page to ram
30 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
31 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
32 *
33 * Caches are indexed (effectively) by physical address on SH-3, so
34 * we don't need them.
35 */
36 #define flush_cache_all() do { } while (0)
37 #define flush_cache_mm(mm) do { } while (0)
38 #define flush_cache_range(mm, start, end) do { } while (0)
39 #define flush_cache_page(vma, vmaddr) do { } while (0)
40 #define flush_page_to_ram(page) do { } while (0)
41 #define flush_dcache_page(page) do { } while (0)
42 #define flush_icache_range(start, end) do { } while (0)
43 #define flush_icache_page(vma,pg) do { } while (0)
44 #define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
45 #define flush_cache_sigtramp(vaddr) do { } while (0)
46 #define __flush_icache_all() do { } while (0)
47
48 #define p3_cache_init() do { } while (0)
49
50 #elif defined(__SH4__)
51 /*
52 * Caches are broken on SH-4, so we need them.
53 */
54
55 /* Page is 4K, OC size is 16K, there are four lines. */
56 #define CACHE_ALIAS 0x00003000
57
58 extern void flush_cache_all(void);
59 extern void flush_cache_mm(struct mm_struct *mm);
60 extern void flush_cache_range(struct mm_struct *mm, unsigned long start,
61 unsigned long end);
62 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr);
63 extern void flush_dcache_page(struct page *pg);
64 extern void flush_icache_range(unsigned long start, unsigned long end);
65 extern void flush_cache_sigtramp(unsigned long addr);
66
67 #define flush_page_to_ram(page) do { } while (0)
68 #define flush_icache_page(vma,pg) do { } while (0)
69 #define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
70
71 /* Initialization of P3 area for copy_user_page */
72 extern void p3_cache_init(void);
73
74 #define PG_mapped PG_arch_1
75
76 /* We provide our own get_unmapped_area to avoid cache alias issue */
77 #define HAVE_ARCH_UNMAPPED_AREA
78 #endif
79
80 /* Flush (write-back only) a region (smaller than a page) */
81 extern void __flush_wback_region(void *start, int size);
82 /* Flush (write-back & invalidate) a region (smaller than a page) */
83 extern void __flush_purge_region(void *start, int size);
84 /* Flush (invalidate only) a region (smaller than a page) */
85 extern void __flush_invalidate_region(void *start, int size);
86
87
88 /*
89 * Basically we have the same two-level (which is the logical three level
90 * Linux page table layout folded) page tables as the i386.
91 */
92
93 /*
94 * ZERO_PAGE is a global shared page that is always zero: used
95 * for zero-mapped memory areas etc..
96 */
97 extern unsigned long empty_zero_page[1024];
98 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
99
100 #endif /* !__ASSEMBLY__ */
101
102 #define __beep() asm("")
103
104 #define PMD_SIZE (1UL << PMD_SHIFT)
105 #define PMD_MASK (~(PMD_SIZE-1))
106 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
107 #define PGDIR_MASK (~(PGDIR_SIZE-1))
108
109 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
110 #define FIRST_USER_PGD_NR 0
111
112 #define PTE_PHYS_MASK 0x1ffff000
113
114 #ifndef __ASSEMBLY__
115 /*
116 * First 1MB map is used by fixed purpose.
117 * Currently only 4-enty (16kB) is used (see arch/sh/mm/cache.c)
118 */
119 #define VMALLOC_START (P3SEG+0x00100000)
120 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
121 #define VMALLOC_END P4SEG
122
123 /* 0x001 WT-bit on SH-4, 0 on SH-3 */
124 #define _PAGE_HW_SHARED 0x002 /* SH-bit : page is shared among processes */
125 #define _PAGE_DIRTY 0x004 /* D-bit : page changed */
126 #define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
127 /* 0x010 SZ0-bit : Size of page */
128 #define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
129 #define _PAGE_USER 0x040 /* PR1-bit : user space access allowed */
130 /* 0x080 SZ1-bit : Size of page (on SH-4) */
131 #define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
132 #define _PAGE_PROTNONE 0x200 /* software: if not present */
133 #define _PAGE_ACCESSED 0x400 /* software: page referenced */
134 #define _PAGE_U0_SHARED 0x800 /* software: page is shared in user space */
135
136
137 /* software: moves to PTEA.TC (Timing Control) */
138 #define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
139 #define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */
140
141 /* software: moves to PTEA.SA[2:0] (Space Attributes) */
142 #define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */
143 #define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */
144 #define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */
145 #define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */
146 #define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */
147 #define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
148 #define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
149
150
151 /* Mask which drop software flags */
152 #if defined(__sh3__)
153 /*
154 * MMU on SH-3 has bug on SH-bit: We can't use it if MMUCR.IX=1.
155 * Work around: Just drop SH-bit.
156 */
157 #define _PAGE_FLAGS_HARDWARE_MASK 0x1ffff1fc
158 #else
159 #define _PAGE_FLAGS_HARDWARE_MASK 0x1ffff1fe
160 #endif
161 /* Hardware flags: SZ=1 (4k-byte) */
162 #define _PAGE_FLAGS_HARD 0x00000010
163
164 #define _PAGE_SHARED _PAGE_U0_SHARED
165
166 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
167 #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
168 #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_SHARED)
169
170 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_FLAGS_HARD)
171 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_SHARED | _PAGE_FLAGS_HARD)
172 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
173 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
174 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
175 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
176 #define PAGE_KERNEL_PCC(slot, type) \
177 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_FLAGS_HARD | (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | (type))
178
179 /*
180 * As i386 and MIPS, SuperH can't do page protection for execute, and
181 * considers that the same as a read. Also, write permissions imply
182 * read permissions. This is the closest we can get..
183 */
184
185 #define __P000 PAGE_NONE
186 #define __P001 PAGE_READONLY
187 #define __P010 PAGE_COPY
188 #define __P011 PAGE_COPY
189 #define __P100 PAGE_READONLY
190 #define __P101 PAGE_READONLY
191 #define __P110 PAGE_COPY
192 #define __P111 PAGE_COPY
193
194 #define __S000 PAGE_NONE
195 #define __S001 PAGE_READONLY
196 #define __S010 PAGE_SHARED
197 #define __S011 PAGE_SHARED
198 #define __S100 PAGE_READONLY
199 #define __S101 PAGE_READONLY
200 #define __S110 PAGE_SHARED
201 #define __S111 PAGE_SHARED
202
203 #define pte_none(x) (!pte_val(x))
204 #define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
205 #define pte_clear(xp) do { set_pte(xp, __pte(0)); } while (0)
206
207 #define pmd_none(x) (!pmd_val(x))
208 #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
209 #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
210 #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
211
212 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
213 #define pte_page(x) phys_to_page(pte_val(x)&PTE_PHYS_MASK)
214
215 /*
216 * The following only work if pte_present() is true.
217 * Undefined behaviour if not..
218 */
pte_read(pte_t pte)219 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
pte_exec(pte_t pte)220 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
pte_dirty(pte_t pte)221 static inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; }
pte_young(pte_t pte)222 static inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; }
pte_write(pte_t pte)223 static inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_RW; }
pte_not_present(pte_t pte)224 static inline int pte_not_present(pte_t pte){ return !(pte_val(pte) & _PAGE_PRESENT); }
225
pte_rdprotect(pte_t pte)226 static inline pte_t pte_rdprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
pte_exprotect(pte_t pte)227 static inline pte_t pte_exprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; }
pte_mkclean(pte_t pte)228 static inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
pte_mkold(pte_t pte)229 static inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
pte_wrprotect(pte_t pte)230 static inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_RW)); return pte; }
pte_mkread(pte_t pte)231 static inline pte_t pte_mkread(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
pte_mkexec(pte_t pte)232 static inline pte_t pte_mkexec(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; }
pte_mkdirty(pte_t pte)233 static inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
pte_mkyoung(pte_t pte)234 static inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
pte_mkwrite(pte_t pte)235 static inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; }
236
237 /*
238 * Conversion functions: convert a page and protection to a page entry,
239 * and a page entry and page directory to the page they refer to.
240 *
241 * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
242 */
243 #define mk_pte(page,pgprot) \
244 ({ pte_t __pte; \
245 \
246 set_pte(&__pte, __pte(PHYSADDR(page_address(page)) \
247 +pgprot_val(pgprot))); \
248 __pte; \
249 })
250
251 /* This takes a physical page address that is used by the remapping functions */
252 #define mk_pte_phys(physpage, pgprot) \
253 ({ pte_t __pte; set_pte(&__pte, __pte(physpage + pgprot_val(pgprot))); __pte; })
254
pte_modify(pte_t pte,pgprot_t newprot)255 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
256 { set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
257
258 #define page_pte(page) page_pte_prot(page, __pgprot(0))
259
260 #define pmd_page(pmd) \
261 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
262
263 /* to find an entry in a page-table-directory. */
264 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
265 #define __pgd_offset(address) pgd_index(address)
266 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
267
268 /* to find an entry in a kernel page-table-directory */
269 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
270
271 /* Find an entry in the third-level page table.. */
272 #define __pte_offset(address) \
273 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
274 #define pte_offset(dir, address) ((pte_t *) pmd_page(*(dir)) + \
275 __pte_offset(address))
276
277 extern void update_mmu_cache(struct vm_area_struct * vma,
278 unsigned long address, pte_t pte);
279
280 /* Encode and de-code a swap entry */
281 /*
282 * NOTE: We should set ZEROs at the position of _PAGE_PRESENT
283 * and _PAGE_PROTONOE bits
284 */
285 #define SWP_TYPE(x) ((x).val & 0xff)
286 #define SWP_OFFSET(x) ((x).val >> 10)
287 #define SWP_ENTRY(type, offset) ((swp_entry_t) { (type) | ((offset) << 10) })
288 #define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
289 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
290
291 /*
292 * Routines for update of PTE
293 *
294 * We just can use generic implementation, as SuperH has no SMP feature.
295 * (We needed atomic implementation for SMP)
296 *
297 */
298
299 #define pte_same(A,B) (pte_val(A) == pte_val(B))
300
301 #endif /* !__ASSEMBLY__ */
302
303 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
304 #define PageSkip(page) (0)
305 #define kern_addr_valid(addr) (1)
306
307 #define io_remap_page_range remap_page_range
308
309 /*
310 * No page table caches to initialise
311 */
312 #define pgtable_cache_init() do { } while (0)
313
314 /*
315 * Set pg flags to non-cached
316 */
317 #define pgprot_noncached(_prot) __pgprot(pgprot_val(_prot) &= ~_PAGE_CACHABLE)
318
319
320 #endif /* __ASM_SH_PAGE_H */
321