1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
3 */
4
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
7
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
12 #include <net/dsa.h>
13
14 /* Port Group IDs (PGID) are masks of destination ports.
15 *
16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
17 * frame, and forwards the frame to the ports that are present in the logical
18 * AND of all 3 PGIDs.
19 *
20 * These PGID lookups are:
21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
22 * which the switch selects a destination PGID:
23 * - The {DMAC, VID} is present in the MAC table. In that case, the
24 * destination PGID is given by the DEST_IDX field of the MAC table entry
25 * that matched.
26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
27 * frame is disseminated as being either unicast, multicast or broadcast,
28 * and according to that, the destination PGID is chosen as being the
29 * value contained by ANA_FLOODING_FLD_UNICAST,
30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
31 * The destination PGID can be an unicast set: the first PGIDs, 0 to
32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
34 * a physical port and has a single bit set in the destination ports mask:
35 * that corresponding to the port number itself. In contrast, a multicast
36 * PGID will have potentially more than one single bit set in the destination
37 * ports mask.
38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
39 * dissects each frame and generates a 4-bit Link Aggregation Code which is
40 * used for this second PGID table lookup. The goal of link aggregation is to
41 * hash multiple flows within the same LAG on to different destination ports.
42 * The first lookup will result in a PGID with all the LAG members present in
43 * the destination ports mask, and the second lookup, by Link Aggregation
44 * Code, will ensure that each flow gets forwarded only to a single port out
45 * of that mask (there are no duplicates).
46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
47 * is indexed with the ingress port (plus 80). These PGIDs answer the
48 * question "is port i allowed to forward traffic to port j?" If yes, then
49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
51 */
52
53 /* Reserve some destination PGIDs at the end of the range:
54 * PGID_BLACKHOLE: used for not forwarding the frames
55 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
56 * of the switch port net devices, towards the CPU port module.
57 * PGID_UC: the flooding destinations for unknown unicast traffic.
58 * PGID_MC: the flooding destinations for non-IP multicast traffic.
59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
61 * PGID_BC: the flooding destinations for broadcast traffic.
62 */
63 #define PGID_BLACKHOLE 57
64 #define PGID_CPU 58
65 #define PGID_UC 59
66 #define PGID_MC 60
67 #define PGID_MCIPV4 61
68 #define PGID_MCIPV6 62
69 #define PGID_BC 63
70
71 #define for_each_unicast_dest_pgid(ocelot, pgid) \
72 for ((pgid) = 0; \
73 (pgid) < (ocelot)->num_phys_ports; \
74 (pgid)++)
75
76 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \
77 for ((pgid) = (ocelot)->num_phys_ports + 1; \
78 (pgid) < PGID_BLACKHOLE; \
79 (pgid)++)
80
81 #define for_each_aggr_pgid(ocelot, pgid) \
82 for ((pgid) = PGID_AGGR; \
83 (pgid) < PGID_SRC; \
84 (pgid)++)
85
86 /* Aggregation PGIDs, one per Link Aggregation Code */
87 #define PGID_AGGR 64
88
89 /* Source PGIDs, one per physical port */
90 #define PGID_SRC 80
91
92 #define OCELOT_NUM_TC 8
93
94 #define OCELOT_SPEED_2500 0
95 #define OCELOT_SPEED_1000 1
96 #define OCELOT_SPEED_100 2
97 #define OCELOT_SPEED_10 3
98
99 #define OCELOT_PTP_PINS_NUM 4
100
101 #define TARGET_OFFSET 24
102 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
103 #define REG(reg, offset) [reg & REG_MASK] = offset
104
105 #define REG_RESERVED_ADDR 0xffffffff
106 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
107
108 enum ocelot_target {
109 ANA = 1,
110 QS,
111 QSYS,
112 REW,
113 SYS,
114 S0,
115 S1,
116 S2,
117 HSIO,
118 PTP,
119 FDMA,
120 GCB,
121 DEV_GMII,
122 TARGET_MAX,
123 };
124
125 enum ocelot_reg {
126 ANA_ADVLEARN = ANA << TARGET_OFFSET,
127 ANA_VLANMASK,
128 ANA_PORT_B_DOMAIN,
129 ANA_ANAGEFIL,
130 ANA_ANEVENTS,
131 ANA_STORMLIMIT_BURST,
132 ANA_STORMLIMIT_CFG,
133 ANA_ISOLATED_PORTS,
134 ANA_COMMUNITY_PORTS,
135 ANA_AUTOAGE,
136 ANA_MACTOPTIONS,
137 ANA_LEARNDISC,
138 ANA_AGENCTRL,
139 ANA_MIRRORPORTS,
140 ANA_EMIRRORPORTS,
141 ANA_FLOODING,
142 ANA_FLOODING_IPMC,
143 ANA_SFLOW_CFG,
144 ANA_PORT_MODE,
145 ANA_CUT_THRU_CFG,
146 ANA_PGID_PGID,
147 ANA_TABLES_ANMOVED,
148 ANA_TABLES_MACHDATA,
149 ANA_TABLES_MACLDATA,
150 ANA_TABLES_STREAMDATA,
151 ANA_TABLES_MACACCESS,
152 ANA_TABLES_MACTINDX,
153 ANA_TABLES_VLANACCESS,
154 ANA_TABLES_VLANTIDX,
155 ANA_TABLES_ISDXACCESS,
156 ANA_TABLES_ISDXTIDX,
157 ANA_TABLES_ENTRYLIM,
158 ANA_TABLES_PTP_ID_HIGH,
159 ANA_TABLES_PTP_ID_LOW,
160 ANA_TABLES_STREAMACCESS,
161 ANA_TABLES_STREAMTIDX,
162 ANA_TABLES_SEQ_HISTORY,
163 ANA_TABLES_SEQ_MASK,
164 ANA_TABLES_SFID_MASK,
165 ANA_TABLES_SFIDACCESS,
166 ANA_TABLES_SFIDTIDX,
167 ANA_MSTI_STATE,
168 ANA_OAM_UPM_LM_CNT,
169 ANA_SG_ACCESS_CTRL,
170 ANA_SG_CONFIG_REG_1,
171 ANA_SG_CONFIG_REG_2,
172 ANA_SG_CONFIG_REG_3,
173 ANA_SG_CONFIG_REG_4,
174 ANA_SG_CONFIG_REG_5,
175 ANA_SG_GCL_GS_CONFIG,
176 ANA_SG_GCL_TI_CONFIG,
177 ANA_SG_STATUS_REG_1,
178 ANA_SG_STATUS_REG_2,
179 ANA_SG_STATUS_REG_3,
180 ANA_PORT_VLAN_CFG,
181 ANA_PORT_DROP_CFG,
182 ANA_PORT_QOS_CFG,
183 ANA_PORT_VCAP_CFG,
184 ANA_PORT_VCAP_S1_KEY_CFG,
185 ANA_PORT_VCAP_S2_CFG,
186 ANA_PORT_PCP_DEI_MAP,
187 ANA_PORT_CPU_FWD_CFG,
188 ANA_PORT_CPU_FWD_BPDU_CFG,
189 ANA_PORT_CPU_FWD_GARP_CFG,
190 ANA_PORT_CPU_FWD_CCM_CFG,
191 ANA_PORT_PORT_CFG,
192 ANA_PORT_POL_CFG,
193 ANA_PORT_PTP_CFG,
194 ANA_PORT_PTP_DLY1_CFG,
195 ANA_PORT_PTP_DLY2_CFG,
196 ANA_PORT_SFID_CFG,
197 ANA_PFC_PFC_CFG,
198 ANA_PFC_PFC_TIMER,
199 ANA_IPT_OAM_MEP_CFG,
200 ANA_IPT_IPT,
201 ANA_PPT_PPT,
202 ANA_FID_MAP_FID_MAP,
203 ANA_AGGR_CFG,
204 ANA_CPUQ_CFG,
205 ANA_CPUQ_CFG2,
206 ANA_CPUQ_8021_CFG,
207 ANA_DSCP_CFG,
208 ANA_DSCP_REWR_CFG,
209 ANA_VCAP_RNG_TYPE_CFG,
210 ANA_VCAP_RNG_VAL_CFG,
211 ANA_VRAP_CFG,
212 ANA_VRAP_HDR_DATA,
213 ANA_VRAP_HDR_MASK,
214 ANA_DISCARD_CFG,
215 ANA_FID_CFG,
216 ANA_POL_PIR_CFG,
217 ANA_POL_CIR_CFG,
218 ANA_POL_MODE_CFG,
219 ANA_POL_PIR_STATE,
220 ANA_POL_CIR_STATE,
221 ANA_POL_STATE,
222 ANA_POL_FLOWC,
223 ANA_POL_HYST,
224 ANA_POL_MISC_CFG,
225 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
226 QS_XTR_RD,
227 QS_XTR_FRM_PRUNING,
228 QS_XTR_FLUSH,
229 QS_XTR_DATA_PRESENT,
230 QS_XTR_CFG,
231 QS_INJ_GRP_CFG,
232 QS_INJ_WR,
233 QS_INJ_CTRL,
234 QS_INJ_STATUS,
235 QS_INJ_ERR,
236 QS_INH_DBG,
237 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
238 QSYS_SWITCH_PORT_MODE,
239 QSYS_STAT_CNT_CFG,
240 QSYS_EEE_CFG,
241 QSYS_EEE_THRES,
242 QSYS_IGR_NO_SHARING,
243 QSYS_EGR_NO_SHARING,
244 QSYS_SW_STATUS,
245 QSYS_EXT_CPU_CFG,
246 QSYS_PAD_CFG,
247 QSYS_CPU_GROUP_MAP,
248 QSYS_QMAP,
249 QSYS_ISDX_SGRP,
250 QSYS_TIMED_FRAME_ENTRY,
251 QSYS_TFRM_MISC,
252 QSYS_TFRM_PORT_DLY,
253 QSYS_TFRM_TIMER_CFG_1,
254 QSYS_TFRM_TIMER_CFG_2,
255 QSYS_TFRM_TIMER_CFG_3,
256 QSYS_TFRM_TIMER_CFG_4,
257 QSYS_TFRM_TIMER_CFG_5,
258 QSYS_TFRM_TIMER_CFG_6,
259 QSYS_TFRM_TIMER_CFG_7,
260 QSYS_TFRM_TIMER_CFG_8,
261 QSYS_RED_PROFILE,
262 QSYS_RES_QOS_MODE,
263 QSYS_RES_CFG,
264 QSYS_RES_STAT,
265 QSYS_EGR_DROP_MODE,
266 QSYS_EQ_CTRL,
267 QSYS_EVENTS_CORE,
268 QSYS_QMAXSDU_CFG_0,
269 QSYS_QMAXSDU_CFG_1,
270 QSYS_QMAXSDU_CFG_2,
271 QSYS_QMAXSDU_CFG_3,
272 QSYS_QMAXSDU_CFG_4,
273 QSYS_QMAXSDU_CFG_5,
274 QSYS_QMAXSDU_CFG_6,
275 QSYS_QMAXSDU_CFG_7,
276 QSYS_PREEMPTION_CFG,
277 QSYS_CIR_CFG,
278 QSYS_EIR_CFG,
279 QSYS_SE_CFG,
280 QSYS_SE_DWRR_CFG,
281 QSYS_SE_CONNECT,
282 QSYS_SE_DLB_SENSE,
283 QSYS_CIR_STATE,
284 QSYS_EIR_STATE,
285 QSYS_SE_STATE,
286 QSYS_HSCH_MISC_CFG,
287 QSYS_TAG_CONFIG,
288 QSYS_TAS_PARAM_CFG_CTRL,
289 QSYS_PORT_MAX_SDU,
290 QSYS_PARAM_CFG_REG_1,
291 QSYS_PARAM_CFG_REG_2,
292 QSYS_PARAM_CFG_REG_3,
293 QSYS_PARAM_CFG_REG_4,
294 QSYS_PARAM_CFG_REG_5,
295 QSYS_GCL_CFG_REG_1,
296 QSYS_GCL_CFG_REG_2,
297 QSYS_PARAM_STATUS_REG_1,
298 QSYS_PARAM_STATUS_REG_2,
299 QSYS_PARAM_STATUS_REG_3,
300 QSYS_PARAM_STATUS_REG_4,
301 QSYS_PARAM_STATUS_REG_5,
302 QSYS_PARAM_STATUS_REG_6,
303 QSYS_PARAM_STATUS_REG_7,
304 QSYS_PARAM_STATUS_REG_8,
305 QSYS_PARAM_STATUS_REG_9,
306 QSYS_GCL_STATUS_REG_1,
307 QSYS_GCL_STATUS_REG_2,
308 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
309 REW_TAG_CFG,
310 REW_PORT_CFG,
311 REW_DSCP_CFG,
312 REW_PCP_DEI_QOS_MAP_CFG,
313 REW_PTP_CFG,
314 REW_PTP_DLY1_CFG,
315 REW_RED_TAG_CFG,
316 REW_DSCP_REMAP_DP1_CFG,
317 REW_DSCP_REMAP_CFG,
318 REW_STAT_CFG,
319 REW_REW_STICKY,
320 REW_PPT,
321 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
322 SYS_COUNT_RX_UNICAST,
323 SYS_COUNT_RX_MULTICAST,
324 SYS_COUNT_RX_BROADCAST,
325 SYS_COUNT_RX_SHORTS,
326 SYS_COUNT_RX_FRAGMENTS,
327 SYS_COUNT_RX_JABBERS,
328 SYS_COUNT_RX_CRC_ALIGN_ERRS,
329 SYS_COUNT_RX_SYM_ERRS,
330 SYS_COUNT_RX_64,
331 SYS_COUNT_RX_65_127,
332 SYS_COUNT_RX_128_255,
333 SYS_COUNT_RX_256_511,
334 SYS_COUNT_RX_512_1023,
335 SYS_COUNT_RX_1024_1526,
336 SYS_COUNT_RX_1527_MAX,
337 SYS_COUNT_RX_PAUSE,
338 SYS_COUNT_RX_CONTROL,
339 SYS_COUNT_RX_LONGS,
340 SYS_COUNT_RX_CLASSIFIED_DROPS,
341 SYS_COUNT_RX_RED_PRIO_0,
342 SYS_COUNT_RX_RED_PRIO_1,
343 SYS_COUNT_RX_RED_PRIO_2,
344 SYS_COUNT_RX_RED_PRIO_3,
345 SYS_COUNT_RX_RED_PRIO_4,
346 SYS_COUNT_RX_RED_PRIO_5,
347 SYS_COUNT_RX_RED_PRIO_6,
348 SYS_COUNT_RX_RED_PRIO_7,
349 SYS_COUNT_RX_YELLOW_PRIO_0,
350 SYS_COUNT_RX_YELLOW_PRIO_1,
351 SYS_COUNT_RX_YELLOW_PRIO_2,
352 SYS_COUNT_RX_YELLOW_PRIO_3,
353 SYS_COUNT_RX_YELLOW_PRIO_4,
354 SYS_COUNT_RX_YELLOW_PRIO_5,
355 SYS_COUNT_RX_YELLOW_PRIO_6,
356 SYS_COUNT_RX_YELLOW_PRIO_7,
357 SYS_COUNT_RX_GREEN_PRIO_0,
358 SYS_COUNT_RX_GREEN_PRIO_1,
359 SYS_COUNT_RX_GREEN_PRIO_2,
360 SYS_COUNT_RX_GREEN_PRIO_3,
361 SYS_COUNT_RX_GREEN_PRIO_4,
362 SYS_COUNT_RX_GREEN_PRIO_5,
363 SYS_COUNT_RX_GREEN_PRIO_6,
364 SYS_COUNT_RX_GREEN_PRIO_7,
365 SYS_COUNT_TX_OCTETS,
366 SYS_COUNT_TX_UNICAST,
367 SYS_COUNT_TX_MULTICAST,
368 SYS_COUNT_TX_BROADCAST,
369 SYS_COUNT_TX_COLLISION,
370 SYS_COUNT_TX_DROPS,
371 SYS_COUNT_TX_PAUSE,
372 SYS_COUNT_TX_64,
373 SYS_COUNT_TX_65_127,
374 SYS_COUNT_TX_128_255,
375 SYS_COUNT_TX_256_511,
376 SYS_COUNT_TX_512_1023,
377 SYS_COUNT_TX_1024_1526,
378 SYS_COUNT_TX_1527_MAX,
379 SYS_COUNT_TX_YELLOW_PRIO_0,
380 SYS_COUNT_TX_YELLOW_PRIO_1,
381 SYS_COUNT_TX_YELLOW_PRIO_2,
382 SYS_COUNT_TX_YELLOW_PRIO_3,
383 SYS_COUNT_TX_YELLOW_PRIO_4,
384 SYS_COUNT_TX_YELLOW_PRIO_5,
385 SYS_COUNT_TX_YELLOW_PRIO_6,
386 SYS_COUNT_TX_YELLOW_PRIO_7,
387 SYS_COUNT_TX_GREEN_PRIO_0,
388 SYS_COUNT_TX_GREEN_PRIO_1,
389 SYS_COUNT_TX_GREEN_PRIO_2,
390 SYS_COUNT_TX_GREEN_PRIO_3,
391 SYS_COUNT_TX_GREEN_PRIO_4,
392 SYS_COUNT_TX_GREEN_PRIO_5,
393 SYS_COUNT_TX_GREEN_PRIO_6,
394 SYS_COUNT_TX_GREEN_PRIO_7,
395 SYS_COUNT_TX_AGED,
396 SYS_COUNT_DROP_LOCAL,
397 SYS_COUNT_DROP_TAIL,
398 SYS_COUNT_DROP_YELLOW_PRIO_0,
399 SYS_COUNT_DROP_YELLOW_PRIO_1,
400 SYS_COUNT_DROP_YELLOW_PRIO_2,
401 SYS_COUNT_DROP_YELLOW_PRIO_3,
402 SYS_COUNT_DROP_YELLOW_PRIO_4,
403 SYS_COUNT_DROP_YELLOW_PRIO_5,
404 SYS_COUNT_DROP_YELLOW_PRIO_6,
405 SYS_COUNT_DROP_YELLOW_PRIO_7,
406 SYS_COUNT_DROP_GREEN_PRIO_0,
407 SYS_COUNT_DROP_GREEN_PRIO_1,
408 SYS_COUNT_DROP_GREEN_PRIO_2,
409 SYS_COUNT_DROP_GREEN_PRIO_3,
410 SYS_COUNT_DROP_GREEN_PRIO_4,
411 SYS_COUNT_DROP_GREEN_PRIO_5,
412 SYS_COUNT_DROP_GREEN_PRIO_6,
413 SYS_COUNT_DROP_GREEN_PRIO_7,
414 SYS_COUNT_SF_MATCHING_FRAMES,
415 SYS_COUNT_SF_NOT_PASSING_FRAMES,
416 SYS_COUNT_SF_NOT_PASSING_SDU,
417 SYS_COUNT_SF_RED_FRAMES,
418 SYS_RESET_CFG,
419 SYS_SR_ETYPE_CFG,
420 SYS_VLAN_ETYPE_CFG,
421 SYS_PORT_MODE,
422 SYS_FRONT_PORT_MODE,
423 SYS_FRM_AGING,
424 SYS_STAT_CFG,
425 SYS_SW_STATUS,
426 SYS_MISC_CFG,
427 SYS_REW_MAC_HIGH_CFG,
428 SYS_REW_MAC_LOW_CFG,
429 SYS_TIMESTAMP_OFFSET,
430 SYS_CMID,
431 SYS_PAUSE_CFG,
432 SYS_PAUSE_TOT_CFG,
433 SYS_ATOP,
434 SYS_ATOP_TOT_CFG,
435 SYS_MAC_FC_CFG,
436 SYS_MMGT,
437 SYS_MMGT_FAST,
438 SYS_EVENTS_DIF,
439 SYS_EVENTS_CORE,
440 SYS_PTP_STATUS,
441 SYS_PTP_TXSTAMP,
442 SYS_PTP_NXT,
443 SYS_PTP_CFG,
444 SYS_RAM_INIT,
445 SYS_CM_ADDR,
446 SYS_CM_DATA_WR,
447 SYS_CM_DATA_RD,
448 SYS_CM_OP,
449 SYS_CM_DATA,
450 PTP_PIN_CFG = PTP << TARGET_OFFSET,
451 PTP_PIN_TOD_SEC_MSB,
452 PTP_PIN_TOD_SEC_LSB,
453 PTP_PIN_TOD_NSEC,
454 PTP_PIN_WF_HIGH_PERIOD,
455 PTP_PIN_WF_LOW_PERIOD,
456 PTP_CFG_MISC,
457 PTP_CLK_CFG_ADJ_CFG,
458 PTP_CLK_CFG_ADJ_FREQ,
459 GCB_SOFT_RST = GCB << TARGET_OFFSET,
460 GCB_MIIM_MII_STATUS,
461 GCB_MIIM_MII_CMD,
462 GCB_MIIM_MII_DATA,
463 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
464 DEV_PORT_MISC,
465 DEV_EVENTS,
466 DEV_EEE_CFG,
467 DEV_RX_PATH_DELAY,
468 DEV_TX_PATH_DELAY,
469 DEV_PTP_PREDICT_CFG,
470 DEV_MAC_ENA_CFG,
471 DEV_MAC_MODE_CFG,
472 DEV_MAC_MAXLEN_CFG,
473 DEV_MAC_TAGS_CFG,
474 DEV_MAC_ADV_CHK_CFG,
475 DEV_MAC_IFG_CFG,
476 DEV_MAC_HDX_CFG,
477 DEV_MAC_DBG_CFG,
478 DEV_MAC_FC_MAC_LOW_CFG,
479 DEV_MAC_FC_MAC_HIGH_CFG,
480 DEV_MAC_STICKY,
481 PCS1G_CFG,
482 PCS1G_MODE_CFG,
483 PCS1G_SD_CFG,
484 PCS1G_ANEG_CFG,
485 PCS1G_ANEG_NP_CFG,
486 PCS1G_LB_CFG,
487 PCS1G_DBG_CFG,
488 PCS1G_CDET_CFG,
489 PCS1G_ANEG_STATUS,
490 PCS1G_ANEG_NP_STATUS,
491 PCS1G_LINK_STATUS,
492 PCS1G_LINK_DOWN_CNT,
493 PCS1G_STICKY,
494 PCS1G_DEBUG_STATUS,
495 PCS1G_LPI_CFG,
496 PCS1G_LPI_WAKE_ERROR_CNT,
497 PCS1G_LPI_STATUS,
498 PCS1G_TSTPAT_MODE_CFG,
499 PCS1G_TSTPAT_STATUS,
500 DEV_PCS_FX100_CFG,
501 DEV_PCS_FX100_STATUS,
502 };
503
504 enum ocelot_regfield {
505 ANA_ADVLEARN_VLAN_CHK,
506 ANA_ADVLEARN_LEARN_MIRROR,
507 ANA_ANEVENTS_FLOOD_DISCARD,
508 ANA_ANEVENTS_MSTI_DROP,
509 ANA_ANEVENTS_ACLKILL,
510 ANA_ANEVENTS_ACLUSED,
511 ANA_ANEVENTS_AUTOAGE,
512 ANA_ANEVENTS_VS2TTL1,
513 ANA_ANEVENTS_STORM_DROP,
514 ANA_ANEVENTS_LEARN_DROP,
515 ANA_ANEVENTS_AGED_ENTRY,
516 ANA_ANEVENTS_CPU_LEARN_FAILED,
517 ANA_ANEVENTS_AUTO_LEARN_FAILED,
518 ANA_ANEVENTS_LEARN_REMOVE,
519 ANA_ANEVENTS_AUTO_LEARNED,
520 ANA_ANEVENTS_AUTO_MOVED,
521 ANA_ANEVENTS_DROPPED,
522 ANA_ANEVENTS_CLASSIFIED_DROP,
523 ANA_ANEVENTS_CLASSIFIED_COPY,
524 ANA_ANEVENTS_VLAN_DISCARD,
525 ANA_ANEVENTS_FWD_DISCARD,
526 ANA_ANEVENTS_MULTICAST_FLOOD,
527 ANA_ANEVENTS_UNICAST_FLOOD,
528 ANA_ANEVENTS_DEST_KNOWN,
529 ANA_ANEVENTS_BUCKET3_MATCH,
530 ANA_ANEVENTS_BUCKET2_MATCH,
531 ANA_ANEVENTS_BUCKET1_MATCH,
532 ANA_ANEVENTS_BUCKET0_MATCH,
533 ANA_ANEVENTS_CPU_OPERATION,
534 ANA_ANEVENTS_DMAC_LOOKUP,
535 ANA_ANEVENTS_SMAC_LOOKUP,
536 ANA_ANEVENTS_SEQ_GEN_ERR_0,
537 ANA_ANEVENTS_SEQ_GEN_ERR_1,
538 ANA_TABLES_MACACCESS_B_DOM,
539 ANA_TABLES_MACTINDX_BUCKET,
540 ANA_TABLES_MACTINDX_M_INDEX,
541 QSYS_SWITCH_PORT_MODE_PORT_ENA,
542 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG,
543 QSYS_SWITCH_PORT_MODE_YEL_RSRVD,
544 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,
545 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA,
546 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE,
547 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
548 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
549 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
550 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
551 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
552 SYS_PORT_MODE_DATA_WO_TS,
553 SYS_PORT_MODE_INCL_INJ_HDR,
554 SYS_PORT_MODE_INCL_XTR_HDR,
555 SYS_PORT_MODE_INCL_HDR_ERR,
556 SYS_RESET_CFG_CORE_ENA,
557 SYS_RESET_CFG_MEM_ENA,
558 SYS_RESET_CFG_MEM_INIT,
559 GCB_SOFT_RST_SWC_RST,
560 GCB_MIIM_MII_STATUS_PENDING,
561 GCB_MIIM_MII_STATUS_BUSY,
562 SYS_PAUSE_CFG_PAUSE_START,
563 SYS_PAUSE_CFG_PAUSE_STOP,
564 SYS_PAUSE_CFG_PAUSE_ENA,
565 REGFIELD_MAX
566 };
567
568 enum {
569 /* VCAP_CORE_CFG */
570 VCAP_CORE_UPDATE_CTRL,
571 VCAP_CORE_MV_CFG,
572 /* VCAP_CORE_CACHE */
573 VCAP_CACHE_ENTRY_DAT,
574 VCAP_CACHE_MASK_DAT,
575 VCAP_CACHE_ACTION_DAT,
576 VCAP_CACHE_CNT_DAT,
577 VCAP_CACHE_TG_DAT,
578 /* VCAP_CONST */
579 VCAP_CONST_VCAP_VER,
580 VCAP_CONST_ENTRY_WIDTH,
581 VCAP_CONST_ENTRY_CNT,
582 VCAP_CONST_ENTRY_SWCNT,
583 VCAP_CONST_ENTRY_TG_WIDTH,
584 VCAP_CONST_ACTION_DEF_CNT,
585 VCAP_CONST_ACTION_WIDTH,
586 VCAP_CONST_CNT_WIDTH,
587 VCAP_CONST_CORE_CNT,
588 VCAP_CONST_IF_CNT,
589 };
590
591 enum ocelot_ptp_pins {
592 PTP_PIN_0,
593 PTP_PIN_1,
594 PTP_PIN_2,
595 PTP_PIN_3,
596 TOD_ACC_PIN
597 };
598
599 enum ocelot_stat {
600 OCELOT_STAT_RX_OCTETS,
601 OCELOT_STAT_RX_UNICAST,
602 OCELOT_STAT_RX_MULTICAST,
603 OCELOT_STAT_RX_BROADCAST,
604 OCELOT_STAT_RX_SHORTS,
605 OCELOT_STAT_RX_FRAGMENTS,
606 OCELOT_STAT_RX_JABBERS,
607 OCELOT_STAT_RX_CRC_ALIGN_ERRS,
608 OCELOT_STAT_RX_SYM_ERRS,
609 OCELOT_STAT_RX_64,
610 OCELOT_STAT_RX_65_127,
611 OCELOT_STAT_RX_128_255,
612 OCELOT_STAT_RX_256_511,
613 OCELOT_STAT_RX_512_1023,
614 OCELOT_STAT_RX_1024_1526,
615 OCELOT_STAT_RX_1527_MAX,
616 OCELOT_STAT_RX_PAUSE,
617 OCELOT_STAT_RX_CONTROL,
618 OCELOT_STAT_RX_LONGS,
619 OCELOT_STAT_RX_CLASSIFIED_DROPS,
620 OCELOT_STAT_RX_RED_PRIO_0,
621 OCELOT_STAT_RX_RED_PRIO_1,
622 OCELOT_STAT_RX_RED_PRIO_2,
623 OCELOT_STAT_RX_RED_PRIO_3,
624 OCELOT_STAT_RX_RED_PRIO_4,
625 OCELOT_STAT_RX_RED_PRIO_5,
626 OCELOT_STAT_RX_RED_PRIO_6,
627 OCELOT_STAT_RX_RED_PRIO_7,
628 OCELOT_STAT_RX_YELLOW_PRIO_0,
629 OCELOT_STAT_RX_YELLOW_PRIO_1,
630 OCELOT_STAT_RX_YELLOW_PRIO_2,
631 OCELOT_STAT_RX_YELLOW_PRIO_3,
632 OCELOT_STAT_RX_YELLOW_PRIO_4,
633 OCELOT_STAT_RX_YELLOW_PRIO_5,
634 OCELOT_STAT_RX_YELLOW_PRIO_6,
635 OCELOT_STAT_RX_YELLOW_PRIO_7,
636 OCELOT_STAT_RX_GREEN_PRIO_0,
637 OCELOT_STAT_RX_GREEN_PRIO_1,
638 OCELOT_STAT_RX_GREEN_PRIO_2,
639 OCELOT_STAT_RX_GREEN_PRIO_3,
640 OCELOT_STAT_RX_GREEN_PRIO_4,
641 OCELOT_STAT_RX_GREEN_PRIO_5,
642 OCELOT_STAT_RX_GREEN_PRIO_6,
643 OCELOT_STAT_RX_GREEN_PRIO_7,
644 OCELOT_STAT_TX_OCTETS,
645 OCELOT_STAT_TX_UNICAST,
646 OCELOT_STAT_TX_MULTICAST,
647 OCELOT_STAT_TX_BROADCAST,
648 OCELOT_STAT_TX_COLLISION,
649 OCELOT_STAT_TX_DROPS,
650 OCELOT_STAT_TX_PAUSE,
651 OCELOT_STAT_TX_64,
652 OCELOT_STAT_TX_65_127,
653 OCELOT_STAT_TX_128_255,
654 OCELOT_STAT_TX_256_511,
655 OCELOT_STAT_TX_512_1023,
656 OCELOT_STAT_TX_1024_1526,
657 OCELOT_STAT_TX_1527_MAX,
658 OCELOT_STAT_TX_YELLOW_PRIO_0,
659 OCELOT_STAT_TX_YELLOW_PRIO_1,
660 OCELOT_STAT_TX_YELLOW_PRIO_2,
661 OCELOT_STAT_TX_YELLOW_PRIO_3,
662 OCELOT_STAT_TX_YELLOW_PRIO_4,
663 OCELOT_STAT_TX_YELLOW_PRIO_5,
664 OCELOT_STAT_TX_YELLOW_PRIO_6,
665 OCELOT_STAT_TX_YELLOW_PRIO_7,
666 OCELOT_STAT_TX_GREEN_PRIO_0,
667 OCELOT_STAT_TX_GREEN_PRIO_1,
668 OCELOT_STAT_TX_GREEN_PRIO_2,
669 OCELOT_STAT_TX_GREEN_PRIO_3,
670 OCELOT_STAT_TX_GREEN_PRIO_4,
671 OCELOT_STAT_TX_GREEN_PRIO_5,
672 OCELOT_STAT_TX_GREEN_PRIO_6,
673 OCELOT_STAT_TX_GREEN_PRIO_7,
674 OCELOT_STAT_TX_AGED,
675 OCELOT_STAT_DROP_LOCAL,
676 OCELOT_STAT_DROP_TAIL,
677 OCELOT_STAT_DROP_YELLOW_PRIO_0,
678 OCELOT_STAT_DROP_YELLOW_PRIO_1,
679 OCELOT_STAT_DROP_YELLOW_PRIO_2,
680 OCELOT_STAT_DROP_YELLOW_PRIO_3,
681 OCELOT_STAT_DROP_YELLOW_PRIO_4,
682 OCELOT_STAT_DROP_YELLOW_PRIO_5,
683 OCELOT_STAT_DROP_YELLOW_PRIO_6,
684 OCELOT_STAT_DROP_YELLOW_PRIO_7,
685 OCELOT_STAT_DROP_GREEN_PRIO_0,
686 OCELOT_STAT_DROP_GREEN_PRIO_1,
687 OCELOT_STAT_DROP_GREEN_PRIO_2,
688 OCELOT_STAT_DROP_GREEN_PRIO_3,
689 OCELOT_STAT_DROP_GREEN_PRIO_4,
690 OCELOT_STAT_DROP_GREEN_PRIO_5,
691 OCELOT_STAT_DROP_GREEN_PRIO_6,
692 OCELOT_STAT_DROP_GREEN_PRIO_7,
693 OCELOT_NUM_STATS,
694 };
695
696 struct ocelot_stat_layout {
697 u32 reg;
698 char name[ETH_GSTRING_LEN];
699 };
700
701 /* 32-bit counter checked for wraparound by ocelot_port_update_stats()
702 * and copied to ocelot->stats.
703 */
704 #define OCELOT_STAT(kind) \
705 [OCELOT_STAT_ ## kind] = { .reg = SYS_COUNT_ ## kind }
706 /* Same as above, except also exported to ethtool -S. Standard counters should
707 * only be exposed to more specific interfaces rather than by their string name.
708 */
709 #define OCELOT_STAT_ETHTOOL(kind, ethtool_name) \
710 [OCELOT_STAT_ ## kind] = { .reg = SYS_COUNT_ ## kind, .name = ethtool_name }
711
712 #define OCELOT_COMMON_STATS \
713 OCELOT_STAT_ETHTOOL(RX_OCTETS, "rx_octets"), \
714 OCELOT_STAT_ETHTOOL(RX_UNICAST, "rx_unicast"), \
715 OCELOT_STAT_ETHTOOL(RX_MULTICAST, "rx_multicast"), \
716 OCELOT_STAT_ETHTOOL(RX_BROADCAST, "rx_broadcast"), \
717 OCELOT_STAT_ETHTOOL(RX_SHORTS, "rx_shorts"), \
718 OCELOT_STAT_ETHTOOL(RX_FRAGMENTS, "rx_fragments"), \
719 OCELOT_STAT_ETHTOOL(RX_JABBERS, "rx_jabbers"), \
720 OCELOT_STAT_ETHTOOL(RX_CRC_ALIGN_ERRS, "rx_crc_align_errs"), \
721 OCELOT_STAT_ETHTOOL(RX_SYM_ERRS, "rx_sym_errs"), \
722 OCELOT_STAT_ETHTOOL(RX_64, "rx_frames_below_65_octets"), \
723 OCELOT_STAT_ETHTOOL(RX_65_127, "rx_frames_65_to_127_octets"), \
724 OCELOT_STAT_ETHTOOL(RX_128_255, "rx_frames_128_to_255_octets"), \
725 OCELOT_STAT_ETHTOOL(RX_256_511, "rx_frames_256_to_511_octets"), \
726 OCELOT_STAT_ETHTOOL(RX_512_1023, "rx_frames_512_to_1023_octets"), \
727 OCELOT_STAT_ETHTOOL(RX_1024_1526, "rx_frames_1024_to_1526_octets"), \
728 OCELOT_STAT_ETHTOOL(RX_1527_MAX, "rx_frames_over_1526_octets"), \
729 OCELOT_STAT_ETHTOOL(RX_PAUSE, "rx_pause"), \
730 OCELOT_STAT_ETHTOOL(RX_CONTROL, "rx_control"), \
731 OCELOT_STAT_ETHTOOL(RX_LONGS, "rx_longs"), \
732 OCELOT_STAT_ETHTOOL(RX_CLASSIFIED_DROPS, "rx_classified_drops"), \
733 OCELOT_STAT_ETHTOOL(RX_RED_PRIO_0, "rx_red_prio_0"), \
734 OCELOT_STAT_ETHTOOL(RX_RED_PRIO_1, "rx_red_prio_1"), \
735 OCELOT_STAT_ETHTOOL(RX_RED_PRIO_2, "rx_red_prio_2"), \
736 OCELOT_STAT_ETHTOOL(RX_RED_PRIO_3, "rx_red_prio_3"), \
737 OCELOT_STAT_ETHTOOL(RX_RED_PRIO_4, "rx_red_prio_4"), \
738 OCELOT_STAT_ETHTOOL(RX_RED_PRIO_5, "rx_red_prio_5"), \
739 OCELOT_STAT_ETHTOOL(RX_RED_PRIO_6, "rx_red_prio_6"), \
740 OCELOT_STAT_ETHTOOL(RX_RED_PRIO_7, "rx_red_prio_7"), \
741 OCELOT_STAT_ETHTOOL(RX_YELLOW_PRIO_0, "rx_yellow_prio_0"), \
742 OCELOT_STAT_ETHTOOL(RX_YELLOW_PRIO_1, "rx_yellow_prio_1"), \
743 OCELOT_STAT_ETHTOOL(RX_YELLOW_PRIO_2, "rx_yellow_prio_2"), \
744 OCELOT_STAT_ETHTOOL(RX_YELLOW_PRIO_3, "rx_yellow_prio_3"), \
745 OCELOT_STAT_ETHTOOL(RX_YELLOW_PRIO_4, "rx_yellow_prio_4"), \
746 OCELOT_STAT_ETHTOOL(RX_YELLOW_PRIO_5, "rx_yellow_prio_5"), \
747 OCELOT_STAT_ETHTOOL(RX_YELLOW_PRIO_6, "rx_yellow_prio_6"), \
748 OCELOT_STAT_ETHTOOL(RX_YELLOW_PRIO_7, "rx_yellow_prio_7"), \
749 OCELOT_STAT_ETHTOOL(RX_GREEN_PRIO_0, "rx_green_prio_0"), \
750 OCELOT_STAT_ETHTOOL(RX_GREEN_PRIO_1, "rx_green_prio_1"), \
751 OCELOT_STAT_ETHTOOL(RX_GREEN_PRIO_2, "rx_green_prio_2"), \
752 OCELOT_STAT_ETHTOOL(RX_GREEN_PRIO_3, "rx_green_prio_3"), \
753 OCELOT_STAT_ETHTOOL(RX_GREEN_PRIO_4, "rx_green_prio_4"), \
754 OCELOT_STAT_ETHTOOL(RX_GREEN_PRIO_5, "rx_green_prio_5"), \
755 OCELOT_STAT_ETHTOOL(RX_GREEN_PRIO_6, "rx_green_prio_6"), \
756 OCELOT_STAT_ETHTOOL(RX_GREEN_PRIO_7, "rx_green_prio_7"), \
757 OCELOT_STAT_ETHTOOL(TX_OCTETS, "tx_octets"), \
758 OCELOT_STAT_ETHTOOL(TX_UNICAST, "tx_unicast"), \
759 OCELOT_STAT_ETHTOOL(TX_MULTICAST, "tx_multicast"), \
760 OCELOT_STAT_ETHTOOL(TX_BROADCAST, "tx_broadcast"), \
761 OCELOT_STAT_ETHTOOL(TX_COLLISION, "tx_collision"), \
762 OCELOT_STAT_ETHTOOL(TX_DROPS, "tx_drops"), \
763 OCELOT_STAT_ETHTOOL(TX_PAUSE, "tx_pause"), \
764 OCELOT_STAT_ETHTOOL(TX_64, "tx_frames_below_65_octets"), \
765 OCELOT_STAT_ETHTOOL(TX_65_127, "tx_frames_65_to_127_octets"), \
766 OCELOT_STAT_ETHTOOL(TX_128_255, "tx_frames_128_255_octets"), \
767 OCELOT_STAT_ETHTOOL(TX_256_511, "tx_frames_256_511_octets"), \
768 OCELOT_STAT_ETHTOOL(TX_512_1023, "tx_frames_512_1023_octets"), \
769 OCELOT_STAT_ETHTOOL(TX_1024_1526, "tx_frames_1024_1526_octets"), \
770 OCELOT_STAT_ETHTOOL(TX_1527_MAX, "tx_frames_over_1526_octets"), \
771 OCELOT_STAT_ETHTOOL(TX_YELLOW_PRIO_0, "tx_yellow_prio_0"), \
772 OCELOT_STAT_ETHTOOL(TX_YELLOW_PRIO_1, "tx_yellow_prio_1"), \
773 OCELOT_STAT_ETHTOOL(TX_YELLOW_PRIO_2, "tx_yellow_prio_2"), \
774 OCELOT_STAT_ETHTOOL(TX_YELLOW_PRIO_3, "tx_yellow_prio_3"), \
775 OCELOT_STAT_ETHTOOL(TX_YELLOW_PRIO_4, "tx_yellow_prio_4"), \
776 OCELOT_STAT_ETHTOOL(TX_YELLOW_PRIO_5, "tx_yellow_prio_5"), \
777 OCELOT_STAT_ETHTOOL(TX_YELLOW_PRIO_6, "tx_yellow_prio_6"), \
778 OCELOT_STAT_ETHTOOL(TX_YELLOW_PRIO_7, "tx_yellow_prio_7"), \
779 OCELOT_STAT_ETHTOOL(TX_GREEN_PRIO_0, "tx_green_prio_0"), \
780 OCELOT_STAT_ETHTOOL(TX_GREEN_PRIO_1, "tx_green_prio_1"), \
781 OCELOT_STAT_ETHTOOL(TX_GREEN_PRIO_2, "tx_green_prio_2"), \
782 OCELOT_STAT_ETHTOOL(TX_GREEN_PRIO_3, "tx_green_prio_3"), \
783 OCELOT_STAT_ETHTOOL(TX_GREEN_PRIO_4, "tx_green_prio_4"), \
784 OCELOT_STAT_ETHTOOL(TX_GREEN_PRIO_5, "tx_green_prio_5"), \
785 OCELOT_STAT_ETHTOOL(TX_GREEN_PRIO_6, "tx_green_prio_6"), \
786 OCELOT_STAT_ETHTOOL(TX_GREEN_PRIO_7, "tx_green_prio_7"), \
787 OCELOT_STAT_ETHTOOL(TX_AGED, "tx_aged"), \
788 OCELOT_STAT_ETHTOOL(DROP_LOCAL, "drop_local"), \
789 OCELOT_STAT_ETHTOOL(DROP_TAIL, "drop_tail"), \
790 OCELOT_STAT_ETHTOOL(DROP_YELLOW_PRIO_0, "drop_yellow_prio_0"), \
791 OCELOT_STAT_ETHTOOL(DROP_YELLOW_PRIO_1, "drop_yellow_prio_1"), \
792 OCELOT_STAT_ETHTOOL(DROP_YELLOW_PRIO_2, "drop_yellow_prio_2"), \
793 OCELOT_STAT_ETHTOOL(DROP_YELLOW_PRIO_3, "drop_yellow_prio_3"), \
794 OCELOT_STAT_ETHTOOL(DROP_YELLOW_PRIO_4, "drop_yellow_prio_4"), \
795 OCELOT_STAT_ETHTOOL(DROP_YELLOW_PRIO_5, "drop_yellow_prio_5"), \
796 OCELOT_STAT_ETHTOOL(DROP_YELLOW_PRIO_6, "drop_yellow_prio_6"), \
797 OCELOT_STAT_ETHTOOL(DROP_YELLOW_PRIO_7, "drop_yellow_prio_7"), \
798 OCELOT_STAT_ETHTOOL(DROP_GREEN_PRIO_0, "drop_green_prio_0"), \
799 OCELOT_STAT_ETHTOOL(DROP_GREEN_PRIO_1, "drop_green_prio_1"), \
800 OCELOT_STAT_ETHTOOL(DROP_GREEN_PRIO_2, "drop_green_prio_2"), \
801 OCELOT_STAT_ETHTOOL(DROP_GREEN_PRIO_3, "drop_green_prio_3"), \
802 OCELOT_STAT_ETHTOOL(DROP_GREEN_PRIO_4, "drop_green_prio_4"), \
803 OCELOT_STAT_ETHTOOL(DROP_GREEN_PRIO_5, "drop_green_prio_5"), \
804 OCELOT_STAT_ETHTOOL(DROP_GREEN_PRIO_6, "drop_green_prio_6"), \
805 OCELOT_STAT_ETHTOOL(DROP_GREEN_PRIO_7, "drop_green_prio_7")
806
807 struct ocelot_stats_region {
808 struct list_head node;
809 u32 base;
810 int count;
811 u32 *buf;
812 };
813
814 enum ocelot_tag_prefix {
815 OCELOT_TAG_PREFIX_DISABLED = 0,
816 OCELOT_TAG_PREFIX_NONE,
817 OCELOT_TAG_PREFIX_SHORT,
818 OCELOT_TAG_PREFIX_LONG,
819 };
820
821 struct ocelot;
822
823 struct ocelot_ops {
824 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
825 int (*netdev_to_port)(struct net_device *dev);
826 int (*reset)(struct ocelot *ocelot);
827 u16 (*wm_enc)(u16 value);
828 u16 (*wm_dec)(u16 value);
829 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse);
830 void (*psfp_init)(struct ocelot *ocelot);
831 int (*psfp_filter_add)(struct ocelot *ocelot, int port,
832 struct flow_cls_offload *f);
833 int (*psfp_filter_del)(struct ocelot *ocelot, struct flow_cls_offload *f);
834 int (*psfp_stats_get)(struct ocelot *ocelot, struct flow_cls_offload *f,
835 struct flow_stats *stats);
836 void (*cut_through_fwd)(struct ocelot *ocelot);
837 void (*tas_clock_adjust)(struct ocelot *ocelot);
838 void (*update_stats)(struct ocelot *ocelot);
839 };
840
841 struct ocelot_vcap_policer {
842 struct list_head pol_list;
843 u16 base;
844 u16 max;
845 u16 base2;
846 u16 max2;
847 };
848
849 struct ocelot_vcap_block {
850 struct list_head rules;
851 int count;
852 };
853
854 struct ocelot_bridge_vlan {
855 u16 vid;
856 unsigned long portmask;
857 unsigned long untagged;
858 struct list_head list;
859 };
860
861 enum ocelot_port_tag_config {
862 /* all VLANs are egress-untagged */
863 OCELOT_PORT_TAG_DISABLED = 0,
864 /* all VLANs except the native VLAN and VID 0 are egress-tagged */
865 OCELOT_PORT_TAG_NATIVE = 1,
866 /* all VLANs except VID 0 are egress-tagged */
867 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2,
868 /* all VLANs are egress-tagged */
869 OCELOT_PORT_TAG_TRUNK = 3,
870 };
871
872 struct ocelot_psfp_list {
873 struct list_head stream_list;
874 struct list_head sfi_list;
875 struct list_head sgi_list;
876 /* Serialize access to the lists */
877 struct mutex lock;
878 };
879
880 enum ocelot_sb {
881 OCELOT_SB_BUF,
882 OCELOT_SB_REF,
883 OCELOT_SB_NUM,
884 };
885
886 enum ocelot_sb_pool {
887 OCELOT_SB_POOL_ING,
888 OCELOT_SB_POOL_EGR,
889 OCELOT_SB_POOL_NUM,
890 };
891
892 /* MAC table entry types.
893 * ENTRYTYPE_NORMAL is subject to aging.
894 * ENTRYTYPE_LOCKED is not subject to aging.
895 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
896 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
897 */
898 enum macaccess_entry_type {
899 ENTRYTYPE_NORMAL = 0,
900 ENTRYTYPE_LOCKED,
901 ENTRYTYPE_MACv4,
902 ENTRYTYPE_MACv6,
903 };
904
905 #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0)
906 #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1)
907
908 struct ocelot_lag_fdb {
909 unsigned char addr[ETH_ALEN];
910 u16 vid;
911 struct net_device *bond;
912 struct list_head list;
913 };
914
915 struct ocelot_mirror {
916 refcount_t refcount;
917 int to;
918 };
919
920 struct ocelot_port;
921
922 struct ocelot_port {
923 struct ocelot *ocelot;
924
925 struct regmap *target;
926
927 struct net_device *bond;
928 struct net_device *bridge;
929
930 struct ocelot_port *dsa_8021q_cpu;
931
932 /* VLAN that untagged frames are classified to, on ingress */
933 const struct ocelot_bridge_vlan *pvid_vlan;
934
935 struct tc_taprio_qopt_offload *taprio;
936
937 phy_interface_t phy_mode;
938
939 unsigned int ptp_skbs_in_flight;
940 struct sk_buff_head tx_skbs;
941
942 u16 mrp_ring_id;
943
944 u8 ptp_cmd;
945 u8 ts_id;
946
947 u8 index;
948
949 u8 stp_state;
950 bool vlan_aware;
951 bool is_dsa_8021q_cpu;
952 bool learn_ena;
953
954 bool lag_tx_active;
955
956 int bridge_num;
957
958 int speed;
959 };
960
961 struct ocelot {
962 struct device *dev;
963 struct devlink *devlink;
964 struct devlink_port *devlink_ports;
965
966 const struct ocelot_ops *ops;
967 struct regmap *targets[TARGET_MAX];
968 struct regmap_field *regfields[REGFIELD_MAX];
969 const u32 *const *map;
970 const struct ocelot_stat_layout *stats_layout;
971 struct list_head stats_regions;
972
973 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM];
974 int packet_buffer_size;
975 int num_frame_refs;
976 int num_mact_rows;
977
978 struct ocelot_port **ports;
979
980 u8 base_mac[ETH_ALEN];
981
982 struct list_head vlans;
983 struct list_head traps;
984 struct list_head lag_fdbs;
985
986 /* Switches like VSC9959 have flooding per traffic class */
987 int num_flooding_pgids;
988
989 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
990 * the CPU is located after the physical ports (at the
991 * num_phys_ports index).
992 */
993 u8 num_phys_ports;
994
995 int npi;
996
997 enum ocelot_tag_prefix npi_inj_prefix;
998 enum ocelot_tag_prefix npi_xtr_prefix;
999
1000 unsigned long bridges;
1001
1002 struct list_head multicast;
1003 struct list_head pgids;
1004
1005 struct list_head dummy_rules;
1006 struct ocelot_vcap_block block[3];
1007 struct ocelot_vcap_policer vcap_pol;
1008 struct vcap_props *vcap;
1009 struct ocelot_mirror *mirror;
1010
1011 struct ocelot_psfp_list psfp;
1012
1013 /* Workqueue to check statistics for overflow */
1014 struct delayed_work stats_work;
1015 struct workqueue_struct *stats_queue;
1016 /* Lock for serializing access to the statistics array */
1017 spinlock_t stats_lock;
1018 u64 *stats;
1019
1020 /* Lock for serializing indirect access to STAT_VIEW registers */
1021 struct mutex stat_view_lock;
1022 /* Lock for serializing access to the MAC table */
1023 struct mutex mact_lock;
1024 /* Lock for serializing forwarding domain changes */
1025 struct mutex fwd_domain_lock;
1026
1027 /* Lock for serializing Time-Aware Shaper changes */
1028 struct mutex tas_lock;
1029
1030 struct workqueue_struct *owq;
1031
1032 u8 ptp:1;
1033 struct ptp_clock *ptp_clock;
1034 struct ptp_clock_info ptp_info;
1035 struct hwtstamp_config hwtstamp_config;
1036 unsigned int ptp_skbs_in_flight;
1037 /* Protects the 2-step TX timestamp ID logic */
1038 spinlock_t ts_id_lock;
1039 /* Protects the PTP interface state */
1040 struct mutex ptp_lock;
1041 /* Protects the PTP clock */
1042 spinlock_t ptp_clock_lock;
1043 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM];
1044
1045 struct ocelot_fdma *fdma;
1046 };
1047
1048 struct ocelot_policer {
1049 u32 rate; /* kilobit per second */
1050 u32 burst; /* bytes */
1051 };
1052
1053 #define ocelot_bulk_read(ocelot, reg, buf, count) \
1054 __ocelot_bulk_read_ix(ocelot, reg, 0, buf, count)
1055
1056 #define ocelot_read_ix(ocelot, reg, gi, ri) \
1057 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
1058 #define ocelot_read_gix(ocelot, reg, gi) \
1059 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
1060 #define ocelot_read_rix(ocelot, reg, ri) \
1061 __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
1062 #define ocelot_read(ocelot, reg) \
1063 __ocelot_read_ix(ocelot, reg, 0)
1064
1065 #define ocelot_write_ix(ocelot, val, reg, gi, ri) \
1066 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
1067 #define ocelot_write_gix(ocelot, val, reg, gi) \
1068 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
1069 #define ocelot_write_rix(ocelot, val, reg, ri) \
1070 __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
1071 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
1072
1073 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) \
1074 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
1075 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) \
1076 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
1077 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) \
1078 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
1079 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
1080
1081 #define ocelot_field_write(ocelot, reg, val) \
1082 regmap_field_write((ocelot)->regfields[(reg)], (val))
1083 #define ocelot_field_read(ocelot, reg, val) \
1084 regmap_field_read((ocelot)->regfields[(reg)], (val))
1085 #define ocelot_fields_write(ocelot, id, reg, val) \
1086 regmap_fields_write((ocelot)->regfields[(reg)], (id), (val))
1087 #define ocelot_fields_read(ocelot, id, reg, val) \
1088 regmap_fields_read((ocelot)->regfields[(reg)], (id), (val))
1089
1090 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \
1091 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
1092 #define ocelot_target_read_gix(ocelot, target, reg, gi) \
1093 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi))
1094 #define ocelot_target_read_rix(ocelot, target, reg, ri) \
1095 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri))
1096 #define ocelot_target_read(ocelot, target, reg) \
1097 __ocelot_target_read_ix(ocelot, target, reg, 0)
1098
1099 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \
1100 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
1101 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \
1102 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi))
1103 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \
1104 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri))
1105 #define ocelot_target_write(ocelot, target, val, reg) \
1106 __ocelot_target_write_ix(ocelot, target, val, reg, 0)
1107
1108 /* I/O */
1109 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
1110 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
1111 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg);
1112 int __ocelot_bulk_read_ix(struct ocelot *ocelot, u32 reg, u32 offset, void *buf,
1113 int count);
1114 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
1115 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
1116 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
1117 u32 offset);
1118 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
1119 u32 reg, u32 offset);
1120 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
1121 u32 val, u32 reg, u32 offset);
1122
1123 /* Packet I/O */
1124 bool ocelot_can_inject(struct ocelot *ocelot, int grp);
1125 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1126 u32 rew_op, struct sk_buff *skb);
1127 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag);
1128 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb);
1129 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp);
1130 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
1131 u64 timestamp);
1132
1133 /* Hardware initialization */
1134 int ocelot_regfields_init(struct ocelot *ocelot,
1135 const struct reg_field *const regfields);
1136 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
1137 int ocelot_init(struct ocelot *ocelot);
1138 void ocelot_deinit(struct ocelot *ocelot);
1139 void ocelot_init_port(struct ocelot *ocelot, int port);
1140 void ocelot_deinit_port(struct ocelot *ocelot, int port);
1141
1142 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu);
1143 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu);
1144 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu);
1145 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port);
1146 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port);
1147
1148 /* DSA callbacks */
1149 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
1150 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
1151 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
1152 void ocelot_port_get_stats64(struct ocelot *ocelot, int port,
1153 struct rtnl_link_stats64 *stats);
1154 void ocelot_port_get_pause_stats(struct ocelot *ocelot, int port,
1155 struct ethtool_pause_stats *pause_stats);
1156 void ocelot_port_get_rmon_stats(struct ocelot *ocelot, int port,
1157 struct ethtool_rmon_stats *rmon_stats,
1158 const struct ethtool_rmon_hist_range **ranges);
1159 void ocelot_port_get_eth_ctrl_stats(struct ocelot *ocelot, int port,
1160 struct ethtool_eth_ctrl_stats *ctrl_stats);
1161 void ocelot_port_get_eth_mac_stats(struct ocelot *ocelot, int port,
1162 struct ethtool_eth_mac_stats *mac_stats);
1163 void ocelot_port_get_eth_phy_stats(struct ocelot *ocelot, int port,
1164 struct ethtool_eth_phy_stats *phy_stats);
1165 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
1166 struct ethtool_ts_info *info);
1167 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
1168 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled,
1169 struct netlink_ext_ack *extack);
1170 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
1171 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port);
1172 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
1173 struct switchdev_brport_flags val);
1174 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
1175 struct switchdev_brport_flags val);
1176 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port);
1177 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio);
1178 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp);
1179 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
1180 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
1181 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1182 struct net_device *bridge, int bridge_num,
1183 struct netlink_ext_ack *extack);
1184 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1185 struct net_device *bridge);
1186 int ocelot_mact_flush(struct ocelot *ocelot, int port);
1187 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1188 dsa_fdb_dump_cb_t *cb, void *data);
1189 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1190 u16 vid, const struct net_device *bridge);
1191 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1192 u16 vid, const struct net_device *bridge);
1193 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
1194 const unsigned char *addr, u16 vid,
1195 const struct net_device *bridge);
1196 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
1197 const unsigned char *addr, u16 vid,
1198 const struct net_device *bridge);
1199 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
1200 bool untagged, struct netlink_ext_ack *extack);
1201 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
1202 bool untagged);
1203 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
1204 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
1205 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
1206 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
1207 struct sk_buff *skb,
1208 struct sk_buff **clone);
1209 void ocelot_get_txtstamp(struct ocelot *ocelot);
1210 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
1211 int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
1212 int ocelot_port_policer_add(struct ocelot *ocelot, int port,
1213 struct ocelot_policer *pol);
1214 int ocelot_port_policer_del(struct ocelot *ocelot, int port);
1215 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
1216 bool ingress, struct netlink_ext_ack *extack);
1217 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress);
1218 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
1219 struct flow_cls_offload *f, bool ingress);
1220 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
1221 struct flow_cls_offload *f, bool ingress);
1222 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
1223 struct flow_cls_offload *f, bool ingress);
1224 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1225 const struct switchdev_obj_port_mdb *mdb,
1226 const struct net_device *bridge);
1227 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1228 const struct switchdev_obj_port_mdb *mdb,
1229 const struct net_device *bridge);
1230 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1231 struct net_device *bond,
1232 struct netdev_lag_upper_info *info,
1233 struct netlink_ext_ack *extack);
1234 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1235 struct net_device *bond);
1236 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active);
1237 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond);
1238
1239 int ocelot_devlink_sb_register(struct ocelot *ocelot);
1240 void ocelot_devlink_sb_unregister(struct ocelot *ocelot);
1241 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index,
1242 u16 pool_index,
1243 struct devlink_sb_pool_info *pool_info);
1244 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index,
1245 u16 pool_index, u32 size,
1246 enum devlink_sb_threshold_type threshold_type,
1247 struct netlink_ext_ack *extack);
1248 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port,
1249 unsigned int sb_index, u16 pool_index,
1250 u32 *p_threshold);
1251 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port,
1252 unsigned int sb_index, u16 pool_index,
1253 u32 threshold, struct netlink_ext_ack *extack);
1254 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port,
1255 unsigned int sb_index, u16 tc_index,
1256 enum devlink_sb_pool_type pool_type,
1257 u16 *p_pool_index, u32 *p_threshold);
1258 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port,
1259 unsigned int sb_index, u16 tc_index,
1260 enum devlink_sb_pool_type pool_type,
1261 u16 pool_index, u32 threshold,
1262 struct netlink_ext_ack *extack);
1263 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index);
1264 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index);
1265 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port,
1266 unsigned int sb_index, u16 pool_index,
1267 u32 *p_cur, u32 *p_max);
1268 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port,
1269 unsigned int sb_index, u16 tc_index,
1270 enum devlink_sb_pool_type pool_type,
1271 u32 *p_cur, u32 *p_max);
1272
1273 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
1274 unsigned int link_an_mode,
1275 phy_interface_t interface,
1276 unsigned long quirks);
1277 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
1278 struct phy_device *phydev,
1279 unsigned int link_an_mode,
1280 phy_interface_t interface,
1281 int speed, int duplex,
1282 bool tx_pause, bool rx_pause,
1283 unsigned long quirks);
1284
1285 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
1286 const unsigned char mac[ETH_ALEN],
1287 unsigned int vid, enum macaccess_entry_type *type);
1288 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
1289 const unsigned char mac[ETH_ALEN],
1290 unsigned int vid,
1291 enum macaccess_entry_type type,
1292 int sfid, int ssid);
1293
1294 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
1295 unsigned long to_mask);
1296
1297 int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix,
1298 struct ocelot_policer *pol);
1299 int ocelot_vcap_policer_del(struct ocelot *ocelot, u32 pol_ix);
1300
1301 #if IS_ENABLED(CONFIG_BRIDGE_MRP)
1302 int ocelot_mrp_add(struct ocelot *ocelot, int port,
1303 const struct switchdev_obj_mrp *mrp);
1304 int ocelot_mrp_del(struct ocelot *ocelot, int port,
1305 const struct switchdev_obj_mrp *mrp);
1306 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1307 const struct switchdev_obj_ring_role_mrp *mrp);
1308 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1309 const struct switchdev_obj_ring_role_mrp *mrp);
1310 #else
ocelot_mrp_add(struct ocelot * ocelot,int port,const struct switchdev_obj_mrp * mrp)1311 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port,
1312 const struct switchdev_obj_mrp *mrp)
1313 {
1314 return -EOPNOTSUPP;
1315 }
1316
ocelot_mrp_del(struct ocelot * ocelot,int port,const struct switchdev_obj_mrp * mrp)1317 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port,
1318 const struct switchdev_obj_mrp *mrp)
1319 {
1320 return -EOPNOTSUPP;
1321 }
1322
1323 static inline int
ocelot_mrp_add_ring_role(struct ocelot * ocelot,int port,const struct switchdev_obj_ring_role_mrp * mrp)1324 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1325 const struct switchdev_obj_ring_role_mrp *mrp)
1326 {
1327 return -EOPNOTSUPP;
1328 }
1329
1330 static inline int
ocelot_mrp_del_ring_role(struct ocelot * ocelot,int port,const struct switchdev_obj_ring_role_mrp * mrp)1331 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1332 const struct switchdev_obj_ring_role_mrp *mrp)
1333 {
1334 return -EOPNOTSUPP;
1335 }
1336 #endif
1337
1338 #endif
1339