1 /* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * PCI specific definitions 5 * 6 * Author: source@mvista.com 7 * 8 * This program is free software; you can distribute it and/or modify it 9 * under the terms of the GNU General Public License (Version 2) as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 20 */ 21 22 #ifndef __PNX8550_PCI_H 23 #define __PNX8550_PCI_H 24 25 #include <linux/types.h> 26 #include <linux/pci.h> 27 #include <linux/kernel.h> 28 #include <linux/init.h> 29 30 #define PCI_ACCESS_READ 0 31 #define PCI_ACCESS_WRITE 1 32 33 #define PCI_CMD_IOR 0x20 34 #define PCI_CMD_IOW 0x30 35 #define PCI_CMD_CONFIG_READ 0xa0 36 #define PCI_CMD_CONFIG_WRITE 0xb0 37 38 #define PCI_IO_TIMEOUT 1000 39 #define PCI_IO_RETRY 5 40 /* Timeout for IO and CFG accesses. 41 This is in 1/1024 th of a jiffie(=10ms) 42 i.e. approx 10us */ 43 #define PCI_IO_JIFFIES_TIMEOUT 40 44 #define PCI_IO_JIFFIES_SHIFT 10 45 46 #define PCI_BYTE_ENABLE_MASK 0x0000000f 47 #define PCI_CFG_BUS_SHIFT 16 48 #define PCI_CFG_FUNC_SHIFT 8 49 #define PCI_CFG_REG_SHIFT 2 50 51 #define PCI_BASE 0x1be00000 52 #define PCI_SETUP 0x00040010 53 #define PCI_DIS_REQGNT (1<<30) 54 #define PCI_DIS_REQGNTA (1<<29) 55 #define PCI_DIS_REQGNTB (1<<28) 56 #define PCI_D2_SUPPORT (1<<27) 57 #define PCI_D1_SUPPORT (1<<26) 58 #define PCI_EN_TA (1<<24) 59 #define PCI_EN_PCI2MMI (1<<23) 60 #define PCI_EN_XIO (1<<22) 61 #define PCI_BASE18_PREF (1<<21) 62 #define SIZE_16M 0x3 63 #define SIZE_32M 0x4 64 #define SIZE_64M 0x5 65 #define SIZE_128M 0x6 66 #define PCI_SETUP_BASE18_SIZE(X) (X<<18) 67 #define PCI_SETUP_BASE18_EN (1<<17) 68 #define PCI_SETUP_BASE14_PREF (1<<16) 69 #define PCI_SETUP_BASE14_SIZE(X) (X<<12) 70 #define PCI_SETUP_BASE14_EN (1<<11) 71 #define PCI_SETUP_BASE10_PREF (1<<10) 72 #define PCI_SETUP_BASE10_SIZE(X) (X<<7) 73 #define PCI_SETUP_CFGMANAGE_EN (1<<1) 74 #define PCI_SETUP_PCIARB_EN (1<<0) 75 76 #define PCI_CTRL 0x040014 77 #define PCI_SWPB_DCS_PCI (1<<16) 78 #define PCI_SWPB_PCI_PCI (1<<15) 79 #define PCI_SWPB_PCI_DCS (1<<14) 80 #define PCI_REG_WR_POST (1<<13) 81 #define PCI_XIO_WR_POST (1<<12) 82 #define PCI_PCI2_WR_POST (1<<13) 83 #define PCI_PCI1_WR_POST (1<<12) 84 #define PCI_SERR_SEEN (1<<11) 85 #define PCI_B10_SPEC_RD (1<<6) 86 #define PCI_B14_SPEC_RD (1<<5) 87 #define PCI_B18_SPEC_RD (1<<4) 88 #define PCI_B10_NOSUBWORD (1<<3) 89 #define PCI_B14_NOSUBWORD (1<<2) 90 #define PCI_B18_NOSUBWORD (1<<1) 91 #define PCI_RETRY_TMREN (1<<0) 92 93 #define PCI_BASE1_LO 0x040018 94 #define PCI_BASE1_HI 0x04001C 95 #define PCI_BASE2_LO 0x040020 96 #define PCI_BASE2_HI 0x040024 97 #define PCI_RDLIFETIM 0x040028 98 #define PCI_GPPM_ADDR 0x04002C 99 #define PCI_GPPM_WDAT 0x040030 100 #define PCI_GPPM_RDAT 0x040034 101 #define PCI_GPPM_CTRL 0x040038 102 #define GPPM_DONE (1<<10) 103 #define INIT_PCI_CYCLE (1<<9) 104 #define GPPM_CMD(X) (((X)&0xf)<<4) 105 #define GPPM_BYTEEN(X) ((X)&0xf) 106 #define PCI_UNLOCKREG 0x04003C 107 #define UNLOCK_SSID(X) (((X)&0xff)<<8) 108 #define UNLOCK_SETUP(X) (((X)&0xff)<<0) 109 #define UNLOCK_MAGIC 0xCA 110 #define PCI_DEV_VEND_ID 0x040040 111 #define DEVICE_ID(X) (((X)>>16)&0xffff) 112 #define VENDOR_ID(X) (((X)&0xffff)) 113 #define PCI_CFG_CMDSTAT 0x040044 114 #define PCI_CFG_STATUS(X) (((X)>>16)&0xffff) 115 #define PCI_CFG_COMMAND(X) ((X)&0xffff) 116 #define PCI_CLASS_REV 0x040048 117 #define PCI_CLASSCODE(X) (((X)>>8)&0xffffff) 118 #define PCI_REVID(X) ((X)&0xff) 119 #define PCI_LAT_TMR 0x04004c 120 #define PCI_BASE10 0x040050 121 #define PCI_BASE14 0x040054 122 #define PCI_BASE18 0x040058 123 #define PCI_SUBSYS_ID 0x04006c 124 #define PCI_CAP_PTR 0x040074 125 #define PCI_CFG_MISC 0x04007c 126 #define PCI_PMC 0x040080 127 #define PCI_PWR_STATE 0x040084 128 #define PCI_IO 0x040088 129 #define PCI_SLVTUNING 0x04008C 130 #define PCI_DMATUNING 0x040090 131 #define PCI_DMAEADDR 0x040800 132 #define PCI_DMAIADDR 0x040804 133 #define PCI_DMALEN 0x040808 134 #define PCI_DMACTRL 0x04080C 135 #define PCI_XIOCTRL 0x040810 136 #define PCI_SEL0PROF 0x040814 137 #define PCI_SEL1PROF 0x040818 138 #define PCI_SEL2PROF 0x04081C 139 #define PCI_GPXIOADDR 0x040820 140 #define PCI_NANDCTRLS 0x400830 141 #define PCI_SEL3PROF 0x040834 142 #define PCI_SEL4PROF 0x040838 143 #define PCI_GPXIO_STAT 0x040FB0 144 #define PCI_GPXIO_IMASK 0x040FB4 145 #define PCI_GPXIO_ICLR 0x040FB8 146 #define PCI_GPXIO_ISET 0x040FBC 147 #define PCI_GPPM_STATUS 0x040FC0 148 #define GPPM_DONE (1<<10) 149 #define GPPM_ERR (1<<9) 150 #define GPPM_MPAR_ERR (1<<8) 151 #define GPPM_PAR_ERR (1<<7) 152 #define GPPM_R_MABORT (1<<2) 153 #define GPPM_R_TABORT (1<<1) 154 #define PCI_GPPM_IMASK 0x040FC4 155 #define PCI_GPPM_ICLR 0x040FC8 156 #define PCI_GPPM_ISET 0x040FCC 157 #define PCI_DMA_STATUS 0x040FD0 158 #define PCI_DMA_IMASK 0x040FD4 159 #define PCI_DMA_ICLR 0x040FD8 160 #define PCI_DMA_ISET 0x040FDC 161 #define PCI_ISTATUS 0x040FE0 162 #define PCI_IMASK 0x040FE4 163 #define PCI_ICLR 0x040FE8 164 #define PCI_ISET 0x040FEC 165 #define PCI_MOD_ID 0x040FFC 166 167 /* 168 * PCI configuration cycle AD bus definition 169 */ 170 /* Type 0 */ 171 #define PCI_CFG_TYPE0_REG_SHF 0 172 #define PCI_CFG_TYPE0_FUNC_SHF 8 173 174 /* Type 1 */ 175 #define PCI_CFG_TYPE1_REG_SHF 0 176 #define PCI_CFG_TYPE1_FUNC_SHF 8 177 #define PCI_CFG_TYPE1_DEV_SHF 11 178 #define PCI_CFG_TYPE1_BUS_SHF 16 179 180 /* 181 * Ethernet device DP83816 definition 182 */ 183 #define DP83816_IRQ_ETHER 66 184 185 #endif 186