1 /* $Id$ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. 8 */ 9 #ifndef _ASM_SN_PCI_PCIBR_PRIVATE_H 10 #define _ASM_SN_PCI_PCIBR_PRIVATE_H 11 12 /* 13 * pcibr_private.h -- private definitions for pcibr 14 * only the pcibr driver (and its closest friends) 15 * should ever peek into this file. 16 */ 17 18 #include <linux/config.h> 19 #include <linux/pci.h> 20 #include <asm/sn/pci/pcibr.h> 21 #include <asm/sn/pci/pciio_private.h> 22 #include <asm/sn/ksys/l1.h> 23 24 /* 25 * convenience typedefs 26 */ 27 28 typedef uint64_t pcibr_DMattr_t; 29 typedef uint32_t pcibr_ATEattr_t; 30 31 typedef struct pcibr_info_s *pcibr_info_t, **pcibr_info_h; 32 typedef struct pcibr_soft_s *pcibr_soft_t; 33 typedef struct pcibr_soft_slot_s *pcibr_soft_slot_t; 34 typedef struct pcibr_hints_s *pcibr_hints_t; 35 typedef struct pcibr_intr_list_s *pcibr_intr_list_t; 36 typedef struct pcibr_intr_wrap_s *pcibr_intr_wrap_t; 37 typedef struct pcibr_intr_cbuf_s *pcibr_intr_cbuf_t; 38 39 typedef volatile unsigned *cfg_p; 40 typedef volatile bridgereg_t *reg_p; 41 42 /* 43 * extern functions 44 */ 45 cfg_p pcibr_slot_config_addr(bridge_t *, pciio_slot_t, int); 46 cfg_p pcibr_func_config_addr(bridge_t *, pciio_bus_t bus, pciio_slot_t, pciio_function_t, int); 47 unsigned pcibr_slot_config_get(bridge_t *, pciio_slot_t, int); 48 unsigned pcibr_func_config_get(bridge_t *, pciio_slot_t, pciio_function_t, int); 49 void pcibr_debug(uint32_t, vertex_hdl_t, char *, ...); 50 void pcibr_slot_config_set(bridge_t *, pciio_slot_t, int, unsigned); 51 void pcibr_func_config_set(bridge_t *, pciio_slot_t, pciio_function_t, int, 52 unsigned); 53 /* 54 * PCIBR_DEBUG() macro and debug bitmask defines 55 */ 56 /* low freqency debug events (ie. initialization, resource allocation,...) */ 57 #define PCIBR_DEBUG_INIT 0x00000001 /* bridge init */ 58 #define PCIBR_DEBUG_HINTS 0x00000002 /* bridge hints */ 59 #define PCIBR_DEBUG_ATTACH 0x00000004 /* bridge attach */ 60 #define PCIBR_DEBUG_DETACH 0x00000008 /* bridge detach */ 61 #define PCIBR_DEBUG_ATE 0x00000010 /* bridge ATE allocation */ 62 #define PCIBR_DEBUG_RRB 0x00000020 /* bridge RRB allocation */ 63 #define PCIBR_DEBUG_RBAR 0x00000040 /* bridge RBAR allocation */ 64 #define PCIBR_DEBUG_PROBE 0x00000080 /* bridge device probing */ 65 #define PCIBR_DEBUG_INTR_ERROR 0x00000100 /* bridge error interrupt */ 66 #define PCIBR_DEBUG_ERROR_HDLR 0x00000200 /* bridge error handler */ 67 #define PCIBR_DEBUG_CONFIG 0x00000400 /* device's config space */ 68 #define PCIBR_DEBUG_BAR 0x00000800 /* device's BAR allocations */ 69 #define PCIBR_DEBUG_INTR_ALLOC 0x00001000 /* device's intr allocation */ 70 #define PCIBR_DEBUG_DEV_ATTACH 0x00002000 /* device's attach */ 71 #define PCIBR_DEBUG_DEV_DETACH 0x00004000 /* device's detach */ 72 #define PCIBR_DEBUG_HOTPLUG 0x00008000 73 74 /* high freqency debug events (ie. map allocation, direct translation,...) */ 75 #define PCIBR_DEBUG_DEVREG 0x04000000 /* bridges device reg sets */ 76 #define PCIBR_DEBUG_PIOMAP 0x08000000 /* pcibr_piomap */ 77 #define PCIBR_DEBUG_PIODIR 0x10000000 /* pcibr_piotrans */ 78 #define PCIBR_DEBUG_DMAMAP 0x20000000 /* pcibr_dmamap */ 79 #define PCIBR_DEBUG_DMADIR 0x40000000 /* pcibr_dmatrans */ 80 #define PCIBR_DEBUG_INTR 0x80000000 /* interrupts */ 81 82 extern char *pcibr_debug_module; 83 extern int pcibr_debug_widget; 84 extern int pcibr_debug_slot; 85 extern uint32_t pcibr_debug_mask; 86 87 /* For low frequency events (ie. initialization, resource allocation,...) */ 88 #define PCIBR_DEBUG_ALWAYS(args) pcibr_debug args ; 89 90 /* XXX: habeck: maybe make PCIBR_DEBUG() always available? Even in non- 91 * debug kernels? If tracing isn't enabled (i.e pcibr_debug_mask isn't 92 * set, then the overhead for this macro is just an extra 'if' check. 93 */ 94 /* For high frequency events (ie. map allocation, direct translation,...) */ 95 #if 1 || DEBUG 96 #define PCIBR_DEBUG(args) PCIBR_DEBUG_ALWAYS(args) 97 #else /* DEBUG */ 98 #define PCIBR_DEBUG(args) 99 #endif /* DEBUG */ 100 101 /* 102 * Bridge sets up PIO using this information. 103 */ 104 struct pcibr_piomap_s { 105 struct pciio_piomap_s bp_pp; /* generic stuff */ 106 107 #define bp_flags bp_pp.pp_flags /* PCIBR_PIOMAP flags */ 108 #define bp_dev bp_pp.pp_dev /* associated pci card */ 109 #define bp_slot bp_pp.pp_slot /* which slot the card is in */ 110 #define bp_space bp_pp.pp_space /* which address space */ 111 #define bp_pciaddr bp_pp.pp_pciaddr /* starting offset of mapping */ 112 #define bp_mapsz bp_pp.pp_mapsz /* size of this mapping */ 113 #define bp_kvaddr bp_pp.pp_kvaddr /* kernel virtual address to use */ 114 115 iopaddr_t bp_xtalk_addr; /* corresponding xtalk address */ 116 xtalk_piomap_t bp_xtalk_pio; /* corresponding xtalk resource */ 117 pcibr_piomap_t bp_next; /* Next piomap on the list */ 118 pcibr_soft_t bp_soft; /* backpointer to bridge soft data */ 119 atomic_t bp_toc[1]; /* PCI timeout counter */ 120 121 }; 122 123 /* 124 * Bridge sets up DMA using this information. 125 */ 126 struct pcibr_dmamap_s { 127 struct pciio_dmamap_s bd_pd; 128 #define bd_flags bd_pd.pd_flags /* PCIBR_DMAMAP flags */ 129 #define bd_dev bd_pd.pd_dev /* associated pci card */ 130 #define bd_slot bd_pd.pd_slot /* which slot the card is in */ 131 struct pcibr_soft_s *bd_soft; /* pcibr soft state backptr */ 132 xtalk_dmamap_t bd_xtalk; /* associated xtalk resources */ 133 134 size_t bd_max_size; /* maximum size of mapping */ 135 xwidgetnum_t bd_xio_port; /* target XIO port */ 136 iopaddr_t bd_xio_addr; /* target XIO address */ 137 iopaddr_t bd_pci_addr; /* via PCI address */ 138 139 int bd_ate_index; /* Address Translation Entry Index */ 140 int bd_ate_count; /* number of ATE's allocated */ 141 bridge_ate_p bd_ate_ptr; /* where to write first ATE */ 142 bridge_ate_t bd_ate_proto; /* prototype ATE (for xioaddr=0) */ 143 bridge_ate_t bd_ate_prime; /* value of 1st ATE written */ 144 }; 145 146 #define IBUFSIZE 5 /* size of circular buffer (holds 4) */ 147 148 /* 149 * Circular buffer used for interrupt processing 150 */ 151 struct pcibr_intr_cbuf_s { 152 spinlock_t ib_lock; /* cbuf 'put' lock */ 153 int ib_in; /* index of next free entry */ 154 int ib_out; /* index of next full entry */ 155 pcibr_intr_wrap_t ib_cbuf[IBUFSIZE]; /* circular buffer of wrap */ 156 }; 157 158 /* 159 * Bridge sets up interrupts using this information. 160 */ 161 162 struct pcibr_intr_s { 163 struct pciio_intr_s bi_pi; 164 #define bi_flags bi_pi.pi_flags /* PCIBR_INTR flags */ 165 #define bi_dev bi_pi.pi_dev /* associated pci card */ 166 #define bi_lines bi_pi.pi_lines /* which PCI interrupt line(s) */ 167 #define bi_func bi_pi.pi_func /* handler function (when connected) */ 168 #define bi_arg bi_pi.pi_arg /* handler parameter (when connected) */ 169 #define bi_mustruncpu bi_pi.pi_mustruncpu /* Where we must run. */ 170 #define bi_irq bi_pi.pi_irq /* IRQ assigned. */ 171 #define bi_cpu bi_pi.pi_cpu /* cpu assigned. */ 172 unsigned bi_ibits; /* which Bridge interrupt bit(s) */ 173 pcibr_soft_t bi_soft; /* shortcut to soft info */ 174 struct pcibr_intr_cbuf_s bi_ibuf; /* circular buffer of wrap ptrs */ 175 unsigned bi_last_intr; /* For Shub lb lost intr. bug */ 176 }; 177 178 179 /* 180 * PCIBR_INFO_SLOT_GET_EXT returns the external slot number that the card 181 * resides in. (i.e the slot number silk screened on the back of the I/O 182 * brick). PCIBR_INFO_SLOT_GET_INT returns the internal slot (or device) 183 * number used by the pcibr code to represent that external slot (i.e to 184 * set bit patterns in BRIDGE/PIC registers to represent the device, or to 185 * offset into an array, or ...). 186 * 187 * In BRIDGE and XBRIDGE the external slot and internal device numbering 188 * are the same. (0->0, 1->1, 2->2,... 7->7) BUT in the PIC the external 189 * slot number is always 1 greater than the internal device number (1->0, 190 * 2->1, 3->2, 4->3). This is due to the fact that the PCI-X spec requires 191 * that the 'bridge' (i.e PIC) be designated as 'device 0', thus external 192 * slot numbering can't start at zero. 193 * 194 * PCIBR_DEVICE_TO_SLOT converts an internal device number to an external 195 * slot number. NOTE: PCIIO_SLOT_NONE stays as PCIIO_SLOT_NONE. 196 * 197 * PCIBR_SLOT_TO_DEVICE converts an external slot number to an internal 198 * device number. NOTE: PCIIO_SLOT_NONE stays as PCIIO_SLOT_NONE. 199 */ 200 #define PCIBR_INFO_SLOT_GET_EXT(info) (((pcibr_info_t)info)->f_slot) 201 #define PCIBR_INFO_SLOT_GET_INT(info) (((pcibr_info_t)info)->f_dev) 202 203 #define PCIBR_DEVICE_TO_SLOT(pcibr_soft, dev_num) \ 204 (((dev_num) != PCIIO_SLOT_NONE) ? \ 205 (IS_PIC_SOFT((pcibr_soft)) ? ((dev_num) + 1) : (dev_num)) : \ 206 PCIIO_SLOT_NONE) 207 208 #define PCIBR_SLOT_TO_DEVICE(pcibr_soft, slot) \ 209 (((slot) != PCIIO_SLOT_NONE) ? \ 210 (IS_PIC_SOFT((pcibr_soft)) ? ((slot) - 1) : (slot)) : \ 211 PCIIO_SLOT_NONE) 212 213 /* 214 * per-connect point pcibr data, including standard pciio data in-line: 215 */ 216 struct pcibr_info_s { 217 struct pciio_info_s f_c; /* MUST BE FIRST. */ 218 #define f_vertex f_c.c_vertex /* back pointer to vertex */ 219 #define f_bus f_c.c_bus /* which bus the card is in */ 220 #define f_slot f_c.c_slot /* which slot the card is in */ 221 #define f_func f_c.c_func /* which func (on multi-func cards) */ 222 #define f_vendor f_c.c_vendor /* PCI card "vendor" code */ 223 #define f_device f_c.c_device /* PCI card "device" code */ 224 #define f_master f_c.c_master /* PCI bus provider */ 225 #define f_mfast f_c.c_mfast /* cached fastinfo from c_master */ 226 #define f_pops f_c.c_pops /* cached provider from c_master */ 227 #define f_efunc f_c.c_efunc /* error handling function */ 228 #define f_einfo f_c.c_einfo /* first parameter for efunc */ 229 #define f_window f_c.c_window /* state of BASE regs */ 230 #define f_rwindow f_c.c_rwindow /* expansion ROM BASE regs */ 231 #define f_rbase f_c.c_rbase /* expansion ROM base */ 232 #define f_rsize f_c.c_rsize /* expansion ROM size */ 233 #define f_piospace f_c.c_piospace /* additional I/O spaces allocated */ 234 235 /* pcibr-specific connection state */ 236 int f_ibit[4]; /* Bridge bit for each INTx */ 237 pcibr_piomap_t f_piomap; 238 int f_att_det_error; 239 pciio_slot_t f_dev; /* which device the card represents */ 240 cap_pcix_type0_t *f_pcix_cap; /* pointer to the pcix capability */ 241 }; 242 243 /* ===================================================================== 244 * Shared Interrupt Information 245 */ 246 247 struct pcibr_intr_list_s { 248 pcibr_intr_list_t il_next; 249 pcibr_intr_t il_intr; 250 volatile bridgereg_t *il_wrbf; /* ptr to b_wr_req_buf[] */ 251 }; 252 253 /* ===================================================================== 254 * Interrupt Wrapper Data 255 */ 256 struct pcibr_intr_wrap_s { 257 pcibr_soft_t iw_soft; /* which bridge */ 258 volatile bridgereg_t *iw_stat; /* ptr to b_int_status */ 259 bridgereg_t iw_ibit; /* bit in b_int_status */ 260 pcibr_intr_list_t iw_list; /* ghostbusters! */ 261 int iw_hdlrcnt; /* running handler count */ 262 int iw_shared; /* if Bridge bit is shared */ 263 int iw_connected; /* if already connected */ 264 }; 265 266 #define PCIBR_ISR_ERR_START 8 267 #define PCIBR_ISR_MAX_ERRS_BRIDGE 32 268 #define PCIBR_ISR_MAX_ERRS_PIC 45 269 #define PCIBR_ISR_MAX_ERRS PCIBR_ISR_MAX_ERRS_PIC 270 271 /* 272 * PCI Base Address Register window allocation constants. 273 * To reduce the size of the internal resource mapping structures, do 274 * not use the entire PCI bus I/O address space 275 */ 276 #define PCIBR_BUS_IO_BASE 0x100000 277 #define PCIBR_BUS_IO_MAX 0x0FFFFFFF 278 #define PCIBR_BUS_IO_PAGE 0x100000 279 280 #define PCIBR_BUS_SWIN_BASE PAGE_SIZE 281 #define PCIBR_BUS_SWIN_MAX 0x000FFFFF 282 #define PCIBR_BUS_SWIN_PAGE PAGE_SIZE 283 284 #define PCIBR_BUS_MEM_BASE 0x200000 285 #define PCIBR_BUS_MEM_MAX 0x3FFFFFFF 286 #define PCIBR_BUS_MEM_PAGE 0x100000 287 288 /* defines for pcibr_soft_s->bs_bridge_type */ 289 #define PCIBR_BRIDGETYPE_BRIDGE 0 290 #define PCIBR_BRIDGETYPE_XBRIDGE 1 291 #define PCIBR_BRIDGETYPE_PIC 2 292 #define IS_XBRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_XBRIDGE) 293 #define IS_PIC_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_PIC) 294 #define IS_PIC_BUSNUM_SOFT(ps, bus) \ 295 (IS_PIC_SOFT(ps) && ((ps)->bs_busnum == (bus))) 296 #define IS_BRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_BRIDGE) 297 #define IS_XBRIDGE_OR_PIC_SOFT(ps) (IS_XBRIDGE_SOFT(ps) || IS_PIC_SOFT(ps)) 298 299 /* 300 * Runtime checks for workarounds. 301 */ 302 #define PCIBR_WAR_ENABLED(pv, pcibr_soft) \ 303 ((1 << XWIDGET_PART_REV_NUM_REV(pcibr_soft->bs_rev_num)) & pv) 304 /* 305 * Defines for individual WARs. Each is a bitmask of applicable 306 * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B, etc. 307 */ 308 #define PV854697 (~0) /* PIC: write 64bit regs as 64bits. permanent */ 309 #define PV854827 (~0) /* PIC: fake widget 0xf presence bit. permanent */ 310 #define PV855271 (1 << 1) /* PIC: PIC: use virt chan iff 64-bit device. */ 311 #define PV855272 (1 << 1) /* PIC: runaway interrupt WAR */ 312 #define PV856155 (1 << 1) /* PIC: arbitration WAR */ 313 #define PV856864 (1 << 1) /* PIC: lower timeout to free TNUMs quicker */ 314 #define PV856866 (1 << 1) /* PIC: avoid rrb's 0/1/8/9. */ 315 #define PV862253 (1 << 1) /* PIC: don't enable write req RAM parity checking */ 316 #define PV867308 (3 << 1) /* PIC: make LLP error interrupts FATAL for PIC */ 317 318 319 /* defines for pcibr_soft_s->bs_bridge_mode */ 320 #define PCIBR_BRIDGEMODE_PCI_33 0x0 321 #define PCIBR_BRIDGEMODE_PCI_66 0x2 322 #define PCIBR_BRIDGEMODE_PCIX_66 0x3 323 #define PCIBR_BRIDGEMODE_PCIX_100 0x5 324 #define PCIBR_BRIDGEMODE_PCIX_133 0x7 325 #define BUSSPEED_MASK 0x6 326 #define BUSTYPE_MASK 0x1 327 328 #define IS_PCI(ps) (!IS_PCIX(ps)) 329 #define IS_PCIX(ps) ((ps)->bs_bridge_mode & BUSTYPE_MASK) 330 331 #define IS_33MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCI_33) 332 #define IS_66MHZ(ps) (((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCI_66) || \ 333 ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_66)) 334 #define IS_100MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_100) 335 #define IS_133MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_133) 336 337 338 /* Number of PCI slots. NOTE: this works as long as the first slot 339 * is zero. Otherwise use ((ps->bs_max_slot+1) - ps->bs_min_slot) 340 */ 341 #define PCIBR_NUM_SLOTS(ps) (ps->bs_max_slot+1) 342 343 /* ===================================================================== 344 * Bridge Device State structure 345 * 346 * one instance of this structure is kept for each 347 * Bridge ASIC in the system. 348 */ 349 350 struct pcibr_soft_s { 351 vertex_hdl_t bs_conn; /* xtalk connection point */ 352 vertex_hdl_t bs_vhdl; /* vertex owned by pcibr */ 353 uint64_t bs_int_enable; /* Mask of enabled intrs */ 354 bridge_t *bs_base; /* PIO pointer to Bridge chip */ 355 char *bs_name; /* hw graph name */ 356 xwidgetnum_t bs_xid; /* Bridge's xtalk ID number */ 357 vertex_hdl_t bs_master; /* xtalk master vertex */ 358 xwidgetnum_t bs_mxid; /* master's xtalk ID number */ 359 pciio_slot_t bs_first_slot; /* first existing slot */ 360 pciio_slot_t bs_last_slot; /* last existing slot */ 361 pciio_slot_t bs_last_reset; /* last slot to reset */ 362 pciio_slot_t bs_min_slot; /* lowest possible slot */ 363 pciio_slot_t bs_max_slot; /* highest possible slot */ 364 pcibr_soft_t bs_peers_soft; /* PICs other bus's soft */ 365 int bs_busnum; /* PIC has two pci busses */ 366 367 iopaddr_t bs_dir_xbase; /* xtalk address for 32-bit PCI direct map */ 368 xwidgetnum_t bs_dir_xport; /* xtalk port for 32-bit PCI direct map */ 369 370 struct resource bs_int_ate_resource;/* root resource for internal ATEs */ 371 struct resource bs_ext_ate_resource;/* root resource for external ATEs */ 372 void *bs_allocated_ate_res;/* resource struct allocated */ 373 short bs_int_ate_size; /* number of internal ates */ 374 short bs_bridge_type; /* see defines above */ 375 short bs_bridge_mode; /* see defines above */ 376 int bs_rev_num; /* revision number of Bridge */ 377 378 /* bs_dma_flags are the forced dma flags used on all DMAs. Used for 379 * working around ASIC rev issues and protocol specific requirements 380 */ 381 unsigned bs_dma_flags; /* forced DMA flags */ 382 383 moduleid_t bs_moduleid; /* io brick moduleid */ 384 short bs_bricktype; /* io brick type */ 385 386 /* 387 * Lock used primarily to get mutual exclusion while managing any 388 * bridge resources.. 389 */ 390 spinlock_t bs_lock; 391 392 vertex_hdl_t bs_noslot_conn; /* NO-SLOT connection point */ 393 pcibr_info_t bs_noslot_info; 394 struct pcibr_soft_slot_s { 395 /* information we keep about each CFG slot */ 396 397 /* some devices (ioc3 in non-slotted 398 * configurations, sometimes) make use 399 * of more than one REQ/GNT/INT* signal 400 * sets. The slot corresponding to the 401 * IDSEL that the device responds to is 402 * called the host slot; the slot 403 * numbers that the device is stealing 404 * REQ/GNT/INT bits from are known as 405 * the guest slots. 406 */ 407 int has_host; 408 pciio_slot_t host_slot; 409 vertex_hdl_t slot_conn; 410 411 /* PCI Hot-Plug status word */ 412 int slot_status; 413 414 /* Potentially several connection points 415 * for this slot. bss_ninfo is how many, 416 * and bss_infos is a pointer to 417 * an array pcibr_info_t values (which are 418 * pointers to pcibr_info structs, stored 419 * as device_info in connection ponts). 420 */ 421 int bss_ninfo; 422 pcibr_info_h bss_infos; 423 424 /* Temporary Compatibility Macros, for 425 * stuff that has moved out of bs_slot 426 * and into the info structure. These 427 * will go away when their users have 428 * converted over to multifunction- 429 * friendly use of bss_{ninfo,infos}. 430 */ 431 #define bss_vendor_id bss_infos[0]->f_vendor 432 #define bss_device_id bss_infos[0]->f_device 433 #define bss_window bss_infos[0]->f_window 434 #define bssw_space w_space 435 #define bssw_base w_base 436 #define bssw_size w_size 437 438 /* Where is DevIO(x) pointing? */ 439 /* bssd_space is NONE if it is not assigned. */ 440 struct { 441 pciio_space_t bssd_space; 442 iopaddr_t bssd_base; 443 int bssd_ref_cnt; 444 } bss_devio; 445 446 /* Shadow value for Device(x) register, 447 * so we don't have to go to the chip. 448 */ 449 bridgereg_t bss_device; 450 451 /* Number of sets on GBR/REALTIME bit outstanding 452 * Used by Priority I/O for tracking reservations 453 */ 454 int bss_pri_uctr; 455 456 /* Number of "uses" of PMU, 32-bit direct, 457 * and 64-bit direct DMA (0:none, <0: trans, 458 * >0: how many dmamaps). Device(x) bits 459 * controlling attribute of each kind of 460 * channel can't be changed by dmamap_alloc 461 * or dmatrans if the controlling counter 462 * is nonzero. dmatrans is forever. 463 */ 464 int bss_pmu_uctr; 465 int bss_d32_uctr; 466 int bss_d64_uctr; 467 468 /* When the contents of mapping configuration 469 * information is locked down by dmatrans, 470 * repeated checks of the same flags should 471 * be shortcircuited for efficiency. 472 */ 473 iopaddr_t bss_d64_base; 474 unsigned bss_d64_flags; 475 iopaddr_t bss_d32_base; 476 unsigned bss_d32_flags; 477 478 /* Shadow information used for implementing 479 * Bridge Hardware WAR #484930 480 */ 481 atomic_t bss_ext_ates_active; 482 volatile unsigned *bss_cmd_pointer; 483 unsigned bss_cmd_shadow; 484 485 } bs_slot[8]; 486 487 pcibr_intr_bits_f *bs_intr_bits; 488 489 /* PIC PCI-X Read Buffer Management : 490 * bs_pcix_num_funcs: the total number of PCI-X functions 491 * on the bus 492 * bs_pcix_split_tot: total number of outstanding split 493 * transactions requested by all functions on the bus 494 * bs_pcix_rbar_percent_allowed: the percentage of the 495 * total number of buffers a function requested that are 496 * available to it, not including the 1 RBAR guaranteed 497 * to it. 498 * bs_pcix_rbar_inuse: number of RBARs in use. 499 * bs_pcix_rbar_avail: number of RBARs available. NOTE: 500 * this value can go negative if we oversubscribe the 501 * RBARs. (i.e. We have 16 RBARs but 17 functions). 502 */ 503 int bs_pcix_num_funcs; 504 int bs_pcix_split_tot; 505 int bs_pcix_rbar_percent_allowed; 506 507 int bs_pcix_rbar_inuse; 508 int bs_pcix_rbar_avail; 509 510 511 /* RRB MANAGEMENT 512 * bs_rrb_fixed: bitmap of slots whose RRB 513 * allocations we should not "automatically" change 514 * bs_rrb_avail: number of RRBs that have not 515 * been allocated or reserved for {even,odd} slots 516 * bs_rrb_res: number of RRBs currently reserved for the 517 * use of the index slot number 518 * bs_rrb_res_dflt: number of RRBs reserved at boot 519 * time for the use of the index slot number 520 * bs_rrb_valid: number of RRBs currently marked valid 521 * for the indexed slot/vchan number; array[slot][vchan] 522 * bs_rrb_valid_dflt: number of RRBs marked valid at boot 523 * time for the indexed slot/vchan number; array[slot][vchan] 524 */ 525 int bs_rrb_fixed; 526 int bs_rrb_avail[2]; 527 int bs_rrb_res[8]; 528 int bs_rrb_res_dflt[8]; 529 int bs_rrb_valid[8][4]; 530 int bs_rrb_valid_dflt[8][4]; 531 struct { 532 /* Each Bridge interrupt bit has a single XIO 533 * interrupt channel allocated. 534 */ 535 xtalk_intr_t bsi_xtalk_intr; 536 /* 537 * A wrapper structure is associated with each 538 * Bridge interrupt bit. 539 */ 540 struct pcibr_intr_wrap_s bsi_pcibr_intr_wrap; 541 542 } bs_intr[8]; 543 544 xtalk_intr_t bsi_err_intr; 545 546 /* 547 * We stash away some information in this structure on getting 548 * an error interrupt. This information is used during PIO read/ 549 * write error handling. 550 * 551 * As it stands now, we do not re-enable the error interrupt 552 * till the error is resolved. Error resolution happens either at 553 * bus error time for PIO Read errors (~100 microseconds), or at 554 * the scheduled timeout time for PIO write errors (~milliseconds). 555 * If this delay causes problems, we may need to move towards 556 * a different scheme.. 557 * 558 * Note that there is no locking while looking at this data structure. 559 * There should not be any race between bus error code and 560 * error interrupt code.. will look into this if needed. 561 * 562 * NOTE: The above discussion of error interrupt processing is 563 * no longer true. Whether it should again be true, is 564 * being looked into. 565 */ 566 struct br_errintr_info { 567 int bserr_toutcnt; 568 #ifdef LATER 569 toid_t bserr_toutid; /* Timeout started by errintr */ 570 #endif /* LATER */ 571 iopaddr_t bserr_addr; /* Address where error occured */ 572 uint64_t bserr_intstat; /* interrupts active at error dump */ 573 } bs_errinfo; 574 575 /* 576 * PCI Bus Space allocation data structure. 577 * 578 * The resource mapping functions rmalloc() and rmfree() are used 579 * to manage the PCI bus I/O, small window, and memory address 580 * spaces. 581 * 582 * This info is used to assign PCI bus space addresses to cards 583 * via their BARs and to the callers of the pcibr_piospace_alloc() 584 * interface. 585 * 586 * Users of the pcibr_piospace_alloc() interface, such as the VME 587 * Universe chip, need PCI bus space that is not acquired by BARs. 588 * Most of these users need "large" amounts of PIO space (typically 589 * in Megabytes), and they generally tend to take once and never 590 * release. 591 */ 592 struct pciio_win_map_s bs_io_win_map; /* I/O addr space */ 593 struct pciio_win_map_s bs_swin_map; /* Small window addr space */ 594 struct pciio_win_map_s bs_mem_win_map; /* Memory addr space */ 595 596 struct resource bs_io_win_root_resource; /* I/O addr space */ 597 struct resource bs_swin_root_resource; /* Small window addr space */ 598 struct resource bs_mem_win_root_resource; /* Memory addr space */ 599 600 int bs_bus_addr_status; /* Bus space status */ 601 602 #define PCIBR_BUS_ADDR_MEM_FREED 1 /* Reserved PROM mem addr freed */ 603 #define PCIBR_BUS_ADDR_IO_FREED 2 /* Reserved PROM I/O addr freed */ 604 605 struct bs_errintr_stat_s { 606 uint32_t bs_errcount_total; 607 uint32_t bs_lasterr_timestamp; 608 uint32_t bs_lasterr_snapshot; 609 } bs_errintr_stat[PCIBR_ISR_MAX_ERRS]; 610 611 /* 612 * Bridge-wide endianness control for 613 * large-window PIO mappings 614 * 615 * These fields are set to PCIIO_BYTE_SWAP 616 * or PCIIO_WORD_VALUES once the swapper 617 * has been configured, one way or the other, 618 * for the direct windows. If they are zero, 619 * nobody has a PIO mapping through that window, 620 * and the swapper can be set either way. 621 */ 622 unsigned bs_pio_end_io; 623 unsigned bs_pio_end_mem; 624 }; 625 626 #define PCIBR_ERRTIME_THRESHOLD (100) 627 #define PCIBR_ERRRATE_THRESHOLD (100) 628 629 /* 630 * pcibr will respond to hints dropped in its vertex 631 * using the following structure. 632 */ 633 struct pcibr_hints_s { 634 /* ph_host_slot is actually +1 so "0" means "no host" */ 635 pciio_slot_t ph_host_slot[8]; /* REQ/GNT/INT in use by ... */ 636 unsigned ph_rrb_fixed; /* do not change RRB allocations */ 637 unsigned ph_hands_off; /* prevent further pcibr operations */ 638 rrb_alloc_funct_t rrb_alloc_funct; /* do dynamic rrb allocation */ 639 pcibr_intr_bits_f *ph_intr_bits; /* map PCI INT[ABCD] to Bridge Int(n) */ 640 }; 641 642 /* 643 * Number of bridge non-fatal error interrupts we can see before 644 * we decide to disable that interrupt. 645 */ 646 #define PCIBR_ERRINTR_DISABLE_LEVEL 10000 647 648 /* ===================================================================== 649 * Bridge (pcibr) state management functions 650 * 651 * pcibr_soft_get is here because we do it in a lot 652 * of places and I want to make sure they all stay 653 * in step with each other. 654 * 655 * pcibr_soft_set is here because I want it to be 656 * closely associated with pcibr_soft_get, even 657 * though it is only called in one place. 658 */ 659 660 #define pcibr_soft_get(v) ((pcibr_soft_t)hwgraph_fastinfo_get((v))) 661 #define pcibr_soft_set(v,i) (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i))) 662 663 /* 664 * mem alloc/free macros 665 */ 666 #define NEWAf(ptr,n,f) (ptr = snia_kmem_zalloc((n)*sizeof (*(ptr)))) 667 #define NEWA(ptr,n) (ptr = snia_kmem_zalloc((n)*sizeof (*(ptr)))) 668 #define DELA(ptr,n) (kfree(ptr)) 669 670 #define NEWf(ptr,f) NEWAf(ptr,1,f) 671 #define NEW(ptr) NEWA(ptr,1) 672 #define DEL(ptr) DELA(ptr,1) 673 674 /* 675 * Additional PIO spaces per slot are 676 * recorded in this structure. 677 */ 678 struct pciio_piospace_s { 679 pciio_piospace_t next; /* another space for this device */ 680 char free; /* 1 if free, 0 if in use */ 681 pciio_space_t space; /* Which space is in use */ 682 iopaddr_t start; /* Starting address of the PIO space */ 683 size_t count; /* size of PIO space */ 684 }; 685 686 /* Use io spin locks. This ensures that all the PIO writes from a particular 687 * CPU to a particular IO device are synched before the start of the next 688 * set of PIO operations to the same device. 689 */ 690 #ifdef PCI_LATER 691 #define pcibr_lock(pcibr_soft) io_splock(pcibr_soft->bs_lock) 692 #define pcibr_unlock(pcibr_soft, s) io_spunlock(pcibr_soft->bs_lock,s) 693 #else 694 #define pcibr_lock(pcibr_soft) 1 695 #define pcibr_unlock(pcibr_soft, s) 696 #endif /* PCI_LATER */ 697 698 #define PCIBR_VALID_SLOT(ps, s) (s < PCIBR_NUM_SLOTS(ps)) 699 #define PCIBR_D64_BASE_UNSET (0xFFFFFFFFFFFFFFFF) 700 #define PCIBR_D32_BASE_UNSET (0xFFFFFFFF) 701 #define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev" 702 703 #define PCIBR_SOFT_LIST 1 704 #if PCIBR_SOFT_LIST 705 typedef struct pcibr_list_s *pcibr_list_p; 706 struct pcibr_list_s { 707 pcibr_list_p bl_next; 708 pcibr_soft_t bl_soft; 709 vertex_hdl_t bl_vhdl; 710 }; 711 #endif /* PCIBR_SOFT_LIST */ 712 713 714 // Devices per widget: 2 buses, 2 slots per bus, 8 functions per slot. 715 #define DEV_PER_WIDGET (2*2*8) 716 717 struct sn_flush_device_list { 718 int bus; 719 int pin; 720 struct bar_list { 721 unsigned long start; 722 unsigned long end; 723 } bar_list[PCI_ROM_RESOURCE]; 724 unsigned long force_int_addr; 725 volatile unsigned long flush_addr; 726 spinlock_t flush_lock; 727 }; 728 729 struct sn_flush_nasid_entry { 730 struct sn_flush_device_list **widget_p; 731 unsigned long iio_itte1; 732 unsigned long iio_itte2; 733 unsigned long iio_itte3; 734 unsigned long iio_itte4; 735 unsigned long iio_itte5; 736 unsigned long iio_itte6; 737 unsigned long iio_itte7; 738 }; 739 740 #endif /* _ASM_SN_PCI_PCIBR_PRIVATE_H */ 741