1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #ifndef __INTEL_LVDS_REGS_H__
7 #define __INTEL_LVDS_REGS_H__
8 
9 #include "intel_display_reg_defs.h"
10 
11 /* LVDS port control */
12 #define LVDS		_MMIO(0x61180)
13 /*
14  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
15  * the DPLL semantics change when the LVDS is assigned to that pipe.
16  */
17 #define   LVDS_PORT_EN			REG_BIT(31)
18 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
19 #define   LVDS_PIPE_SEL_MASK		REG_BIT(30)
20 #define   LVDS_PIPE_SEL(pipe)		REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (pipe))
21 #define   LVDS_PIPE_SEL_MASK_CPT	REG_GENMASK(30, 29)
22 #define   LVDS_PIPE_SEL_CPT(pipe)	REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (pipe))
23 /* LVDS dithering flag on 965/g4x platform */
24 #define   LVDS_ENABLE_DITHER		REG_BIT(25)
25 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
26 #define   LVDS_VSYNC_POLARITY		REG_BIT(21)
27 #define   LVDS_HSYNC_POLARITY		REG_BIT(20)
28 
29 /* Enable border for unscaled (or aspect-scaled) display */
30 #define   LVDS_BORDER_ENABLE		REG_BIT(15)
31 /*
32  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
33  * pixel.
34  */
35 #define   LVDS_A0A2_CLKA_POWER_MASK	REG_GENMASK(9, 8)
36 #define   LVDS_A0A2_CLKA_POWER_DOWN	REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 0)
37 #define   LVDS_A0A2_CLKA_POWER_UP	REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 3)
38 /*
39  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
40  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
41  * on.
42  */
43 #define   LVDS_A3_POWER_MASK		REG_GENMASK(7, 6)
44 #define   LVDS_A3_POWER_DOWN		REG_FIELD_PREP(LVDS_A3_POWER_MASK, 0)
45 #define   LVDS_A3_POWER_UP		REG_FIELD_PREP(LVDS_A3_POWER_MASK, 3)
46 /*
47  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
48  * is set.
49  */
50 #define   LVDS_CLKB_POWER_MASK		REG_GENMASK(5, 4)
51 #define   LVDS_CLKB_POWER_DOWN		REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 0)
52 #define   LVDS_CLKB_POWER_UP		REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 3)
53 /*
54  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
55  * setting for whether we are in dual-channel mode.  The B3 pair will
56  * additionally only be powered up when LVDS_A3_POWER_UP is set.
57  */
58 #define   LVDS_B0B3_POWER_MASK		REG_GENMASK(3, 2)
59 #define   LVDS_B0B3_POWER_DOWN		REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 0)
60 #define   LVDS_B0B3_POWER_UP		REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 3)
61 
62 #define PCH_LVDS	_MMIO(0xe1180)
63 #define   LVDS_DETECTED			REG_BIT(1)
64 
65 #endif /* __INTEL_LVDS_REGS_H__ */
66