1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /*
3  * hw.h - DesignWare HS OTG Controller hardware definitions
4  *
5  * Copyright 2004-2013 Synopsys, Inc.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. The names of the above-listed copyright holders may not be used
17  *    to endorse or promote products derived from this software without
18  *    specific prior written permission.
19  *
20  * ALTERNATIVELY, this software may be distributed under the terms of the
21  * GNU General Public License ("GPL") as published by the Free Software
22  * Foundation; either version 2 of the License, or (at your option) any
23  * later version.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __DWC2_HW_H__
39 #define __DWC2_HW_H__
40 
41 #define HSOTG_REG(x)	(x)
42 
43 #define GOTGCTL				HSOTG_REG(0x000)
44 #define GOTGCTL_CHIRPEN			BIT(27)
45 #define GOTGCTL_MULT_VALID_BC_MASK	(0x1f << 22)
46 #define GOTGCTL_MULT_VALID_BC_SHIFT	22
47 #define GOTGCTL_CURMODE_HOST		BIT(21)
48 #define GOTGCTL_OTGVER			BIT(20)
49 #define GOTGCTL_BSESVLD			BIT(19)
50 #define GOTGCTL_ASESVLD			BIT(18)
51 #define GOTGCTL_DBNC_SHORT		BIT(17)
52 #define GOTGCTL_CONID_B			BIT(16)
53 #define GOTGCTL_DBNCE_FLTR_BYPASS	BIT(15)
54 #define GOTGCTL_DEVHNPEN		BIT(11)
55 #define GOTGCTL_HSTSETHNPEN		BIT(10)
56 #define GOTGCTL_HNPREQ			BIT(9)
57 #define GOTGCTL_HSTNEGSCS		BIT(8)
58 #define GOTGCTL_BVALOVAL		BIT(7)
59 #define GOTGCTL_BVALOEN			BIT(6)
60 #define GOTGCTL_AVALOVAL		BIT(5)
61 #define GOTGCTL_AVALOEN			BIT(4)
62 #define GOTGCTL_VBVALOVAL		BIT(3)
63 #define GOTGCTL_VBVALOEN		BIT(2)
64 #define GOTGCTL_SESREQ			BIT(1)
65 #define GOTGCTL_SESREQSCS		BIT(0)
66 
67 #define GOTGINT				HSOTG_REG(0x004)
68 #define GOTGINT_DBNCE_DONE		BIT(19)
69 #define GOTGINT_A_DEV_TOUT_CHG		BIT(18)
70 #define GOTGINT_HST_NEG_DET		BIT(17)
71 #define GOTGINT_HST_NEG_SUC_STS_CHNG	BIT(9)
72 #define GOTGINT_SES_REQ_SUC_STS_CHNG	BIT(8)
73 #define GOTGINT_SES_END_DET		BIT(2)
74 
75 #define GAHBCFG				HSOTG_REG(0x008)
76 #define GAHBCFG_AHB_SINGLE		BIT(23)
77 #define GAHBCFG_NOTI_ALL_DMA_WRIT	BIT(22)
78 #define GAHBCFG_REM_MEM_SUPP		BIT(21)
79 #define GAHBCFG_P_TXF_EMP_LVL		BIT(8)
80 #define GAHBCFG_NP_TXF_EMP_LVL		BIT(7)
81 #define GAHBCFG_DMA_EN			BIT(5)
82 #define GAHBCFG_HBSTLEN_MASK		(0xf << 1)
83 #define GAHBCFG_HBSTLEN_SHIFT		1
84 #define GAHBCFG_HBSTLEN_SINGLE		0
85 #define GAHBCFG_HBSTLEN_INCR		1
86 #define GAHBCFG_HBSTLEN_INCR4		3
87 #define GAHBCFG_HBSTLEN_INCR8		5
88 #define GAHBCFG_HBSTLEN_INCR16		7
89 #define GAHBCFG_GLBL_INTR_EN		BIT(0)
90 #define GAHBCFG_CTRL_MASK		(GAHBCFG_P_TXF_EMP_LVL | \
91 					 GAHBCFG_NP_TXF_EMP_LVL | \
92 					 GAHBCFG_DMA_EN | \
93 					 GAHBCFG_GLBL_INTR_EN)
94 
95 #define GUSBCFG				HSOTG_REG(0x00C)
96 #define GUSBCFG_FORCEDEVMODE		BIT(30)
97 #define GUSBCFG_FORCEHOSTMODE		BIT(29)
98 #define GUSBCFG_TXENDDELAY		BIT(28)
99 #define GUSBCFG_ICTRAFFICPULLREMOVE	BIT(27)
100 #define GUSBCFG_ICUSBCAP		BIT(26)
101 #define GUSBCFG_ULPI_INT_PROT_DIS	BIT(25)
102 #define GUSBCFG_INDICATORPASSTHROUGH	BIT(24)
103 #define GUSBCFG_INDICATORCOMPLEMENT	BIT(23)
104 #define GUSBCFG_TERMSELDLPULSE		BIT(22)
105 #define GUSBCFG_ULPI_INT_VBUS_IND	BIT(21)
106 #define GUSBCFG_ULPI_EXT_VBUS_DRV	BIT(20)
107 #define GUSBCFG_ULPI_CLK_SUSP_M		BIT(19)
108 #define GUSBCFG_ULPI_AUTO_RES		BIT(18)
109 #define GUSBCFG_ULPI_FS_LS		BIT(17)
110 #define GUSBCFG_OTG_UTMI_FS_SEL		BIT(16)
111 #define GUSBCFG_PHY_LP_CLK_SEL		BIT(15)
112 #define GUSBCFG_USBTRDTIM_MASK		(0xf << 10)
113 #define GUSBCFG_USBTRDTIM_SHIFT		10
114 #define GUSBCFG_HNPCAP			BIT(9)
115 #define GUSBCFG_SRPCAP			BIT(8)
116 #define GUSBCFG_DDRSEL			BIT(7)
117 #define GUSBCFG_PHYSEL			BIT(6)
118 #define GUSBCFG_FSINTF			BIT(5)
119 #define GUSBCFG_ULPI_UTMI_SEL		BIT(4)
120 #define GUSBCFG_PHYIF16			BIT(3)
121 #define GUSBCFG_PHYIF8			(0 << 3)
122 #define GUSBCFG_TOUTCAL_MASK		(0x7 << 0)
123 #define GUSBCFG_TOUTCAL_SHIFT		0
124 #define GUSBCFG_TOUTCAL_LIMIT		0x7
125 #define GUSBCFG_TOUTCAL(_x)		((_x) << 0)
126 
127 #define GRSTCTL				HSOTG_REG(0x010)
128 #define GRSTCTL_AHBIDLE			BIT(31)
129 #define GRSTCTL_DMAREQ			BIT(30)
130 #define GRSTCTL_CSFTRST_DONE		BIT(29)
131 #define GRSTCTL_TXFNUM_MASK		(0x1f << 6)
132 #define GRSTCTL_TXFNUM_SHIFT		6
133 #define GRSTCTL_TXFNUM_LIMIT		0x1f
134 #define GRSTCTL_TXFNUM(_x)		((_x) << 6)
135 #define GRSTCTL_TXFFLSH			BIT(5)
136 #define GRSTCTL_RXFFLSH			BIT(4)
137 #define GRSTCTL_IN_TKNQ_FLSH		BIT(3)
138 #define GRSTCTL_FRMCNTRRST		BIT(2)
139 #define GRSTCTL_HSFTRST			BIT(1)
140 #define GRSTCTL_CSFTRST			BIT(0)
141 
142 #define GINTSTS				HSOTG_REG(0x014)
143 #define GINTMSK				HSOTG_REG(0x018)
144 #define GINTSTS_WKUPINT			BIT(31)
145 #define GINTSTS_SESSREQINT		BIT(30)
146 #define GINTSTS_DISCONNINT		BIT(29)
147 #define GINTSTS_CONIDSTSCHNG		BIT(28)
148 #define GINTSTS_LPMTRANRCVD		BIT(27)
149 #define GINTSTS_PTXFEMP			BIT(26)
150 #define GINTSTS_HCHINT			BIT(25)
151 #define GINTSTS_PRTINT			BIT(24)
152 #define GINTSTS_RESETDET		BIT(23)
153 #define GINTSTS_FET_SUSP		BIT(22)
154 #define GINTSTS_INCOMPL_IP		BIT(21)
155 #define GINTSTS_INCOMPL_SOOUT		BIT(21)
156 #define GINTSTS_INCOMPL_SOIN		BIT(20)
157 #define GINTSTS_OEPINT			BIT(19)
158 #define GINTSTS_IEPINT			BIT(18)
159 #define GINTSTS_EPMIS			BIT(17)
160 #define GINTSTS_RESTOREDONE		BIT(16)
161 #define GINTSTS_EOPF			BIT(15)
162 #define GINTSTS_ISOUTDROP		BIT(14)
163 #define GINTSTS_ENUMDONE		BIT(13)
164 #define GINTSTS_USBRST			BIT(12)
165 #define GINTSTS_USBSUSP			BIT(11)
166 #define GINTSTS_ERLYSUSP		BIT(10)
167 #define GINTSTS_I2CINT			BIT(9)
168 #define GINTSTS_ULPI_CK_INT		BIT(8)
169 #define GINTSTS_GOUTNAKEFF		BIT(7)
170 #define GINTSTS_GINNAKEFF		BIT(6)
171 #define GINTSTS_NPTXFEMP		BIT(5)
172 #define GINTSTS_RXFLVL			BIT(4)
173 #define GINTSTS_SOF			BIT(3)
174 #define GINTSTS_OTGINT			BIT(2)
175 #define GINTSTS_MODEMIS			BIT(1)
176 #define GINTSTS_CURMODE_HOST		BIT(0)
177 
178 #define GRXSTSR				HSOTG_REG(0x01C)
179 #define GRXSTSP				HSOTG_REG(0x020)
180 #define GRXSTS_FN_MASK			(0x7f << 25)
181 #define GRXSTS_FN_SHIFT			25
182 #define GRXSTS_PKTSTS_MASK		(0xf << 17)
183 #define GRXSTS_PKTSTS_SHIFT		17
184 #define GRXSTS_PKTSTS_GLOBALOUTNAK	1
185 #define GRXSTS_PKTSTS_OUTRX		2
186 #define GRXSTS_PKTSTS_HCHIN		2
187 #define GRXSTS_PKTSTS_OUTDONE		3
188 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP	3
189 #define GRXSTS_PKTSTS_SETUPDONE		4
190 #define GRXSTS_PKTSTS_DATATOGGLEERR	5
191 #define GRXSTS_PKTSTS_SETUPRX		6
192 #define GRXSTS_PKTSTS_HCHHALTED		7
193 #define GRXSTS_HCHNUM_MASK		(0xf << 0)
194 #define GRXSTS_HCHNUM_SHIFT		0
195 #define GRXSTS_DPID_MASK		(0x3 << 15)
196 #define GRXSTS_DPID_SHIFT		15
197 #define GRXSTS_BYTECNT_MASK		(0x7ff << 4)
198 #define GRXSTS_BYTECNT_SHIFT		4
199 #define GRXSTS_EPNUM_MASK		(0xf << 0)
200 #define GRXSTS_EPNUM_SHIFT		0
201 
202 #define GRXFSIZ				HSOTG_REG(0x024)
203 #define GRXFSIZ_DEPTH_MASK		(0xffff << 0)
204 #define GRXFSIZ_DEPTH_SHIFT		0
205 
206 #define GNPTXFSIZ			HSOTG_REG(0x028)
207 /* Use FIFOSIZE_* constants to access this register */
208 
209 #define GNPTXSTS			HSOTG_REG(0x02C)
210 #define GNPTXSTS_NP_TXQ_TOP_MASK		(0x7f << 24)
211 #define GNPTXSTS_NP_TXQ_TOP_SHIFT		24
212 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK		(0xff << 16)
213 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT		16
214 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v)	(((_v) >> 16) & 0xff)
215 #define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK		(0xffff << 0)
216 #define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT		0
217 #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v)	(((_v) >> 0) & 0xffff)
218 
219 #define GI2CCTL				HSOTG_REG(0x0030)
220 #define GI2CCTL_BSYDNE			BIT(31)
221 #define GI2CCTL_RW			BIT(30)
222 #define GI2CCTL_I2CDATSE0		BIT(28)
223 #define GI2CCTL_I2CDEVADDR_MASK		(0x3 << 26)
224 #define GI2CCTL_I2CDEVADDR_SHIFT	26
225 #define GI2CCTL_I2CSUSPCTL		BIT(25)
226 #define GI2CCTL_ACK			BIT(24)
227 #define GI2CCTL_I2CEN			BIT(23)
228 #define GI2CCTL_ADDR_MASK		(0x7f << 16)
229 #define GI2CCTL_ADDR_SHIFT		16
230 #define GI2CCTL_REGADDR_MASK		(0xff << 8)
231 #define GI2CCTL_REGADDR_SHIFT		8
232 #define GI2CCTL_RWDATA_MASK		(0xff << 0)
233 #define GI2CCTL_RWDATA_SHIFT		0
234 
235 #define GPVNDCTL			HSOTG_REG(0x0034)
236 #define GGPIO				HSOTG_REG(0x0038)
237 #define GGPIO_STM32_OTG_GCCFG_PWRDWN	BIT(16)
238 #define GGPIO_STM32_OTG_GCCFG_VBDEN	BIT(21)
239 #define GGPIO_STM32_OTG_GCCFG_IDEN	BIT(22)
240 
241 #define GUID				HSOTG_REG(0x003c)
242 #define GSNPSID				HSOTG_REG(0x0040)
243 #define GHWCFG1				HSOTG_REG(0x0044)
244 #define GSNPSID_ID_MASK			GENMASK(31, 16)
245 
246 #define GHWCFG2				HSOTG_REG(0x0048)
247 #define GHWCFG2_OTG_ENABLE_IC_USB		BIT(31)
248 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK		(0x1f << 26)
249 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT		26
250 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK	(0x3 << 24)
251 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT	24
252 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK	(0x3 << 22)
253 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT	22
254 #define GHWCFG2_MULTI_PROC_INT			BIT(20)
255 #define GHWCFG2_DYNAMIC_FIFO			BIT(19)
256 #define GHWCFG2_PERIO_EP_SUPPORTED		BIT(18)
257 #define GHWCFG2_NUM_HOST_CHAN_MASK		(0xf << 14)
258 #define GHWCFG2_NUM_HOST_CHAN_SHIFT		14
259 #define GHWCFG2_NUM_DEV_EP_MASK			(0xf << 10)
260 #define GHWCFG2_NUM_DEV_EP_SHIFT		10
261 #define GHWCFG2_FS_PHY_TYPE_MASK		(0x3 << 8)
262 #define GHWCFG2_FS_PHY_TYPE_SHIFT		8
263 #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED	0
264 #define GHWCFG2_FS_PHY_TYPE_DEDICATED		1
265 #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI		2
266 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI		3
267 #define GHWCFG2_HS_PHY_TYPE_MASK		(0x3 << 6)
268 #define GHWCFG2_HS_PHY_TYPE_SHIFT		6
269 #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED	0
270 #define GHWCFG2_HS_PHY_TYPE_UTMI		1
271 #define GHWCFG2_HS_PHY_TYPE_ULPI		2
272 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI		3
273 #define GHWCFG2_POINT2POINT			BIT(5)
274 #define GHWCFG2_ARCHITECTURE_MASK		(0x3 << 3)
275 #define GHWCFG2_ARCHITECTURE_SHIFT		3
276 #define GHWCFG2_SLAVE_ONLY_ARCH			0
277 #define GHWCFG2_EXT_DMA_ARCH			1
278 #define GHWCFG2_INT_DMA_ARCH			2
279 #define GHWCFG2_OP_MODE_MASK			(0x7 << 0)
280 #define GHWCFG2_OP_MODE_SHIFT			0
281 #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE		0
282 #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE	1
283 #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE	2
284 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE	3
285 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE	4
286 #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST	5
287 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST	6
288 #define GHWCFG2_OP_MODE_UNDEFINED		7
289 
290 #define GHWCFG3				HSOTG_REG(0x004c)
291 #define GHWCFG3_DFIFO_DEPTH_MASK		(0xffff << 16)
292 #define GHWCFG3_DFIFO_DEPTH_SHIFT		16
293 #define GHWCFG3_OTG_LPM_EN			BIT(15)
294 #define GHWCFG3_BC_SUPPORT			BIT(14)
295 #define GHWCFG3_OTG_ENABLE_HSIC			BIT(13)
296 #define GHWCFG3_ADP_SUPP			BIT(12)
297 #define GHWCFG3_SYNCH_RESET_TYPE		BIT(11)
298 #define GHWCFG3_OPTIONAL_FEATURES		BIT(10)
299 #define GHWCFG3_VENDOR_CTRL_IF			BIT(9)
300 #define GHWCFG3_I2C				BIT(8)
301 #define GHWCFG3_OTG_FUNC			BIT(7)
302 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK	(0x7 << 4)
303 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT	4
304 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK	(0xf << 0)
305 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT	0
306 
307 #define GHWCFG4				HSOTG_REG(0x0050)
308 #define GHWCFG4_DESC_DMA_DYN			BIT(31)
309 #define GHWCFG4_DESC_DMA			BIT(30)
310 #define GHWCFG4_NUM_IN_EPS_MASK			(0xf << 26)
311 #define GHWCFG4_NUM_IN_EPS_SHIFT		26
312 #define GHWCFG4_DED_FIFO_EN			BIT(25)
313 #define GHWCFG4_DED_FIFO_SHIFT		25
314 #define GHWCFG4_SESSION_END_FILT_EN		BIT(24)
315 #define GHWCFG4_B_VALID_FILT_EN			BIT(23)
316 #define GHWCFG4_A_VALID_FILT_EN			BIT(22)
317 #define GHWCFG4_VBUS_VALID_FILT_EN		BIT(21)
318 #define GHWCFG4_IDDIG_FILT_EN			BIT(20)
319 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK	(0xf << 16)
320 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT	16
321 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK	(0x3 << 14)
322 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT	14
323 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8		0
324 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16		1
325 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16	2
326 #define GHWCFG4_ACG_SUPPORTED			BIT(12)
327 #define GHWCFG4_IPG_ISOC_SUPPORTED		BIT(11)
328 #define GHWCFG4_SERVICE_INTERVAL_SUPPORTED      BIT(10)
329 #define GHWCFG4_XHIBER				BIT(7)
330 #define GHWCFG4_HIBER				BIT(6)
331 #define GHWCFG4_MIN_AHB_FREQ			BIT(5)
332 #define GHWCFG4_POWER_OPTIMIZ			BIT(4)
333 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK	(0xf << 0)
334 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT	0
335 
336 #define GLPMCFG				HSOTG_REG(0x0054)
337 #define GLPMCFG_INVSELHSIC		BIT(31)
338 #define GLPMCFG_HSICCON			BIT(30)
339 #define GLPMCFG_RSTRSLPSTS		BIT(29)
340 #define GLPMCFG_ENBESL			BIT(28)
341 #define GLPMCFG_LPM_RETRYCNT_STS_MASK	(0x7 << 25)
342 #define GLPMCFG_LPM_RETRYCNT_STS_SHIFT	25
343 #define GLPMCFG_SNDLPM			BIT(24)
344 #define GLPMCFG_RETRY_CNT_MASK		(0x7 << 21)
345 #define GLPMCFG_RETRY_CNT_SHIFT		21
346 #define GLPMCFG_LPM_REJECT_CTRL_CONTROL	BIT(21)
347 #define GLPMCFG_LPM_ACCEPT_CTRL_ISOC	BIT(22)
348 #define GLPMCFG_LPM_CHNL_INDX_MASK	(0xf << 17)
349 #define GLPMCFG_LPM_CHNL_INDX_SHIFT	17
350 #define GLPMCFG_L1RESUMEOK		BIT(16)
351 #define GLPMCFG_SLPSTS			BIT(15)
352 #define GLPMCFG_COREL1RES_MASK		(0x3 << 13)
353 #define GLPMCFG_COREL1RES_SHIFT		13
354 #define GLPMCFG_HIRD_THRES_MASK		(0x1f << 8)
355 #define GLPMCFG_HIRD_THRES_SHIFT	8
356 #define GLPMCFG_HIRD_THRES_EN		(0x10 << 8)
357 #define GLPMCFG_ENBLSLPM		BIT(7)
358 #define GLPMCFG_BREMOTEWAKE		BIT(6)
359 #define GLPMCFG_HIRD_MASK		(0xf << 2)
360 #define GLPMCFG_HIRD_SHIFT		2
361 #define GLPMCFG_APPL1RES		BIT(1)
362 #define GLPMCFG_LPMCAP			BIT(0)
363 
364 #define GPWRDN				HSOTG_REG(0x0058)
365 #define GPWRDN_MULT_VAL_ID_BC_MASK	(0x1f << 24)
366 #define GPWRDN_MULT_VAL_ID_BC_SHIFT	24
367 #define GPWRDN_ADP_INT			BIT(23)
368 #define GPWRDN_BSESSVLD			BIT(22)
369 #define GPWRDN_IDSTS			BIT(21)
370 #define GPWRDN_LINESTATE_MASK		(0x3 << 19)
371 #define GPWRDN_LINESTATE_SHIFT		19
372 #define GPWRDN_STS_CHGINT_MSK		BIT(18)
373 #define GPWRDN_STS_CHGINT		BIT(17)
374 #define GPWRDN_SRP_DET_MSK		BIT(16)
375 #define GPWRDN_SRP_DET			BIT(15)
376 #define GPWRDN_CONNECT_DET_MSK		BIT(14)
377 #define GPWRDN_CONNECT_DET		BIT(13)
378 #define GPWRDN_DISCONN_DET_MSK		BIT(12)
379 #define GPWRDN_DISCONN_DET		BIT(11)
380 #define GPWRDN_RST_DET_MSK		BIT(10)
381 #define GPWRDN_RST_DET			BIT(9)
382 #define GPWRDN_LNSTSCHG_MSK		BIT(8)
383 #define GPWRDN_LNSTSCHG			BIT(7)
384 #define GPWRDN_DIS_VBUS			BIT(6)
385 #define GPWRDN_PWRDNSWTCH		BIT(5)
386 #define GPWRDN_PWRDNRSTN		BIT(4)
387 #define GPWRDN_PWRDNCLMP		BIT(3)
388 #define GPWRDN_RESTORE			BIT(2)
389 #define GPWRDN_PMUACTV			BIT(1)
390 #define GPWRDN_PMUINTSEL		BIT(0)
391 
392 #define GDFIFOCFG			HSOTG_REG(0x005c)
393 #define GDFIFOCFG_EPINFOBASE_MASK	(0xffff << 16)
394 #define GDFIFOCFG_EPINFOBASE_SHIFT	16
395 #define GDFIFOCFG_GDFIFOCFG_MASK	(0xffff << 0)
396 #define GDFIFOCFG_GDFIFOCFG_SHIFT	0
397 
398 #define ADPCTL				HSOTG_REG(0x0060)
399 #define ADPCTL_AR_MASK			(0x3 << 27)
400 #define ADPCTL_AR_SHIFT			27
401 #define ADPCTL_ADP_TMOUT_INT_MSK	BIT(26)
402 #define ADPCTL_ADP_SNS_INT_MSK		BIT(25)
403 #define ADPCTL_ADP_PRB_INT_MSK		BIT(24)
404 #define ADPCTL_ADP_TMOUT_INT		BIT(23)
405 #define ADPCTL_ADP_SNS_INT		BIT(22)
406 #define ADPCTL_ADP_PRB_INT		BIT(21)
407 #define ADPCTL_ADPENA			BIT(20)
408 #define ADPCTL_ADPRES			BIT(19)
409 #define ADPCTL_ENASNS			BIT(18)
410 #define ADPCTL_ENAPRB			BIT(17)
411 #define ADPCTL_RTIM_MASK		(0x7ff << 6)
412 #define ADPCTL_RTIM_SHIFT		6
413 #define ADPCTL_PRB_PER_MASK		(0x3 << 4)
414 #define ADPCTL_PRB_PER_SHIFT		4
415 #define ADPCTL_PRB_DELTA_MASK		(0x3 << 2)
416 #define ADPCTL_PRB_DELTA_SHIFT		2
417 #define ADPCTL_PRB_DSCHRG_MASK		(0x3 << 0)
418 #define ADPCTL_PRB_DSCHRG_SHIFT		0
419 
420 #define GREFCLK				    HSOTG_REG(0x0064)
421 #define GREFCLK_REFCLKPER_MASK		    (0x1ffff << 15)
422 #define GREFCLK_REFCLKPER_SHIFT		    15
423 #define GREFCLK_REF_CLK_MODE		    BIT(14)
424 #define GREFCLK_SOF_CNT_WKUP_ALERT_MASK	    (0x3ff)
425 #define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT    0
426 
427 #define GINTMSK2			HSOTG_REG(0x0068)
428 #define GINTMSK2_WKUP_ALERT_INT_MSK	BIT(0)
429 
430 #define GINTSTS2			HSOTG_REG(0x006c)
431 #define GINTSTS2_WKUP_ALERT_INT		BIT(0)
432 
433 #define HPTXFSIZ			HSOTG_REG(0x100)
434 /* Use FIFOSIZE_* constants to access this register */
435 
436 #define DPTXFSIZN(_a)			HSOTG_REG(0x104 + (((_a) - 1) * 4))
437 /* Use FIFOSIZE_* constants to access this register */
438 
439 /* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
440 #define FIFOSIZE_DEPTH_MASK		(0xffff << 16)
441 #define FIFOSIZE_DEPTH_SHIFT		16
442 #define FIFOSIZE_STARTADDR_MASK		(0xffff << 0)
443 #define FIFOSIZE_STARTADDR_SHIFT	0
444 #define FIFOSIZE_DEPTH_GET(_x)		(((_x) >> 16) & 0xffff)
445 
446 /* Device mode registers */
447 
448 #define DCFG				HSOTG_REG(0x800)
449 #define DCFG_DESCDMA_EN			BIT(23)
450 #define DCFG_EPMISCNT_MASK		(0x1f << 18)
451 #define DCFG_EPMISCNT_SHIFT		18
452 #define DCFG_EPMISCNT_LIMIT		0x1f
453 #define DCFG_EPMISCNT(_x)		((_x) << 18)
454 #define DCFG_IPG_ISOC_SUPPORDED		BIT(17)
455 #define DCFG_PERFRINT_MASK		(0x3 << 11)
456 #define DCFG_PERFRINT_SHIFT		11
457 #define DCFG_PERFRINT_LIMIT		0x3
458 #define DCFG_PERFRINT(_x)		((_x) << 11)
459 #define DCFG_DEVADDR_MASK		(0x7f << 4)
460 #define DCFG_DEVADDR_SHIFT		4
461 #define DCFG_DEVADDR_LIMIT		0x7f
462 #define DCFG_DEVADDR(_x)		((_x) << 4)
463 #define DCFG_NZ_STS_OUT_HSHK		BIT(2)
464 #define DCFG_DEVSPD_MASK		(0x3 << 0)
465 #define DCFG_DEVSPD_SHIFT		0
466 #define DCFG_DEVSPD_HS			0
467 #define DCFG_DEVSPD_FS			1
468 #define DCFG_DEVSPD_LS			2
469 #define DCFG_DEVSPD_FS48		3
470 
471 #define DCTL				HSOTG_REG(0x804)
472 #define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
473 #define DCTL_PWRONPRGDONE		BIT(11)
474 #define DCTL_CGOUTNAK			BIT(10)
475 #define DCTL_SGOUTNAK			BIT(9)
476 #define DCTL_CGNPINNAK			BIT(8)
477 #define DCTL_SGNPINNAK			BIT(7)
478 #define DCTL_TSTCTL_MASK		(0x7 << 4)
479 #define DCTL_TSTCTL_SHIFT		4
480 #define DCTL_GOUTNAKSTS			BIT(3)
481 #define DCTL_GNPINNAKSTS		BIT(2)
482 #define DCTL_SFTDISCON			BIT(1)
483 #define DCTL_RMTWKUPSIG			BIT(0)
484 
485 #define DSTS				HSOTG_REG(0x808)
486 #define DSTS_SOFFN_MASK			(0x3fff << 8)
487 #define DSTS_SOFFN_SHIFT		8
488 #define DSTS_SOFFN_LIMIT		0x3fff
489 #define DSTS_SOFFN(_x)			((_x) << 8)
490 #define DSTS_ERRATICERR			BIT(3)
491 #define DSTS_ENUMSPD_MASK		(0x3 << 1)
492 #define DSTS_ENUMSPD_SHIFT		1
493 #define DSTS_ENUMSPD_HS			0
494 #define DSTS_ENUMSPD_FS			1
495 #define DSTS_ENUMSPD_LS			2
496 #define DSTS_ENUMSPD_FS48		3
497 #define DSTS_SUSPSTS			BIT(0)
498 
499 #define DIEPMSK				HSOTG_REG(0x810)
500 #define DIEPMSK_NAKMSK			BIT(13)
501 #define DIEPMSK_BNAININTRMSK		BIT(9)
502 #define DIEPMSK_TXFIFOUNDRNMSK		BIT(8)
503 #define DIEPMSK_TXFIFOEMPTY		BIT(7)
504 #define DIEPMSK_INEPNAKEFFMSK		BIT(6)
505 #define DIEPMSK_INTKNEPMISMSK		BIT(5)
506 #define DIEPMSK_INTKNTXFEMPMSK		BIT(4)
507 #define DIEPMSK_TIMEOUTMSK		BIT(3)
508 #define DIEPMSK_AHBERRMSK		BIT(2)
509 #define DIEPMSK_EPDISBLDMSK		BIT(1)
510 #define DIEPMSK_XFERCOMPLMSK		BIT(0)
511 
512 #define DOEPMSK				HSOTG_REG(0x814)
513 #define DOEPMSK_BNAMSK			BIT(9)
514 #define DOEPMSK_BACK2BACKSETUP		BIT(6)
515 #define DOEPMSK_STSPHSERCVDMSK		BIT(5)
516 #define DOEPMSK_OUTTKNEPDISMSK		BIT(4)
517 #define DOEPMSK_SETUPMSK		BIT(3)
518 #define DOEPMSK_AHBERRMSK		BIT(2)
519 #define DOEPMSK_EPDISBLDMSK		BIT(1)
520 #define DOEPMSK_XFERCOMPLMSK		BIT(0)
521 
522 #define DAINT				HSOTG_REG(0x818)
523 #define DAINTMSK			HSOTG_REG(0x81C)
524 #define DAINT_OUTEP_SHIFT		16
525 #define DAINT_OUTEP(_x)			(1 << ((_x) + 16))
526 #define DAINT_INEP(_x)			(1 << (_x))
527 
528 #define DTKNQR1				HSOTG_REG(0x820)
529 #define DTKNQR2				HSOTG_REG(0x824)
530 #define DTKNQR3				HSOTG_REG(0x830)
531 #define DTKNQR4				HSOTG_REG(0x834)
532 #define DIEPEMPMSK			HSOTG_REG(0x834)
533 
534 #define DVBUSDIS			HSOTG_REG(0x828)
535 #define DVBUSPULSE			HSOTG_REG(0x82C)
536 
537 #define DIEPCTL0			HSOTG_REG(0x900)
538 #define DIEPCTL(_a)			HSOTG_REG(0x900 + ((_a) * 0x20))
539 
540 #define DOEPCTL0			HSOTG_REG(0xB00)
541 #define DOEPCTL(_a)			HSOTG_REG(0xB00 + ((_a) * 0x20))
542 
543 /* EP0 specialness:
544  * bits[29..28] - reserved (no SetD0PID, SetD1PID)
545  * bits[25..22] - should always be zero, this isn't a periodic endpoint
546  * bits[10..0]  - MPS setting different for EP0
547  */
548 #define D0EPCTL_MPS_MASK		(0x3 << 0)
549 #define D0EPCTL_MPS_SHIFT		0
550 #define D0EPCTL_MPS_64			0
551 #define D0EPCTL_MPS_32			1
552 #define D0EPCTL_MPS_16			2
553 #define D0EPCTL_MPS_8			3
554 
555 #define DXEPCTL_EPENA			BIT(31)
556 #define DXEPCTL_EPDIS			BIT(30)
557 #define DXEPCTL_SETD1PID		BIT(29)
558 #define DXEPCTL_SETODDFR		BIT(29)
559 #define DXEPCTL_SETD0PID		BIT(28)
560 #define DXEPCTL_SETEVENFR		BIT(28)
561 #define DXEPCTL_SNAK			BIT(27)
562 #define DXEPCTL_CNAK			BIT(26)
563 #define DXEPCTL_TXFNUM_MASK		(0xf << 22)
564 #define DXEPCTL_TXFNUM_SHIFT		22
565 #define DXEPCTL_TXFNUM_LIMIT		0xf
566 #define DXEPCTL_TXFNUM(_x)		((_x) << 22)
567 #define DXEPCTL_STALL			BIT(21)
568 #define DXEPCTL_SNP			BIT(20)
569 #define DXEPCTL_EPTYPE_MASK		(0x3 << 18)
570 #define DXEPCTL_EPTYPE_CONTROL		(0x0 << 18)
571 #define DXEPCTL_EPTYPE_ISO		(0x1 << 18)
572 #define DXEPCTL_EPTYPE_BULK		(0x2 << 18)
573 #define DXEPCTL_EPTYPE_INTERRUPT	(0x3 << 18)
574 
575 #define DXEPCTL_NAKSTS			BIT(17)
576 #define DXEPCTL_DPID			BIT(16)
577 #define DXEPCTL_EOFRNUM			BIT(16)
578 #define DXEPCTL_USBACTEP		BIT(15)
579 #define DXEPCTL_NEXTEP_MASK		(0xf << 11)
580 #define DXEPCTL_NEXTEP_SHIFT		11
581 #define DXEPCTL_NEXTEP_LIMIT		0xf
582 #define DXEPCTL_NEXTEP(_x)		((_x) << 11)
583 #define DXEPCTL_MPS_MASK		(0x7ff << 0)
584 #define DXEPCTL_MPS_SHIFT		0
585 #define DXEPCTL_MPS_LIMIT		0x7ff
586 #define DXEPCTL_MPS(_x)			((_x) << 0)
587 
588 #define DIEPINT(_a)			HSOTG_REG(0x908 + ((_a) * 0x20))
589 #define DOEPINT(_a)			HSOTG_REG(0xB08 + ((_a) * 0x20))
590 #define DXEPINT_SETUP_RCVD		BIT(15)
591 #define DXEPINT_NYETINTRPT		BIT(14)
592 #define DXEPINT_NAKINTRPT		BIT(13)
593 #define DXEPINT_BBLEERRINTRPT		BIT(12)
594 #define DXEPINT_PKTDRPSTS		BIT(11)
595 #define DXEPINT_BNAINTR			BIT(9)
596 #define DXEPINT_TXFIFOUNDRN		BIT(8)
597 #define DXEPINT_OUTPKTERR		BIT(8)
598 #define DXEPINT_TXFEMP			BIT(7)
599 #define DXEPINT_INEPNAKEFF		BIT(6)
600 #define DXEPINT_BACK2BACKSETUP		BIT(6)
601 #define DXEPINT_INTKNEPMIS		BIT(5)
602 #define DXEPINT_STSPHSERCVD		BIT(5)
603 #define DXEPINT_INTKNTXFEMP		BIT(4)
604 #define DXEPINT_OUTTKNEPDIS		BIT(4)
605 #define DXEPINT_TIMEOUT			BIT(3)
606 #define DXEPINT_SETUP			BIT(3)
607 #define DXEPINT_AHBERR			BIT(2)
608 #define DXEPINT_EPDISBLD		BIT(1)
609 #define DXEPINT_XFERCOMPL		BIT(0)
610 
611 #define DIEPTSIZ0			HSOTG_REG(0x910)
612 #define DIEPTSIZ0_PKTCNT_MASK		(0x3 << 19)
613 #define DIEPTSIZ0_PKTCNT_SHIFT		19
614 #define DIEPTSIZ0_PKTCNT_LIMIT		0x3
615 #define DIEPTSIZ0_PKTCNT(_x)		((_x) << 19)
616 #define DIEPTSIZ0_XFERSIZE_MASK		(0x7f << 0)
617 #define DIEPTSIZ0_XFERSIZE_SHIFT	0
618 #define DIEPTSIZ0_XFERSIZE_LIMIT	0x7f
619 #define DIEPTSIZ0_XFERSIZE(_x)		((_x) << 0)
620 
621 #define DOEPTSIZ0			HSOTG_REG(0xB10)
622 #define DOEPTSIZ0_SUPCNT_MASK		(0x3 << 29)
623 #define DOEPTSIZ0_SUPCNT_SHIFT		29
624 #define DOEPTSIZ0_SUPCNT_LIMIT		0x3
625 #define DOEPTSIZ0_SUPCNT(_x)		((_x) << 29)
626 #define DOEPTSIZ0_PKTCNT		BIT(19)
627 #define DOEPTSIZ0_XFERSIZE_MASK		(0x7f << 0)
628 #define DOEPTSIZ0_XFERSIZE_SHIFT	0
629 
630 #define DIEPTSIZ(_a)			HSOTG_REG(0x910 + ((_a) * 0x20))
631 #define DOEPTSIZ(_a)			HSOTG_REG(0xB10 + ((_a) * 0x20))
632 #define DXEPTSIZ_MC_MASK		(0x3 << 29)
633 #define DXEPTSIZ_MC_SHIFT		29
634 #define DXEPTSIZ_MC_LIMIT		0x3
635 #define DXEPTSIZ_MC(_x)			((_x) << 29)
636 #define DXEPTSIZ_PKTCNT_MASK		(0x3ff << 19)
637 #define DXEPTSIZ_PKTCNT_SHIFT		19
638 #define DXEPTSIZ_PKTCNT_LIMIT		0x3ff
639 #define DXEPTSIZ_PKTCNT_GET(_v)		(((_v) >> 19) & 0x3ff)
640 #define DXEPTSIZ_PKTCNT(_x)		((_x) << 19)
641 #define DXEPTSIZ_XFERSIZE_MASK		(0x7ffff << 0)
642 #define DXEPTSIZ_XFERSIZE_SHIFT		0
643 #define DXEPTSIZ_XFERSIZE_LIMIT		0x7ffff
644 #define DXEPTSIZ_XFERSIZE_GET(_v)	(((_v) >> 0) & 0x7ffff)
645 #define DXEPTSIZ_XFERSIZE(_x)		((_x) << 0)
646 
647 #define DIEPDMA(_a)			HSOTG_REG(0x914 + ((_a) * 0x20))
648 #define DOEPDMA(_a)			HSOTG_REG(0xB14 + ((_a) * 0x20))
649 
650 #define DTXFSTS(_a)			HSOTG_REG(0x918 + ((_a) * 0x20))
651 
652 #define PCGCTL				HSOTG_REG(0x0e00)
653 #define PCGCTL_IF_DEV_MODE		BIT(31)
654 #define PCGCTL_P2HD_PRT_SPD_MASK	(0x3 << 29)
655 #define PCGCTL_P2HD_PRT_SPD_SHIFT	29
656 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK	(0x3 << 27)
657 #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT	27
658 #define PCGCTL_MAC_DEV_ADDR_MASK	(0x7f << 20)
659 #define PCGCTL_MAC_DEV_ADDR_SHIFT	20
660 #define PCGCTL_MAX_TERMSEL		BIT(19)
661 #define PCGCTL_MAX_XCVRSELECT_MASK	(0x3 << 17)
662 #define PCGCTL_MAX_XCVRSELECT_SHIFT	17
663 #define PCGCTL_PORT_POWER		BIT(16)
664 #define PCGCTL_PRT_CLK_SEL_MASK		(0x3 << 14)
665 #define PCGCTL_PRT_CLK_SEL_SHIFT	14
666 #define PCGCTL_ESS_REG_RESTORED		BIT(13)
667 #define PCGCTL_EXTND_HIBER_SWITCH	BIT(12)
668 #define PCGCTL_EXTND_HIBER_PWRCLMP	BIT(11)
669 #define PCGCTL_ENBL_EXTND_HIBER		BIT(10)
670 #define PCGCTL_RESTOREMODE		BIT(9)
671 #define PCGCTL_RESETAFTSUSP		BIT(8)
672 #define PCGCTL_DEEP_SLEEP		BIT(7)
673 #define PCGCTL_PHY_IN_SLEEP		BIT(6)
674 #define PCGCTL_ENBL_SLEEP_GATING	BIT(5)
675 #define PCGCTL_RSTPDWNMODULE		BIT(3)
676 #define PCGCTL_PWRCLMP			BIT(2)
677 #define PCGCTL_GATEHCLK			BIT(1)
678 #define PCGCTL_STOPPCLK			BIT(0)
679 
680 #define PCGCCTL1                        HSOTG_REG(0xe04)
681 #define PCGCCTL1_TIMER                  (0x3 << 1)
682 #define PCGCCTL1_GATEEN                 BIT(0)
683 
684 #define EPFIFO(_a)			HSOTG_REG(0x1000 + ((_a) * 0x1000))
685 
686 /* Host Mode Registers */
687 
688 #define HCFG				HSOTG_REG(0x0400)
689 #define HCFG_MODECHTIMEN		BIT(31)
690 #define HCFG_PERSCHEDENA		BIT(26)
691 #define HCFG_FRLISTEN_MASK		(0x3 << 24)
692 #define HCFG_FRLISTEN_SHIFT		24
693 #define HCFG_FRLISTEN_8				(0 << 24)
694 #define FRLISTEN_8_SIZE				8
695 #define HCFG_FRLISTEN_16			BIT(24)
696 #define FRLISTEN_16_SIZE			16
697 #define HCFG_FRLISTEN_32			(2 << 24)
698 #define FRLISTEN_32_SIZE			32
699 #define HCFG_FRLISTEN_64			(3 << 24)
700 #define FRLISTEN_64_SIZE			64
701 #define HCFG_DESCDMA			BIT(23)
702 #define HCFG_RESVALID_MASK		(0xff << 8)
703 #define HCFG_RESVALID_SHIFT		8
704 #define HCFG_ENA32KHZ			BIT(7)
705 #define HCFG_FSLSSUPP			BIT(2)
706 #define HCFG_FSLSPCLKSEL_MASK		(0x3 << 0)
707 #define HCFG_FSLSPCLKSEL_SHIFT		0
708 #define HCFG_FSLSPCLKSEL_30_60_MHZ	0
709 #define HCFG_FSLSPCLKSEL_48_MHZ		1
710 #define HCFG_FSLSPCLKSEL_6_MHZ		2
711 
712 #define HFIR				HSOTG_REG(0x0404)
713 #define HFIR_FRINT_MASK			(0xffff << 0)
714 #define HFIR_FRINT_SHIFT		0
715 #define HFIR_RLDCTRL			BIT(16)
716 
717 #define HFNUM				HSOTG_REG(0x0408)
718 #define HFNUM_FRREM_MASK		(0xffff << 16)
719 #define HFNUM_FRREM_SHIFT		16
720 #define HFNUM_FRNUM_MASK		(0xffff << 0)
721 #define HFNUM_FRNUM_SHIFT		0
722 #define HFNUM_MAX_FRNUM			0x3fff
723 
724 #define HPTXSTS				HSOTG_REG(0x0410)
725 #define TXSTS_QTOP_ODD			BIT(31)
726 #define TXSTS_QTOP_CHNEP_MASK		(0xf << 27)
727 #define TXSTS_QTOP_CHNEP_SHIFT		27
728 #define TXSTS_QTOP_TOKEN_MASK		(0x3 << 25)
729 #define TXSTS_QTOP_TOKEN_SHIFT		25
730 #define TXSTS_QTOP_TERMINATE		BIT(24)
731 #define TXSTS_QSPCAVAIL_MASK		(0xff << 16)
732 #define TXSTS_QSPCAVAIL_SHIFT		16
733 #define TXSTS_FSPCAVAIL_MASK		(0xffff << 0)
734 #define TXSTS_FSPCAVAIL_SHIFT		0
735 
736 #define HAINT				HSOTG_REG(0x0414)
737 #define HAINTMSK			HSOTG_REG(0x0418)
738 #define HFLBADDR			HSOTG_REG(0x041c)
739 
740 #define HPRT0				HSOTG_REG(0x0440)
741 #define HPRT0_SPD_MASK			(0x3 << 17)
742 #define HPRT0_SPD_SHIFT			17
743 #define HPRT0_SPD_HIGH_SPEED		0
744 #define HPRT0_SPD_FULL_SPEED		1
745 #define HPRT0_SPD_LOW_SPEED		2
746 #define HPRT0_TSTCTL_MASK		(0xf << 13)
747 #define HPRT0_TSTCTL_SHIFT		13
748 #define HPRT0_PWR			BIT(12)
749 #define HPRT0_LNSTS_MASK		(0x3 << 10)
750 #define HPRT0_LNSTS_SHIFT		10
751 #define HPRT0_RST			BIT(8)
752 #define HPRT0_SUSP			BIT(7)
753 #define HPRT0_RES			BIT(6)
754 #define HPRT0_OVRCURRCHG		BIT(5)
755 #define HPRT0_OVRCURRACT		BIT(4)
756 #define HPRT0_ENACHG			BIT(3)
757 #define HPRT0_ENA			BIT(2)
758 #define HPRT0_CONNDET			BIT(1)
759 #define HPRT0_CONNSTS			BIT(0)
760 
761 #define HCCHAR(_ch)			HSOTG_REG(0x0500 + 0x20 * (_ch))
762 #define HCCHAR_CHENA			BIT(31)
763 #define HCCHAR_CHDIS			BIT(30)
764 #define HCCHAR_ODDFRM			BIT(29)
765 #define HCCHAR_DEVADDR_MASK		(0x7f << 22)
766 #define HCCHAR_DEVADDR_SHIFT		22
767 #define HCCHAR_MULTICNT_MASK		(0x3 << 20)
768 #define HCCHAR_MULTICNT_SHIFT		20
769 #define HCCHAR_EPTYPE_MASK		(0x3 << 18)
770 #define HCCHAR_EPTYPE_SHIFT		18
771 #define HCCHAR_LSPDDEV			BIT(17)
772 #define HCCHAR_EPDIR			BIT(15)
773 #define HCCHAR_EPNUM_MASK		(0xf << 11)
774 #define HCCHAR_EPNUM_SHIFT		11
775 #define HCCHAR_MPS_MASK			(0x7ff << 0)
776 #define HCCHAR_MPS_SHIFT		0
777 
778 #define HCSPLT(_ch)			HSOTG_REG(0x0504 + 0x20 * (_ch))
779 #define HCSPLT_SPLTENA			BIT(31)
780 #define HCSPLT_COMPSPLT			BIT(16)
781 #define HCSPLT_XACTPOS_MASK		(0x3 << 14)
782 #define HCSPLT_XACTPOS_SHIFT		14
783 #define HCSPLT_XACTPOS_MID		0
784 #define HCSPLT_XACTPOS_END		1
785 #define HCSPLT_XACTPOS_BEGIN		2
786 #define HCSPLT_XACTPOS_ALL		3
787 #define HCSPLT_HUBADDR_MASK		(0x7f << 7)
788 #define HCSPLT_HUBADDR_SHIFT		7
789 #define HCSPLT_PRTADDR_MASK		(0x7f << 0)
790 #define HCSPLT_PRTADDR_SHIFT		0
791 
792 #define HCINT(_ch)			HSOTG_REG(0x0508 + 0x20 * (_ch))
793 #define HCINTMSK(_ch)			HSOTG_REG(0x050c + 0x20 * (_ch))
794 #define HCINTMSK_RESERVED14_31		(0x3ffff << 14)
795 #define HCINTMSK_FRM_LIST_ROLL		BIT(13)
796 #define HCINTMSK_XCS_XACT		BIT(12)
797 #define HCINTMSK_BNA			BIT(11)
798 #define HCINTMSK_DATATGLERR		BIT(10)
799 #define HCINTMSK_FRMOVRUN		BIT(9)
800 #define HCINTMSK_BBLERR			BIT(8)
801 #define HCINTMSK_XACTERR		BIT(7)
802 #define HCINTMSK_NYET			BIT(6)
803 #define HCINTMSK_ACK			BIT(5)
804 #define HCINTMSK_NAK			BIT(4)
805 #define HCINTMSK_STALL			BIT(3)
806 #define HCINTMSK_AHBERR			BIT(2)
807 #define HCINTMSK_CHHLTD			BIT(1)
808 #define HCINTMSK_XFERCOMPL		BIT(0)
809 
810 #define HCTSIZ(_ch)			HSOTG_REG(0x0510 + 0x20 * (_ch))
811 #define TSIZ_DOPNG			BIT(31)
812 #define TSIZ_SC_MC_PID_MASK		(0x3 << 29)
813 #define TSIZ_SC_MC_PID_SHIFT		29
814 #define TSIZ_SC_MC_PID_DATA0		0
815 #define TSIZ_SC_MC_PID_DATA2		1
816 #define TSIZ_SC_MC_PID_DATA1		2
817 #define TSIZ_SC_MC_PID_MDATA		3
818 #define TSIZ_SC_MC_PID_SETUP		3
819 #define TSIZ_PKTCNT_MASK		(0x3ff << 19)
820 #define TSIZ_PKTCNT_SHIFT		19
821 #define TSIZ_NTD_MASK			(0xff << 8)
822 #define TSIZ_NTD_SHIFT			8
823 #define TSIZ_SCHINFO_MASK		(0xff << 0)
824 #define TSIZ_SCHINFO_SHIFT		0
825 #define TSIZ_XFERSIZE_MASK		(0x7ffff << 0)
826 #define TSIZ_XFERSIZE_SHIFT		0
827 
828 #define HCDMA(_ch)			HSOTG_REG(0x0514 + 0x20 * (_ch))
829 
830 #define HCDMAB(_ch)			HSOTG_REG(0x051c + 0x20 * (_ch))
831 
832 #define HCFIFO(_ch)			HSOTG_REG(0x1000 + 0x1000 * (_ch))
833 
834 /**
835  * struct dwc2_dma_desc - DMA descriptor structure,
836  * used for both host and gadget modes
837  *
838  * @status: DMA descriptor status quadlet
839  * @buf:    DMA descriptor data buffer pointer
840  *
841  * DMA Descriptor structure contains two quadlets:
842  * Status quadlet and Data buffer pointer.
843  */
844 struct dwc2_dma_desc {
845 	u32 status;
846 	u32 buf;
847 } __packed;
848 
849 /* Host Mode DMA descriptor status quadlet */
850 
851 #define HOST_DMA_A			BIT(31)
852 #define HOST_DMA_STS_MASK		(0x3 << 28)
853 #define HOST_DMA_STS_SHIFT		28
854 #define HOST_DMA_STS_PKTERR		BIT(28)
855 #define HOST_DMA_EOL			BIT(26)
856 #define HOST_DMA_IOC			BIT(25)
857 #define HOST_DMA_SUP			BIT(24)
858 #define HOST_DMA_ALT_QTD		BIT(23)
859 #define HOST_DMA_QTD_OFFSET_MASK	(0x3f << 17)
860 #define HOST_DMA_QTD_OFFSET_SHIFT	17
861 #define HOST_DMA_ISOC_NBYTES_MASK	(0xfff << 0)
862 #define HOST_DMA_ISOC_NBYTES_SHIFT	0
863 #define HOST_DMA_NBYTES_MASK		(0x1ffff << 0)
864 #define HOST_DMA_NBYTES_SHIFT		0
865 #define HOST_DMA_NBYTES_LIMIT		131071
866 
867 /* Device Mode DMA descriptor status quadlet */
868 
869 #define DEV_DMA_BUFF_STS_MASK		(0x3 << 30)
870 #define DEV_DMA_BUFF_STS_SHIFT		30
871 #define DEV_DMA_BUFF_STS_HREADY		0
872 #define DEV_DMA_BUFF_STS_DMABUSY	1
873 #define DEV_DMA_BUFF_STS_DMADONE	2
874 #define DEV_DMA_BUFF_STS_HBUSY		3
875 #define DEV_DMA_STS_MASK		(0x3 << 28)
876 #define DEV_DMA_STS_SHIFT		28
877 #define DEV_DMA_STS_SUCC		0
878 #define DEV_DMA_STS_BUFF_FLUSH		1
879 #define DEV_DMA_STS_BUFF_ERR		3
880 #define DEV_DMA_L			BIT(27)
881 #define DEV_DMA_SHORT			BIT(26)
882 #define DEV_DMA_IOC			BIT(25)
883 #define DEV_DMA_SR			BIT(24)
884 #define DEV_DMA_MTRF			BIT(23)
885 #define DEV_DMA_ISOC_PID_MASK		(0x3 << 23)
886 #define DEV_DMA_ISOC_PID_SHIFT		23
887 #define DEV_DMA_ISOC_PID_DATA0		0
888 #define DEV_DMA_ISOC_PID_DATA2		1
889 #define DEV_DMA_ISOC_PID_DATA1		2
890 #define DEV_DMA_ISOC_PID_MDATA		3
891 #define DEV_DMA_ISOC_FRNUM_MASK		(0x7ff << 12)
892 #define DEV_DMA_ISOC_FRNUM_SHIFT	12
893 #define DEV_DMA_ISOC_TX_NBYTES_MASK	(0xfff << 0)
894 #define DEV_DMA_ISOC_TX_NBYTES_LIMIT	0xfff
895 #define DEV_DMA_ISOC_RX_NBYTES_MASK	(0x7ff << 0)
896 #define DEV_DMA_ISOC_RX_NBYTES_LIMIT	0x7ff
897 #define DEV_DMA_ISOC_NBYTES_SHIFT	0
898 #define DEV_DMA_NBYTES_MASK		(0xffff << 0)
899 #define DEV_DMA_NBYTES_SHIFT		0
900 #define DEV_DMA_NBYTES_LIMIT		0xffff
901 
902 #define MAX_DMA_DESC_NUM_GENERIC	64
903 #define MAX_DMA_DESC_NUM_HS_ISOC	256
904 
905 #endif /* __DWC2_HW_H__ */
906