1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * PLX NET2272 high/full speed USB device controller
4  *
5  * Copyright (C) 2005-2006 PLX Technology, Inc.
6  * Copyright (C) 2006-2011 Analog Devices, Inc.
7  */
8 
9 #ifndef __NET2272_H__
10 #define __NET2272_H__
11 
12 /* Main Registers */
13 #define REGADDRPTR			0x00
14 #define REGDATA				0x01
15 #define IRQSTAT0			0x02
16 #define 	ENDPOINT_0_INTERRUPT			0
17 #define 	ENDPOINT_A_INTERRUPT			1
18 #define 	ENDPOINT_B_INTERRUPT			2
19 #define 	ENDPOINT_C_INTERRUPT			3
20 #define 	VIRTUALIZED_ENDPOINT_INTERRUPT		4
21 #define 	SETUP_PACKET_INTERRUPT			5
22 #define 	DMA_DONE_INTERRUPT			6
23 #define 	SOF_INTERRUPT				7
24 #define IRQSTAT1			0x03
25 #define 	CONTROL_STATUS_INTERRUPT		1
26 #define 	VBUS_INTERRUPT				2
27 #define 	SUSPEND_REQUEST_INTERRUPT		3
28 #define 	SUSPEND_REQUEST_CHANGE_INTERRUPT	4
29 #define 	RESUME_INTERRUPT			5
30 #define 	ROOT_PORT_RESET_INTERRUPT		6
31 #define 	RESET_STATUS				7
32 #define PAGESEL				0x04
33 #define DMAREQ				0x1c
34 #define 	DMA_ENDPOINT_SELECT			0
35 #define 	DREQ_POLARITY				1
36 #define 	DACK_POLARITY				2
37 #define 	EOT_POLARITY				3
38 #define 	DMA_CONTROL_DACK			4
39 #define 	DMA_REQUEST_ENABLE			5
40 #define 	DMA_REQUEST				6
41 #define 	DMA_BUFFER_VALID			7
42 #define SCRATCH				0x1d
43 #define IRQENB0				0x20
44 #define 	ENDPOINT_0_INTERRUPT_ENABLE		0
45 #define 	ENDPOINT_A_INTERRUPT_ENABLE		1
46 #define 	ENDPOINT_B_INTERRUPT_ENABLE		2
47 #define 	ENDPOINT_C_INTERRUPT_ENABLE		3
48 #define 	VIRTUALIZED_ENDPOINT_INTERRUPT_ENABLE	4
49 #define 	SETUP_PACKET_INTERRUPT_ENABLE		5
50 #define 	DMA_DONE_INTERRUPT_ENABLE		6
51 #define 	SOF_INTERRUPT_ENABLE			7
52 #define IRQENB1				0x21
53 #define 	VBUS_INTERRUPT_ENABLE			2
54 #define 	SUSPEND_REQUEST_INTERRUPT_ENABLE	3
55 #define 	SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE	4
56 #define 	RESUME_INTERRUPT_ENABLE			5
57 #define 	ROOT_PORT_RESET_INTERRUPT_ENABLE	6
58 #define LOCCTL				0x22
59 #define 	DATA_WIDTH				0
60 #define 	LOCAL_CLOCK_OUTPUT			1
61 #define 		LOCAL_CLOCK_OUTPUT_OFF			0
62 #define 		LOCAL_CLOCK_OUTPUT_3_75MHZ		1
63 #define 		LOCAL_CLOCK_OUTPUT_7_5MHZ		2
64 #define 		LOCAL_CLOCK_OUTPUT_15MHZ		3
65 #define 		LOCAL_CLOCK_OUTPUT_30MHZ		4
66 #define 		LOCAL_CLOCK_OUTPUT_60MHZ		5
67 #define 	DMA_SPLIT_BUS_MODE			4
68 #define 	BYTE_SWAP				5
69 #define 	BUFFER_CONFIGURATION			6
70 #define 		BUFFER_CONFIGURATION_EPA512_EPB512	0
71 #define 		BUFFER_CONFIGURATION_EPA1024_EPB512	1
72 #define 		BUFFER_CONFIGURATION_EPA1024_EPB1024	2
73 #define 		BUFFER_CONFIGURATION_EPA1024DB		3
74 #define CHIPREV_LEGACY			0x23
75 #define 		NET2270_LEGACY_REV			0x40
76 #define LOCCTL1				0x24
77 #define 	DMA_MODE				0
78 #define 		SLOW_DREQ				0
79 #define 		FAST_DREQ				1
80 #define 		BURST_MODE				2
81 #define 	DMA_DACK_ENABLE				2
82 #define CHIPREV_2272			0x25
83 #define 		CHIPREV_NET2272_R1			0x10
84 #define 		CHIPREV_NET2272_R1A			0x11
85 /* USB Registers */
86 #define USBCTL0				0x18
87 #define 	IO_WAKEUP_ENABLE			1
88 #define 	USB_DETECT_ENABLE			3
89 #define 	USB_ROOT_PORT_WAKEUP_ENABLE		5
90 #define USBCTL1				0x19
91 #define 	VBUS_PIN				0
92 #define 		USB_FULL_SPEED				1
93 #define 		USB_HIGH_SPEED				2
94 #define 	GENERATE_RESUME				3
95 #define 	VIRTUAL_ENDPOINT_ENABLE			4
96 #define FRAME0				0x1a
97 #define FRAME1				0x1b
98 #define OURADDR				0x30
99 #define 	FORCE_IMMEDIATE				7
100 #define USBDIAG				0x31
101 #define 	FORCE_TRANSMIT_CRC_ERROR		0
102 #define 	PREVENT_TRANSMIT_BIT_STUFF		1
103 #define 	FORCE_RECEIVE_ERROR			2
104 #define 	FAST_TIMES				4
105 #define USBTEST				0x32
106 #define 	TEST_MODE_SELECT			0
107 #define 		NORMAL_OPERATION			0
108 #define XCVRDIAG			0x33
109 #define 	FORCE_FULL_SPEED			2
110 #define 	FORCE_HIGH_SPEED			3
111 #define 	OPMODE					4
112 #define 		NORMAL_OPERATION			0
113 #define 		NON_DRIVING				1
114 #define 		DISABLE_BITSTUFF_AND_NRZI_ENCODE	2
115 #define 	LINESTATE				6
116 #define 		SE0_STATE				0
117 #define 		J_STATE					1
118 #define 		K_STATE					2
119 #define 		SE1_STATE				3
120 #define VIRTOUT0			0x34
121 #define VIRTOUT1			0x35
122 #define VIRTIN0				0x36
123 #define VIRTIN1				0x37
124 #define SETUP0				0x40
125 #define SETUP1				0x41
126 #define SETUP2				0x42
127 #define SETUP3				0x43
128 #define SETUP4				0x44
129 #define SETUP5				0x45
130 #define SETUP6				0x46
131 #define SETUP7				0x47
132 /* Endpoint Registers (Paged via PAGESEL) */
133 #define EP_DATA				0x05
134 #define EP_STAT0			0x06
135 #define 	DATA_IN_TOKEN_INTERRUPT			0
136 #define 	DATA_OUT_TOKEN_INTERRUPT		1
137 #define 	DATA_PACKET_TRANSMITTED_INTERRUPT	2
138 #define 	DATA_PACKET_RECEIVED_INTERRUPT		3
139 #define 	SHORT_PACKET_TRANSFERRED_INTERRUPT	4
140 #define 	NAK_OUT_PACKETS				5
141 #define 	BUFFER_EMPTY				6
142 #define 	BUFFER_FULL				7
143 #define EP_STAT1			0x07
144 #define 	TIMEOUT					0
145 #define 	USB_OUT_ACK_SENT			1
146 #define 	USB_OUT_NAK_SENT			2
147 #define 	USB_IN_ACK_RCVD				3
148 #define 	USB_IN_NAK_SENT				4
149 #define 	USB_STALL_SENT				5
150 #define 	LOCAL_OUT_ZLP				6
151 #define 	BUFFER_FLUSH				7
152 #define EP_TRANSFER0			0x08
153 #define EP_TRANSFER1			0x09
154 #define EP_TRANSFER2			0x0a
155 #define EP_IRQENB			0x0b
156 #define 	DATA_IN_TOKEN_INTERRUPT_ENABLE		0
157 #define 	DATA_OUT_TOKEN_INTERRUPT_ENABLE		1
158 #define 	DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE	2
159 #define 	DATA_PACKET_RECEIVED_INTERRUPT_ENABLE	3
160 #define 	SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE	4
161 #define EP_AVAIL0			0x0c
162 #define EP_AVAIL1			0x0d
163 #define EP_RSPCLR			0x0e
164 #define EP_RSPSET			0x0f
165 #define 	ENDPOINT_HALT				0
166 #define 	ENDPOINT_TOGGLE				1
167 #define 	NAK_OUT_PACKETS_MODE			2
168 #define 	CONTROL_STATUS_PHASE_HANDSHAKE		3
169 #define 	INTERRUPT_MODE				4
170 #define 	AUTOVALIDATE				5
171 #define 	HIDE_STATUS_PHASE			6
172 #define 	ALT_NAK_OUT_PACKETS			7
173 #define EP_MAXPKT0			0x28
174 #define EP_MAXPKT1			0x29
175 #define 	ADDITIONAL_TRANSACTION_OPPORTUNITIES	3
176 #define 		NONE_ADDITIONAL_TRANSACTION		0
177 #define 		ONE_ADDITIONAL_TRANSACTION		1
178 #define 		TWO_ADDITIONAL_TRANSACTION		2
179 #define EP_CFG				0x2a
180 #define 	ENDPOINT_NUMBER				0
181 #define 	ENDPOINT_DIRECTION			4
182 #define 	ENDPOINT_TYPE				5
183 #define 	ENDPOINT_ENABLE				7
184 #define EP_HBW				0x2b
185 #define 	HIGH_BANDWIDTH_OUT_TRANSACTION_PID	0
186 #define 		DATA0_PID				0
187 #define 		DATA1_PID				1
188 #define 		DATA2_PID				2
189 #define 		MDATA_PID				3
190 #define EP_BUFF_STATES			0x2c
191 #define 	BUFFER_A_STATE				0
192 #define 	BUFFER_B_STATE				2
193 #define 		BUFF_FREE				0
194 #define 		BUFF_VALID				1
195 #define 		BUFF_LCL				2
196 #define 		BUFF_USB				3
197 
198 /*---------------------------------------------------------------------------*/
199 
200 #define PCI_DEVICE_ID_RDK1	0x9054
201 
202 /* PCI-RDK EPLD Registers */
203 #define RDK_EPLD_IO_REGISTER1		0x00000000
204 #define 	RDK_EPLD_USB_RESET				0
205 #define 	RDK_EPLD_USB_POWERDOWN				1
206 #define 	RDK_EPLD_USB_WAKEUP				2
207 #define 	RDK_EPLD_USB_EOT				3
208 #define 	RDK_EPLD_DPPULL					4
209 #define RDK_EPLD_IO_REGISTER2		0x00000004
210 #define 	RDK_EPLD_BUSWIDTH				0
211 #define 	RDK_EPLD_USER					2
212 #define 	RDK_EPLD_RESET_INTERRUPT_ENABLE			3
213 #define 	RDK_EPLD_DMA_TIMEOUT_ENABLE			4
214 #define RDK_EPLD_STATUS_REGISTER	0x00000008
215 #define 	RDK_EPLD_USB_LRESET				0
216 #define RDK_EPLD_REVISION_REGISTER	0x0000000c
217 
218 /* PCI-RDK PLX 9054 Registers */
219 #define INTCSR				0x68
220 #define 	PCI_INTERRUPT_ENABLE				8
221 #define 	LOCAL_INTERRUPT_INPUT_ENABLE			11
222 #define 	LOCAL_INPUT_INTERRUPT_ACTIVE			15
223 #define 	LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE		18
224 #define 	LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE		19
225 #define 	DMA_CHANNEL_0_INTERRUPT_ACTIVE			21
226 #define 	DMA_CHANNEL_1_INTERRUPT_ACTIVE			22
227 #define CNTRL				0x6C
228 #define 	RELOAD_CONFIGURATION_REGISTERS			29
229 #define 	PCI_ADAPTER_SOFTWARE_RESET			30
230 #define DMAMODE0			0x80
231 #define 	LOCAL_BUS_WIDTH					0
232 #define 	INTERNAL_WAIT_STATES				2
233 #define 	TA_READY_INPUT_ENABLE				6
234 #define 	LOCAL_BURST_ENABLE				8
235 #define 	SCATTER_GATHER_MODE				9
236 #define 	DONE_INTERRUPT_ENABLE				10
237 #define 	LOCAL_ADDRESSING_MODE				11
238 #define 	DEMAND_MODE					12
239 #define 	DMA_EOT_ENABLE					14
240 #define 	FAST_SLOW_TERMINATE_MODE_SELECT			15
241 #define 	DMA_CHANNEL_INTERRUPT_SELECT			17
242 #define DMAPADR0			0x84
243 #define DMALADR0			0x88
244 #define DMASIZ0				0x8c
245 #define DMADPR0				0x90
246 #define 	DESCRIPTOR_LOCATION				0
247 #define 	END_OF_CHAIN					1
248 #define 	INTERRUPT_AFTER_TERMINAL_COUNT			2
249 #define 	DIRECTION_OF_TRANSFER				3
250 #define DMACSR0				0xa8
251 #define 	CHANNEL_ENABLE					0
252 #define 	CHANNEL_START					1
253 #define 	CHANNEL_ABORT					2
254 #define 	CHANNEL_CLEAR_INTERRUPT				3
255 #define 	CHANNEL_DONE					4
256 #define DMATHR				0xb0
257 #define LBRD1				0xf8
258 #define 	MEMORY_SPACE_LOCAL_BUS_WIDTH			0
259 #define 	W8_BIT						0
260 #define 	W16_BIT						1
261 
262 /* Special OR'ing of INTCSR bits */
263 #define LOCAL_INTERRUPT_TEST \
264 	((1 << LOCAL_INPUT_INTERRUPT_ACTIVE) | \
265 	 (1 << LOCAL_INTERRUPT_INPUT_ENABLE))
266 
267 #define DMA_CHANNEL_0_TEST \
268 	((1 << DMA_CHANNEL_0_INTERRUPT_ACTIVE) | \
269 	 (1 << LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE))
270 
271 #define DMA_CHANNEL_1_TEST \
272 	((1 << DMA_CHANNEL_1_INTERRUPT_ACTIVE) | \
273 	 (1 << LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE))
274 
275 /* EPLD Registers */
276 #define RDK_EPLD_IO_REGISTER1			0x00000000
277 #define 	RDK_EPLD_USB_RESET			0
278 #define 	RDK_EPLD_USB_POWERDOWN			1
279 #define 	RDK_EPLD_USB_WAKEUP			2
280 #define 	RDK_EPLD_USB_EOT			3
281 #define 	RDK_EPLD_DPPULL				4
282 #define RDK_EPLD_IO_REGISTER2			0x00000004
283 #define 	RDK_EPLD_BUSWIDTH			0
284 #define 	RDK_EPLD_USER				2
285 #define 	RDK_EPLD_RESET_INTERRUPT_ENABLE		3
286 #define 	RDK_EPLD_DMA_TIMEOUT_ENABLE		4
287 #define RDK_EPLD_STATUS_REGISTER		0x00000008
288 #define RDK_EPLD_USB_LRESET				0
289 #define RDK_EPLD_REVISION_REGISTER		0x0000000c
290 
291 #define EPLD_IO_CONTROL_REGISTER		0x400
292 #define 	NET2272_RESET				0
293 #define 	BUSWIDTH				1
294 #define 	MPX_MODE				3
295 #define 	USER					4
296 #define 	DMA_TIMEOUT_ENABLE			5
297 #define 	DMA_CTL_DACK				6
298 #define 	EPLD_DMA_ENABLE				7
299 #define EPLD_DMA_CONTROL_REGISTER		0x800
300 #define 	SPLIT_DMA_MODE				0
301 #define 	SPLIT_DMA_DIRECTION			1
302 #define 	SPLIT_DMA_ENABLE			2
303 #define 	SPLIT_DMA_INTERRUPT_ENABLE		3
304 #define 	SPLIT_DMA_INTERRUPT			4
305 #define 	EPLD_DMA_MODE				5
306 #define 	EPLD_DMA_CONTROLLER_ENABLE		7
307 #define SPLIT_DMA_ADDRESS_LOW			0xc00
308 #define SPLIT_DMA_ADDRESS_HIGH			0x1000
309 #define SPLIT_DMA_BYTE_COUNT_LOW		0x1400
310 #define SPLIT_DMA_BYTE_COUNT_HIGH		0x1800
311 #define EPLD_REVISION_REGISTER			0x1c00
312 #define SPLIT_DMA_RAM				0x4000
313 #define DMA_RAM_SIZE				0x1000
314 
315 /*---------------------------------------------------------------------------*/
316 
317 #define PCI_DEVICE_ID_RDK2	0x3272
318 
319 /* PCI-RDK version 2 registers */
320 
321 /* Main Control Registers */
322 
323 #define RDK2_IRQENB			0x00
324 #define RDK2_IRQSTAT			0x04
325 #define 	PB7				23
326 #define 	PB6				22
327 #define 	PB5				21
328 #define 	PB4				20
329 #define 	PB3				19
330 #define 	PB2				18
331 #define 	PB1				17
332 #define 	PB0				16
333 #define 	GP3				23
334 #define 	GP2				23
335 #define 	GP1				23
336 #define 	GP0				23
337 #define 	DMA_RETRY_ABORT			6
338 #define 	DMA_PAUSE_DONE			5
339 #define 	DMA_ABORT_DONE			4
340 #define 	DMA_OUT_FIFO_TRANSFER_DONE	3
341 #define 	DMA_LOCAL_DONE			2
342 #define 	DMA_PCI_DONE			1
343 #define 	NET2272_PCI_IRQ			0
344 
345 #define RDK2_LOCCTLRDK			0x08
346 #define 	CHIP_RESET			3
347 #define 	SPLIT_DMA			2
348 #define 	MULTIPLEX_MODE			1
349 #define 	BUS_WIDTH			0
350 
351 #define RDK2_GPIOCTL			0x10
352 #define 	GP3_OUT_ENABLE					7
353 #define 	GP2_OUT_ENABLE					6
354 #define 	GP1_OUT_ENABLE					5
355 #define 	GP0_OUT_ENABLE					4
356 #define 	GP3_DATA					3
357 #define 	GP2_DATA					2
358 #define 	GP1_DATA					1
359 #define 	GP0_DATA					0
360 
361 #define RDK2_LEDSW			0x14
362 #define 	LED3				27
363 #define 	LED2				26
364 #define 	LED1				25
365 #define 	LED0				24
366 #define 	PBUTTON				16
367 #define 	DIPSW				0
368 
369 #define RDK2_DIAG			0x18
370 #define 	RDK2_FAST_TIMES				2
371 #define 	FORCE_PCI_SERR				1
372 #define 	FORCE_PCI_INT				0
373 #define RDK2_FPGAREV			0x1C
374 
375 /* Dma Control registers */
376 #define RDK2_DMACTL			0x80
377 #define 	ADDR_HOLD				24
378 #define 	RETRY_COUNT				16	/* 23:16 */
379 #define 	FIFO_THRESHOLD				11	/* 15:11 */
380 #define 	MEM_WRITE_INVALIDATE			10
381 #define 	READ_MULTIPLE				9
382 #define 	READ_LINE				8
383 #define 	RDK2_DMA_MODE				6	/* 7:6 */
384 #define 	CONTROL_DACK				5
385 #define 	EOT_ENABLE				4
386 #define 	EOT_POLARITY				3
387 #define 	DACK_POLARITY				2
388 #define 	DREQ_POLARITY				1
389 #define 	DMA_ENABLE				0
390 
391 #define RDK2_DMASTAT			0x84
392 #define 	GATHER_COUNT				12	/* 14:12 */
393 #define 	FIFO_COUNT				6	/* 11:6 */
394 #define 	FIFO_FLUSH				5
395 #define 	FIFO_TRANSFER				4
396 #define 	PAUSE_DONE				3
397 #define 	ABORT_DONE				2
398 #define 	DMA_ABORT				1
399 #define 	DMA_START				0
400 
401 #define RDK2_DMAPCICOUNT		0x88
402 #define 	DMA_DIRECTION				31
403 #define 	DMA_PCI_BYTE_COUNT			0	/* 0:23 */
404 
405 #define RDK2_DMALOCCOUNT		0x8C	/* 0:23 dma local byte count */
406 
407 #define RDK2_DMAADDR			0x90	/* 2:31 PCI bus starting address */
408 
409 /*---------------------------------------------------------------------------*/
410 
411 #define REG_INDEXED_THRESHOLD	(1 << 5)
412 
413 /* DRIVER DATA STRUCTURES and UTILITIES */
414 struct net2272_ep {
415 	struct usb_ep ep;
416 	struct net2272 *dev;
417 	unsigned long irqs;
418 
419 	/* analogous to a host-side qh */
420 	struct list_head queue;
421 	const struct usb_endpoint_descriptor *desc;
422 	unsigned num:8,
423 	         fifo_size:12,
424 	         stopped:1,
425 	         wedged:1,
426 	         is_in:1,
427 	         is_iso:1,
428 	         dma:1,
429 	         not_empty:1;
430 };
431 
432 struct net2272 {
433 	/* each device provides one gadget, several endpoints */
434 	struct usb_gadget gadget;
435 	struct device *dev;
436 	unsigned short dev_id;
437 
438 	spinlock_t lock;
439 	struct net2272_ep ep[4];
440 	struct usb_gadget_driver *driver;
441 	unsigned protocol_stall:1,
442 	         softconnect:1,
443 	         wakeup:1,
444 		 added:1,
445 		 async_callbacks:1,
446 	         dma_eot_polarity:1,
447 	         dma_dack_polarity:1,
448 	         dma_dreq_polarity:1,
449 	         dma_busy:1;
450 	u16 chiprev;
451 	u8 pagesel;
452 
453 	unsigned int irq;
454 	unsigned short fifo_mode;
455 
456 	unsigned int base_shift;
457 	u16 __iomem *base_addr;
458 	union {
459 #ifdef CONFIG_USB_PCI
460 		struct {
461 			void __iomem *plx9054_base_addr;
462 			void __iomem *epld_base_addr;
463 		} rdk1;
464 		struct {
465 			/* Bar0, Bar1 is base_addr both mem-mapped */
466 			void __iomem *fpga_base_addr;
467 		} rdk2;
468 #endif
469 	};
470 };
471 
472 static void __iomem *
net2272_reg_addr(struct net2272 * dev,unsigned int reg)473 net2272_reg_addr(struct net2272 *dev, unsigned int reg)
474 {
475 	return dev->base_addr + (reg << dev->base_shift);
476 }
477 
478 static void
net2272_write(struct net2272 * dev,unsigned int reg,u8 value)479 net2272_write(struct net2272 *dev, unsigned int reg, u8 value)
480 {
481 	if (reg >= REG_INDEXED_THRESHOLD) {
482 		/*
483 		 * Indexed register; use REGADDRPTR/REGDATA
484 		 *  - Save and restore REGADDRPTR. This prevents REGADDRPTR from
485 		 *    changes between other code sections, but it is time consuming.
486 		 *  - Performance tips: either do not save and restore REGADDRPTR (if it
487 		 *    is safe) or do save/restore operations only in critical sections.
488 		u8 tmp = readb(dev->base_addr + REGADDRPTR);
489 		 */
490 		writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR));
491 		writeb(value, net2272_reg_addr(dev, REGDATA));
492 		/* writeb(tmp, net2272_reg_addr(dev, REGADDRPTR)); */
493 	} else
494 		writeb(value, net2272_reg_addr(dev, reg));
495 }
496 
497 static u8
net2272_read(struct net2272 * dev,unsigned int reg)498 net2272_read(struct net2272 *dev, unsigned int reg)
499 {
500 	u8 ret;
501 
502 	if (reg >= REG_INDEXED_THRESHOLD) {
503 		/*
504 		 * Indexed register; use REGADDRPTR/REGDATA
505 		 *  - Save and restore REGADDRPTR. This prevents REGADDRPTR from
506 		 *    changes between other code sections, but it is time consuming.
507 		 *  - Performance tips: either do not save and restore REGADDRPTR (if it
508 		 *    is safe) or do save/restore operations only in critical sections.
509 		u8 tmp = readb(dev->base_addr + REGADDRPTR);
510 		 */
511 		writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR));
512 		ret = readb(net2272_reg_addr(dev, REGDATA));
513 		/* writeb(tmp, net2272_reg_addr(dev, REGADDRPTR)); */
514 	} else
515 		ret = readb(net2272_reg_addr(dev, reg));
516 
517 	return ret;
518 }
519 
520 static void
net2272_ep_write(struct net2272_ep * ep,unsigned int reg,u8 value)521 net2272_ep_write(struct net2272_ep *ep, unsigned int reg, u8 value)
522 {
523 	struct net2272 *dev = ep->dev;
524 
525 	if (dev->pagesel != ep->num) {
526 		net2272_write(dev, PAGESEL, ep->num);
527 		dev->pagesel = ep->num;
528 	}
529 	net2272_write(dev, reg, value);
530 }
531 
532 static u8
net2272_ep_read(struct net2272_ep * ep,unsigned int reg)533 net2272_ep_read(struct net2272_ep *ep, unsigned int reg)
534 {
535 	struct net2272 *dev = ep->dev;
536 
537 	if (dev->pagesel != ep->num) {
538 		net2272_write(dev, PAGESEL, ep->num);
539 		dev->pagesel = ep->num;
540 	}
541 	return net2272_read(dev, reg);
542 }
543 
allow_status(struct net2272_ep * ep)544 static void allow_status(struct net2272_ep *ep)
545 {
546 	/* ep0 only */
547 	net2272_ep_write(ep, EP_RSPCLR,
548 		(1 << CONTROL_STATUS_PHASE_HANDSHAKE) |
549 		(1 << ALT_NAK_OUT_PACKETS) |
550 		(1 << NAK_OUT_PACKETS_MODE));
551 	ep->stopped = 1;
552 }
553 
set_halt(struct net2272_ep * ep)554 static void set_halt(struct net2272_ep *ep)
555 {
556 	/* ep0 and bulk/intr endpoints */
557 	net2272_ep_write(ep, EP_RSPCLR, 1 << CONTROL_STATUS_PHASE_HANDSHAKE);
558 	net2272_ep_write(ep, EP_RSPSET, 1 << ENDPOINT_HALT);
559 }
560 
clear_halt(struct net2272_ep * ep)561 static void clear_halt(struct net2272_ep *ep)
562 {
563 	/* ep0 and bulk/intr endpoints */
564 	net2272_ep_write(ep, EP_RSPCLR,
565 		(1 << ENDPOINT_HALT) | (1 << ENDPOINT_TOGGLE));
566 }
567 
568 /* count (<= 4) bytes in the next fifo write will be valid */
set_fifo_bytecount(struct net2272_ep * ep,unsigned count)569 static void set_fifo_bytecount(struct net2272_ep *ep, unsigned count)
570 {
571 	/* net2272_ep_write will truncate to u8 for us */
572 	net2272_ep_write(ep, EP_TRANSFER2, count >> 16);
573 	net2272_ep_write(ep, EP_TRANSFER1, count >> 8);
574 	net2272_ep_write(ep, EP_TRANSFER0, count);
575 }
576 
577 struct net2272_request {
578 	struct usb_request req;
579 	struct list_head queue;
580 	unsigned mapped:1,
581 	         valid:1;
582 };
583 
584 #endif
585