1 /* 2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. 3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 4 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public 7 * License as published by the Free Software Foundation; 8 * either version 2, or (at your option) any later version. 9 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even 12 * the implied warranty of MERCHANTABILITY or FITNESS FOR 13 * A PARTICULAR PURPOSE.See the GNU General Public License 14 * for more details. 15 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22 #ifndef __HW_H__ 23 #define __HW_H__ 24 25 #include <linux/seq_file.h> 26 27 #include "viamode.h" 28 #include "global.h" 29 #include "via_modesetting.h" 30 31 #define viafb_read_reg(p, i) via_read_reg(p, i) 32 #define viafb_write_reg(i, p, d) via_write_reg(p, i, d) 33 #define viafb_write_reg_mask(i, p, d, m) via_write_reg_mask(p, i, d, m) 34 35 /* VIA output devices */ 36 #define VIA_LDVP0 0x00000001 37 #define VIA_LDVP1 0x00000002 38 #define VIA_DVP0 0x00000004 39 #define VIA_CRT 0x00000010 40 #define VIA_DVP1 0x00000020 41 #define VIA_LVDS1 0x00000040 42 #define VIA_LVDS2 0x00000080 43 44 /* VIA output device power states */ 45 #define VIA_STATE_ON 0 46 #define VIA_STATE_STANDBY 1 47 #define VIA_STATE_SUSPEND 2 48 #define VIA_STATE_OFF 3 49 50 /* VIA output device sync polarity */ 51 #define VIA_HSYNC_NEGATIVE 0x01 52 #define VIA_VSYNC_NEGATIVE 0x02 53 54 /*************************************************** 55 * Definition IGA1 Design Method of CRTC Registers * 56 ****************************************************/ 57 #define IGA1_HOR_TOTAL_FORMULA(x) (((x)/8)-5) 58 #define IGA1_HOR_ADDR_FORMULA(x) (((x)/8)-1) 59 #define IGA1_HOR_BLANK_START_FORMULA(x) (((x)/8)-1) 60 #define IGA1_HOR_BLANK_END_FORMULA(x, y) (((x+y)/8)-1) 61 #define IGA1_HOR_SYNC_START_FORMULA(x) ((x)/8) 62 #define IGA1_HOR_SYNC_END_FORMULA(x, y) ((x+y)/8) 63 64 #define IGA1_VER_TOTAL_FORMULA(x) ((x)-2) 65 #define IGA1_VER_ADDR_FORMULA(x) ((x)-1) 66 #define IGA1_VER_BLANK_START_FORMULA(x) ((x)-1) 67 #define IGA1_VER_BLANK_END_FORMULA(x, y) ((x+y)-1) 68 #define IGA1_VER_SYNC_START_FORMULA(x) ((x)-1) 69 #define IGA1_VER_SYNC_END_FORMULA(x, y) ((x+y)-1) 70 71 /*************************************************** 72 ** Definition IGA2 Design Method of CRTC Registers * 73 ****************************************************/ 74 #define IGA2_HOR_TOTAL_FORMULA(x) ((x)-1) 75 #define IGA2_HOR_ADDR_FORMULA(x) ((x)-1) 76 #define IGA2_HOR_BLANK_START_FORMULA(x) ((x)-1) 77 #define IGA2_HOR_BLANK_END_FORMULA(x, y) ((x+y)-1) 78 #define IGA2_HOR_SYNC_START_FORMULA(x) ((x)-1) 79 #define IGA2_HOR_SYNC_END_FORMULA(x, y) ((x+y)-1) 80 81 #define IGA2_VER_TOTAL_FORMULA(x) ((x)-1) 82 #define IGA2_VER_ADDR_FORMULA(x) ((x)-1) 83 #define IGA2_VER_BLANK_START_FORMULA(x) ((x)-1) 84 #define IGA2_VER_BLANK_END_FORMULA(x, y) ((x+y)-1) 85 #define IGA2_VER_SYNC_START_FORMULA(x) ((x)-1) 86 #define IGA2_VER_SYNC_END_FORMULA(x, y) ((x+y)-1) 87 88 /**********************************************************/ 89 /* Definition IGA2 Design Method of CRTC Shadow Registers */ 90 /**********************************************************/ 91 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) ((x/8)-5) 92 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y) (((x+y)/8)-1) 93 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x) ((x)-2) 94 #define IGA2_VER_ADDR_SHADOW_FORMULA(x) ((x)-1) 95 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) ((x)-1) 96 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y) ((x+y)-1) 97 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x) 98 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) (x+y) 99 100 /* Define Register Number for IGA1 CRTC Timing */ 101 102 /* location: {CR00,0,7},{CR36,3,3} */ 103 #define IGA1_HOR_TOTAL_REG_NUM 2 104 /* location: {CR01,0,7} */ 105 #define IGA1_HOR_ADDR_REG_NUM 1 106 /* location: {CR02,0,7} */ 107 #define IGA1_HOR_BLANK_START_REG_NUM 1 108 /* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */ 109 #define IGA1_HOR_BLANK_END_REG_NUM 3 110 /* location: {CR04,0,7},{CR33,4,4} */ 111 #define IGA1_HOR_SYNC_START_REG_NUM 2 112 /* location: {CR05,0,4} */ 113 #define IGA1_HOR_SYNC_END_REG_NUM 1 114 /* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */ 115 #define IGA1_VER_TOTAL_REG_NUM 4 116 /* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */ 117 #define IGA1_VER_ADDR_REG_NUM 4 118 /* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */ 119 #define IGA1_VER_BLANK_START_REG_NUM 4 120 /* location: {CR16,0,7} */ 121 #define IGA1_VER_BLANK_END_REG_NUM 1 122 /* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */ 123 #define IGA1_VER_SYNC_START_REG_NUM 4 124 /* location: {CR11,0,3} */ 125 #define IGA1_VER_SYNC_END_REG_NUM 1 126 127 /* Define Register Number for IGA2 Shadow CRTC Timing */ 128 129 /* location: {CR6D,0,7},{CR71,3,3} */ 130 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM 2 131 /* location: {CR6E,0,7} */ 132 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM 1 133 /* location: {CR6F,0,7},{CR71,0,2} */ 134 #define IGA2_SHADOW_VER_TOTAL_REG_NUM 2 135 /* location: {CR70,0,7},{CR71,4,6} */ 136 #define IGA2_SHADOW_VER_ADDR_REG_NUM 2 137 /* location: {CR72,0,7},{CR74,4,6} */ 138 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2 139 /* location: {CR73,0,7},{CR74,0,2} */ 140 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM 2 141 /* location: {CR75,0,7},{CR76,4,6} */ 142 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM 2 143 /* location: {CR76,0,3} */ 144 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1 145 146 /* Define Register Number for IGA2 CRTC Timing */ 147 148 /* location: {CR50,0,7},{CR55,0,3} */ 149 #define IGA2_HOR_TOTAL_REG_NUM 2 150 /* location: {CR51,0,7},{CR55,4,6} */ 151 #define IGA2_HOR_ADDR_REG_NUM 2 152 /* location: {CR52,0,7},{CR54,0,2} */ 153 #define IGA2_HOR_BLANK_START_REG_NUM 2 154 /* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6] 155 is reserved, so it may have problem to set 1600x1200 on IGA2. */ 156 /* Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */ 157 #define IGA2_HOR_BLANK_END_REG_NUM 3 158 /* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */ 159 /* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */ 160 #define IGA2_HOR_SYNC_START_REG_NUM 4 161 162 /* location: {CR57,0,7},{CR5C,6,6} */ 163 #define IGA2_HOR_SYNC_END_REG_NUM 2 164 /* location: {CR58,0,7},{CR5D,0,2} */ 165 #define IGA2_VER_TOTAL_REG_NUM 2 166 /* location: {CR59,0,7},{CR5D,3,5} */ 167 #define IGA2_VER_ADDR_REG_NUM 2 168 /* location: {CR5A,0,7},{CR5C,0,2} */ 169 #define IGA2_VER_BLANK_START_REG_NUM 2 170 /* location: {CR5E,0,7},{CR5C,3,5} */ 171 #define IGA2_VER_BLANK_END_REG_NUM 2 172 /* location: {CR5E,0,7},{CR5F,5,7} */ 173 #define IGA2_VER_SYNC_START_REG_NUM 2 174 /* location: {CR5F,0,4} */ 175 #define IGA2_VER_SYNC_END_REG_NUM 1 176 177 /* Define Fetch Count Register*/ 178 179 /* location: {SR1C,0,7},{SR1D,0,1} */ 180 #define IGA1_FETCH_COUNT_REG_NUM 2 181 /* 16 bytes alignment. */ 182 #define IGA1_FETCH_COUNT_ALIGN_BYTE 16 183 /* x: H resolution, y: color depth */ 184 #define IGA1_FETCH_COUNT_PATCH_VALUE 4 185 #define IGA1_FETCH_COUNT_FORMULA(x, y) \ 186 (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE) 187 188 /* location: {CR65,0,7},{CR67,2,3} */ 189 #define IGA2_FETCH_COUNT_REG_NUM 2 190 #define IGA2_FETCH_COUNT_ALIGN_BYTE 16 191 #define IGA2_FETCH_COUNT_PATCH_VALUE 0 192 #define IGA2_FETCH_COUNT_FORMULA(x, y) \ 193 (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE) 194 195 /* Staring Address*/ 196 197 /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */ 198 #define IGA1_STARTING_ADDR_REG_NUM 4 199 /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */ 200 #define IGA2_STARTING_ADDR_REG_NUM 3 201 202 /* Define Display OFFSET*/ 203 /* These value are by HW suggested value*/ 204 /* location: {SR17,0,7} */ 205 #define K800_IGA1_FIFO_MAX_DEPTH 384 206 /* location: {SR16,0,5},{SR16,7,7} */ 207 #define K800_IGA1_FIFO_THRESHOLD 328 208 /* location: {SR18,0,5},{SR18,7,7} */ 209 #define K800_IGA1_FIFO_HIGH_THRESHOLD 296 210 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */ 211 /* because HW only 5 bits */ 212 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 213 214 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ 215 #define K800_IGA2_FIFO_MAX_DEPTH 384 216 /* location: {CR68,0,3},{CR95,4,6} */ 217 #define K800_IGA2_FIFO_THRESHOLD 328 218 /* location: {CR92,0,3},{CR95,0,2} */ 219 #define K800_IGA2_FIFO_HIGH_THRESHOLD 296 220 /* location: {CR94,0,6} */ 221 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 222 223 /* location: {SR17,0,7} */ 224 #define P880_IGA1_FIFO_MAX_DEPTH 192 225 /* location: {SR16,0,5},{SR16,7,7} */ 226 #define P880_IGA1_FIFO_THRESHOLD 128 227 /* location: {SR18,0,5},{SR18,7,7} */ 228 #define P880_IGA1_FIFO_HIGH_THRESHOLD 64 229 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */ 230 /* because HW only 5 bits */ 231 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 232 233 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ 234 #define P880_IGA2_FIFO_MAX_DEPTH 96 235 /* location: {CR68,0,3},{CR95,4,6} */ 236 #define P880_IGA2_FIFO_THRESHOLD 64 237 /* location: {CR92,0,3},{CR95,0,2} */ 238 #define P880_IGA2_FIFO_HIGH_THRESHOLD 32 239 /* location: {CR94,0,6} */ 240 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 241 242 /* VT3314 chipset*/ 243 244 /* location: {SR17,0,7} */ 245 #define CN700_IGA1_FIFO_MAX_DEPTH 96 246 /* location: {SR16,0,5},{SR16,7,7} */ 247 #define CN700_IGA1_FIFO_THRESHOLD 80 248 /* location: {SR18,0,5},{SR18,7,7} */ 249 #define CN700_IGA1_FIFO_HIGH_THRESHOLD 64 250 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero, 251 because HW only 5 bits */ 252 #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 253 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ 254 #define CN700_IGA2_FIFO_MAX_DEPTH 96 255 /* location: {CR68,0,3},{CR95,4,6} */ 256 #define CN700_IGA2_FIFO_THRESHOLD 80 257 /* location: {CR92,0,3},{CR95,0,2} */ 258 #define CN700_IGA2_FIFO_HIGH_THRESHOLD 32 259 /* location: {CR94,0,6} */ 260 #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 261 262 /* For VT3324, these values are suggested by HW */ 263 /* location: {SR17,0,7} */ 264 #define CX700_IGA1_FIFO_MAX_DEPTH 192 265 /* location: {SR16,0,5},{SR16,7,7} */ 266 #define CX700_IGA1_FIFO_THRESHOLD 128 267 /* location: {SR18,0,5},{SR18,7,7} */ 268 #define CX700_IGA1_FIFO_HIGH_THRESHOLD 128 269 /* location: {SR22,0,4} */ 270 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124 271 272 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ 273 #define CX700_IGA2_FIFO_MAX_DEPTH 96 274 /* location: {CR68,0,3},{CR95,4,6} */ 275 #define CX700_IGA2_FIFO_THRESHOLD 64 276 /* location: {CR92,0,3},{CR95,0,2} */ 277 #define CX700_IGA2_FIFO_HIGH_THRESHOLD 32 278 /* location: {CR94,0,6} */ 279 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 280 281 /* VT3336 chipset*/ 282 /* location: {SR17,0,7} */ 283 #define K8M890_IGA1_FIFO_MAX_DEPTH 360 284 /* location: {SR16,0,5},{SR16,7,7} */ 285 #define K8M890_IGA1_FIFO_THRESHOLD 328 286 /* location: {SR18,0,5},{SR18,7,7} */ 287 #define K8M890_IGA1_FIFO_HIGH_THRESHOLD 296 288 /* location: {SR22,0,4}. */ 289 #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124 290 291 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ 292 #define K8M890_IGA2_FIFO_MAX_DEPTH 360 293 /* location: {CR68,0,3},{CR95,4,6} */ 294 #define K8M890_IGA2_FIFO_THRESHOLD 328 295 /* location: {CR92,0,3},{CR95,0,2} */ 296 #define K8M890_IGA2_FIFO_HIGH_THRESHOLD 296 297 /* location: {CR94,0,6} */ 298 #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 124 299 300 /* VT3327 chipset*/ 301 /* location: {SR17,0,7} */ 302 #define P4M890_IGA1_FIFO_MAX_DEPTH 96 303 /* location: {SR16,0,5},{SR16,7,7} */ 304 #define P4M890_IGA1_FIFO_THRESHOLD 76 305 /* location: {SR18,0,5},{SR18,7,7} */ 306 #define P4M890_IGA1_FIFO_HIGH_THRESHOLD 64 307 /* location: {SR22,0,4}. (32/4) =8 */ 308 #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32 309 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ 310 #define P4M890_IGA2_FIFO_MAX_DEPTH 96 311 /* location: {CR68,0,3},{CR95,4,6} */ 312 #define P4M890_IGA2_FIFO_THRESHOLD 76 313 /* location: {CR92,0,3},{CR95,0,2} */ 314 #define P4M890_IGA2_FIFO_HIGH_THRESHOLD 64 315 /* location: {CR94,0,6} */ 316 #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32 317 318 /* VT3364 chipset*/ 319 /* location: {SR17,0,7} */ 320 #define P4M900_IGA1_FIFO_MAX_DEPTH 96 321 /* location: {SR16,0,5},{SR16,7,7} */ 322 #define P4M900_IGA1_FIFO_THRESHOLD 76 323 /* location: {SR18,0,5},{SR18,7,7} */ 324 #define P4M900_IGA1_FIFO_HIGH_THRESHOLD 76 325 /* location: {SR22,0,4}. */ 326 #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32 327 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ 328 #define P4M900_IGA2_FIFO_MAX_DEPTH 96 329 /* location: {CR68,0,3},{CR95,4,6} */ 330 #define P4M900_IGA2_FIFO_THRESHOLD 76 331 /* location: {CR92,0,3},{CR95,0,2} */ 332 #define P4M900_IGA2_FIFO_HIGH_THRESHOLD 76 333 /* location: {CR94,0,6} */ 334 #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32 335 336 /* For VT3353, these values are suggested by HW */ 337 /* location: {SR17,0,7} */ 338 #define VX800_IGA1_FIFO_MAX_DEPTH 192 339 /* location: {SR16,0,5},{SR16,7,7} */ 340 #define VX800_IGA1_FIFO_THRESHOLD 152 341 /* location: {SR18,0,5},{SR18,7,7} */ 342 #define VX800_IGA1_FIFO_HIGH_THRESHOLD 152 343 /* location: {SR22,0,4} */ 344 #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 64 345 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ 346 #define VX800_IGA2_FIFO_MAX_DEPTH 96 347 /* location: {CR68,0,3},{CR95,4,6} */ 348 #define VX800_IGA2_FIFO_THRESHOLD 64 349 /* location: {CR92,0,3},{CR95,0,2} */ 350 #define VX800_IGA2_FIFO_HIGH_THRESHOLD 32 351 /* location: {CR94,0,6} */ 352 #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 353 354 /* For VT3409 */ 355 #define VX855_IGA1_FIFO_MAX_DEPTH 400 356 #define VX855_IGA1_FIFO_THRESHOLD 320 357 #define VX855_IGA1_FIFO_HIGH_THRESHOLD 320 358 #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160 359 360 #define VX855_IGA2_FIFO_MAX_DEPTH 200 361 #define VX855_IGA2_FIFO_THRESHOLD 160 362 #define VX855_IGA2_FIFO_HIGH_THRESHOLD 160 363 #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320 364 365 /* For VT3410 */ 366 #define VX900_IGA1_FIFO_MAX_DEPTH 400 367 #define VX900_IGA1_FIFO_THRESHOLD 320 368 #define VX900_IGA1_FIFO_HIGH_THRESHOLD 320 369 #define VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160 370 371 #define VX900_IGA2_FIFO_MAX_DEPTH 192 372 #define VX900_IGA2_FIFO_THRESHOLD 160 373 #define VX900_IGA2_FIFO_HIGH_THRESHOLD 160 374 #define VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320 375 376 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1 377 #define IGA1_FIFO_THRESHOLD_REG_NUM 2 378 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2 379 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1 380 381 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM 3 382 #define IGA2_FIFO_THRESHOLD_REG_NUM 2 383 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM 2 384 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1 385 386 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) ((x/2)-1) 387 #define IGA1_FIFO_THRESHOLD_FORMULA(x) (x/4) 388 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4) 389 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4) 390 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) (((x/2)/4)-1) 391 #define IGA2_FIFO_THRESHOLD_FORMULA(x) (x/4) 392 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4) 393 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4) 394 395 /************************************************************************/ 396 /* LCD Timing */ 397 /************************************************************************/ 398 399 /* 500 ms = 500000 us */ 400 #define LCD_POWER_SEQ_TD0 500000 401 /* 50 ms = 50000 us */ 402 #define LCD_POWER_SEQ_TD1 50000 403 /* 0 us */ 404 #define LCD_POWER_SEQ_TD2 0 405 /* 210 ms = 210000 us */ 406 #define LCD_POWER_SEQ_TD3 210000 407 /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */ 408 #define CLE266_POWER_SEQ_UNIT 71 409 /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */ 410 #define K800_POWER_SEQ_UNIT 142 411 /* 2^13 * (1/14.31818M) = 572.1 us */ 412 #define P880_POWER_SEQ_UNIT 572 413 414 #define CLE266_POWER_SEQ_FORMULA(x) ((x)/CLE266_POWER_SEQ_UNIT) 415 #define K800_POWER_SEQ_FORMULA(x) ((x)/K800_POWER_SEQ_UNIT) 416 #define P880_POWER_SEQ_FORMULA(x) ((x)/P880_POWER_SEQ_UNIT) 417 418 /* location: {CR8B,0,7},{CR8F,0,3} */ 419 #define LCD_POWER_SEQ_TD0_REG_NUM 2 420 /* location: {CR8C,0,7},{CR8F,4,7} */ 421 #define LCD_POWER_SEQ_TD1_REG_NUM 2 422 /* location: {CR8D,0,7},{CR90,0,3} */ 423 #define LCD_POWER_SEQ_TD2_REG_NUM 2 424 /* location: {CR8E,0,7},{CR90,4,7} */ 425 #define LCD_POWER_SEQ_TD3_REG_NUM 2 426 427 /* LCD Scaling factor*/ 428 /* x: indicate setting horizontal size*/ 429 /* y: indicate panel horizontal size*/ 430 431 /* Horizontal scaling factor 10 bits (2^10) */ 432 #define CLE266_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1)) 433 /* Vertical scaling factor 10 bits (2^10) */ 434 #define CLE266_LCD_VER_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1)) 435 /* Horizontal scaling factor 10 bits (2^12) */ 436 #define K800_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*4096)/(y-1)) 437 /* Vertical scaling factor 10 bits (2^11) */ 438 #define K800_LCD_VER_SCF_FORMULA(x, y) (((x-1)*2048)/(y-1)) 439 440 /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */ 441 #define LCD_HOR_SCALING_FACTOR_REG_NUM 3 442 /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */ 443 #define LCD_VER_SCALING_FACTOR_REG_NUM 3 444 /* location: {CR77,0,7},{CR79,4,5} */ 445 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE 2 446 /* location: {CR78,0,7},{CR79,6,7} */ 447 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2 448 449 /************************************************ 450 ***** Define IGA1 Display Timing ***** 451 ************************************************/ 452 struct io_register { 453 u8 io_addr; 454 u8 start_bit; 455 u8 end_bit; 456 }; 457 458 /* IGA1 Horizontal Total */ 459 struct iga1_hor_total { 460 int reg_num; 461 struct io_register reg[IGA1_HOR_TOTAL_REG_NUM]; 462 }; 463 464 /* IGA1 Horizontal Addressable Video */ 465 struct iga1_hor_addr { 466 int reg_num; 467 struct io_register reg[IGA1_HOR_ADDR_REG_NUM]; 468 }; 469 470 /* IGA1 Horizontal Blank Start */ 471 struct iga1_hor_blank_start { 472 int reg_num; 473 struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM]; 474 }; 475 476 /* IGA1 Horizontal Blank End */ 477 struct iga1_hor_blank_end { 478 int reg_num; 479 struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM]; 480 }; 481 482 /* IGA1 Horizontal Sync Start */ 483 struct iga1_hor_sync_start { 484 int reg_num; 485 struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM]; 486 }; 487 488 /* IGA1 Horizontal Sync End */ 489 struct iga1_hor_sync_end { 490 int reg_num; 491 struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM]; 492 }; 493 494 /* IGA1 Vertical Total */ 495 struct iga1_ver_total { 496 int reg_num; 497 struct io_register reg[IGA1_VER_TOTAL_REG_NUM]; 498 }; 499 500 /* IGA1 Vertical Addressable Video */ 501 struct iga1_ver_addr { 502 int reg_num; 503 struct io_register reg[IGA1_VER_ADDR_REG_NUM]; 504 }; 505 506 /* IGA1 Vertical Blank Start */ 507 struct iga1_ver_blank_start { 508 int reg_num; 509 struct io_register reg[IGA1_VER_BLANK_START_REG_NUM]; 510 }; 511 512 /* IGA1 Vertical Blank End */ 513 struct iga1_ver_blank_end { 514 int reg_num; 515 struct io_register reg[IGA1_VER_BLANK_END_REG_NUM]; 516 }; 517 518 /* IGA1 Vertical Sync Start */ 519 struct iga1_ver_sync_start { 520 int reg_num; 521 struct io_register reg[IGA1_VER_SYNC_START_REG_NUM]; 522 }; 523 524 /* IGA1 Vertical Sync End */ 525 struct iga1_ver_sync_end { 526 int reg_num; 527 struct io_register reg[IGA1_VER_SYNC_END_REG_NUM]; 528 }; 529 530 /***************************************************** 531 ** Define IGA2 Shadow Display Timing **** 532 *****************************************************/ 533 534 /* IGA2 Shadow Horizontal Total */ 535 struct iga2_shadow_hor_total { 536 int reg_num; 537 struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM]; 538 }; 539 540 /* IGA2 Shadow Horizontal Blank End */ 541 struct iga2_shadow_hor_blank_end { 542 int reg_num; 543 struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM]; 544 }; 545 546 /* IGA2 Shadow Vertical Total */ 547 struct iga2_shadow_ver_total { 548 int reg_num; 549 struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM]; 550 }; 551 552 /* IGA2 Shadow Vertical Addressable Video */ 553 struct iga2_shadow_ver_addr { 554 int reg_num; 555 struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM]; 556 }; 557 558 /* IGA2 Shadow Vertical Blank Start */ 559 struct iga2_shadow_ver_blank_start { 560 int reg_num; 561 struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM]; 562 }; 563 564 /* IGA2 Shadow Vertical Blank End */ 565 struct iga2_shadow_ver_blank_end { 566 int reg_num; 567 struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM]; 568 }; 569 570 /* IGA2 Shadow Vertical Sync Start */ 571 struct iga2_shadow_ver_sync_start { 572 int reg_num; 573 struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM]; 574 }; 575 576 /* IGA2 Shadow Vertical Sync End */ 577 struct iga2_shadow_ver_sync_end { 578 int reg_num; 579 struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM]; 580 }; 581 582 /***************************************************** 583 ** Define IGA2 Display Timing **** 584 ******************************************************/ 585 586 /* IGA2 Horizontal Total */ 587 struct iga2_hor_total { 588 int reg_num; 589 struct io_register reg[IGA2_HOR_TOTAL_REG_NUM]; 590 }; 591 592 /* IGA2 Horizontal Addressable Video */ 593 struct iga2_hor_addr { 594 int reg_num; 595 struct io_register reg[IGA2_HOR_ADDR_REG_NUM]; 596 }; 597 598 /* IGA2 Horizontal Blank Start */ 599 struct iga2_hor_blank_start { 600 int reg_num; 601 struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM]; 602 }; 603 604 /* IGA2 Horizontal Blank End */ 605 struct iga2_hor_blank_end { 606 int reg_num; 607 struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM]; 608 }; 609 610 /* IGA2 Horizontal Sync Start */ 611 struct iga2_hor_sync_start { 612 int reg_num; 613 struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM]; 614 }; 615 616 /* IGA2 Horizontal Sync End */ 617 struct iga2_hor_sync_end { 618 int reg_num; 619 struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM]; 620 }; 621 622 /* IGA2 Vertical Total */ 623 struct iga2_ver_total { 624 int reg_num; 625 struct io_register reg[IGA2_VER_TOTAL_REG_NUM]; 626 }; 627 628 /* IGA2 Vertical Addressable Video */ 629 struct iga2_ver_addr { 630 int reg_num; 631 struct io_register reg[IGA2_VER_ADDR_REG_NUM]; 632 }; 633 634 /* IGA2 Vertical Blank Start */ 635 struct iga2_ver_blank_start { 636 int reg_num; 637 struct io_register reg[IGA2_VER_BLANK_START_REG_NUM]; 638 }; 639 640 /* IGA2 Vertical Blank End */ 641 struct iga2_ver_blank_end { 642 int reg_num; 643 struct io_register reg[IGA2_VER_BLANK_END_REG_NUM]; 644 }; 645 646 /* IGA2 Vertical Sync Start */ 647 struct iga2_ver_sync_start { 648 int reg_num; 649 struct io_register reg[IGA2_VER_SYNC_START_REG_NUM]; 650 }; 651 652 /* IGA2 Vertical Sync End */ 653 struct iga2_ver_sync_end { 654 int reg_num; 655 struct io_register reg[IGA2_VER_SYNC_END_REG_NUM]; 656 }; 657 658 /* IGA1 Fetch Count Register */ 659 struct iga1_fetch_count { 660 int reg_num; 661 struct io_register reg[IGA1_FETCH_COUNT_REG_NUM]; 662 }; 663 664 /* IGA2 Fetch Count Register */ 665 struct iga2_fetch_count { 666 int reg_num; 667 struct io_register reg[IGA2_FETCH_COUNT_REG_NUM]; 668 }; 669 670 struct fetch_count { 671 struct iga1_fetch_count iga1_fetch_count_reg; 672 struct iga2_fetch_count iga2_fetch_count_reg; 673 }; 674 675 /* Starting Address Register */ 676 struct iga1_starting_addr { 677 int reg_num; 678 struct io_register reg[IGA1_STARTING_ADDR_REG_NUM]; 679 }; 680 681 struct iga2_starting_addr { 682 int reg_num; 683 struct io_register reg[IGA2_STARTING_ADDR_REG_NUM]; 684 }; 685 686 struct starting_addr { 687 struct iga1_starting_addr iga1_starting_addr_reg; 688 struct iga2_starting_addr iga2_starting_addr_reg; 689 }; 690 691 /* LCD Power Sequence Timer */ 692 struct lcd_pwd_seq_td0 { 693 int reg_num; 694 struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM]; 695 }; 696 697 struct lcd_pwd_seq_td1 { 698 int reg_num; 699 struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM]; 700 }; 701 702 struct lcd_pwd_seq_td2 { 703 int reg_num; 704 struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM]; 705 }; 706 707 struct lcd_pwd_seq_td3 { 708 int reg_num; 709 struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM]; 710 }; 711 712 struct _lcd_pwd_seq_timer { 713 struct lcd_pwd_seq_td0 td0; 714 struct lcd_pwd_seq_td1 td1; 715 struct lcd_pwd_seq_td2 td2; 716 struct lcd_pwd_seq_td3 td3; 717 }; 718 719 /* LCD Scaling Factor */ 720 struct _lcd_hor_scaling_factor { 721 int reg_num; 722 struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM]; 723 }; 724 725 struct _lcd_ver_scaling_factor { 726 int reg_num; 727 struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM]; 728 }; 729 730 struct _lcd_scaling_factor { 731 struct _lcd_hor_scaling_factor lcd_hor_scaling_factor; 732 struct _lcd_ver_scaling_factor lcd_ver_scaling_factor; 733 }; 734 735 struct pll_config { 736 u16 multiplier; 737 u8 divisor; 738 u8 rshift; 739 }; 740 741 struct pll_map { 742 u32 clk; 743 struct pll_config cle266_pll; 744 struct pll_config k800_pll; 745 struct pll_config cx700_pll; 746 struct pll_config vx855_pll; 747 }; 748 749 struct rgbLUT { 750 u8 red; 751 u8 green; 752 u8 blue; 753 }; 754 755 struct lcd_pwd_seq_timer { 756 u16 td0; 757 u16 td1; 758 u16 td2; 759 u16 td3; 760 }; 761 762 /* Display FIFO Relation Registers*/ 763 struct iga1_fifo_depth_select { 764 int reg_num; 765 struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM]; 766 }; 767 768 struct iga1_fifo_threshold_select { 769 int reg_num; 770 struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM]; 771 }; 772 773 struct iga1_fifo_high_threshold_select { 774 int reg_num; 775 struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM]; 776 }; 777 778 struct iga1_display_queue_expire_num { 779 int reg_num; 780 struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM]; 781 }; 782 783 struct iga2_fifo_depth_select { 784 int reg_num; 785 struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM]; 786 }; 787 788 struct iga2_fifo_threshold_select { 789 int reg_num; 790 struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM]; 791 }; 792 793 struct iga2_fifo_high_threshold_select { 794 int reg_num; 795 struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM]; 796 }; 797 798 struct iga2_display_queue_expire_num { 799 int reg_num; 800 struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM]; 801 }; 802 803 struct fifo_depth_select { 804 struct iga1_fifo_depth_select iga1_fifo_depth_select_reg; 805 struct iga2_fifo_depth_select iga2_fifo_depth_select_reg; 806 }; 807 808 struct fifo_threshold_select { 809 struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg; 810 struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg; 811 }; 812 813 struct fifo_high_threshold_select { 814 struct iga1_fifo_high_threshold_select 815 iga1_fifo_high_threshold_select_reg; 816 struct iga2_fifo_high_threshold_select 817 iga2_fifo_high_threshold_select_reg; 818 }; 819 820 struct display_queue_expire_num { 821 struct iga1_display_queue_expire_num 822 iga1_display_queue_expire_num_reg; 823 struct iga2_display_queue_expire_num 824 iga2_display_queue_expire_num_reg; 825 }; 826 827 struct iga1_crtc_timing { 828 struct iga1_hor_total hor_total; 829 struct iga1_hor_addr hor_addr; 830 struct iga1_hor_blank_start hor_blank_start; 831 struct iga1_hor_blank_end hor_blank_end; 832 struct iga1_hor_sync_start hor_sync_start; 833 struct iga1_hor_sync_end hor_sync_end; 834 struct iga1_ver_total ver_total; 835 struct iga1_ver_addr ver_addr; 836 struct iga1_ver_blank_start ver_blank_start; 837 struct iga1_ver_blank_end ver_blank_end; 838 struct iga1_ver_sync_start ver_sync_start; 839 struct iga1_ver_sync_end ver_sync_end; 840 }; 841 842 struct iga2_shadow_crtc_timing { 843 struct iga2_shadow_hor_total hor_total_shadow; 844 struct iga2_shadow_hor_blank_end hor_blank_end_shadow; 845 struct iga2_shadow_ver_total ver_total_shadow; 846 struct iga2_shadow_ver_addr ver_addr_shadow; 847 struct iga2_shadow_ver_blank_start ver_blank_start_shadow; 848 struct iga2_shadow_ver_blank_end ver_blank_end_shadow; 849 struct iga2_shadow_ver_sync_start ver_sync_start_shadow; 850 struct iga2_shadow_ver_sync_end ver_sync_end_shadow; 851 }; 852 853 struct iga2_crtc_timing { 854 struct iga2_hor_total hor_total; 855 struct iga2_hor_addr hor_addr; 856 struct iga2_hor_blank_start hor_blank_start; 857 struct iga2_hor_blank_end hor_blank_end; 858 struct iga2_hor_sync_start hor_sync_start; 859 struct iga2_hor_sync_end hor_sync_end; 860 struct iga2_ver_total ver_total; 861 struct iga2_ver_addr ver_addr; 862 struct iga2_ver_blank_start ver_blank_start; 863 struct iga2_ver_blank_end ver_blank_end; 864 struct iga2_ver_sync_start ver_sync_start; 865 struct iga2_ver_sync_end ver_sync_end; 866 }; 867 868 /* device ID */ 869 #define CLE266_FUNCTION3 0x3123 870 #define KM400_FUNCTION3 0x3205 871 #define CN400_FUNCTION2 0x2259 872 #define CN400_FUNCTION3 0x3259 873 /* support VT3314 chipset */ 874 #define CN700_FUNCTION2 0x2314 875 #define CN700_FUNCTION3 0x3208 876 /* VT3324 chipset */ 877 #define CX700_FUNCTION2 0x2324 878 #define CX700_FUNCTION3 0x3324 879 /* VT3204 chipset*/ 880 #define KM800_FUNCTION3 0x3204 881 /* VT3336 chipset*/ 882 #define KM890_FUNCTION3 0x3336 883 /* VT3327 chipset*/ 884 #define P4M890_FUNCTION3 0x3327 885 /* VT3293 chipset*/ 886 #define CN750_FUNCTION3 0x3208 887 /* VT3364 chipset*/ 888 #define P4M900_FUNCTION3 0x3364 889 /* VT3353 chipset*/ 890 #define VX800_FUNCTION3 0x3353 891 /* VT3409 chipset*/ 892 #define VX855_FUNCTION3 0x3409 893 /* VT3410 chipset*/ 894 #define VX900_FUNCTION3 0x3410 895 896 struct IODATA { 897 u8 Index; 898 u8 Mask; 899 u8 Data; 900 }; 901 902 struct pci_device_id_info { 903 u32 vendor; 904 u32 device; 905 u32 chip_index; 906 }; 907 908 struct via_device_mapping { 909 u32 device; 910 const char *name; 911 }; 912 913 extern unsigned int viafb_second_virtual_xres; 914 extern int viafb_SAMM_ON; 915 extern int viafb_dual_fb; 916 extern int viafb_LCD2_ON; 917 extern int viafb_LCD_ON; 918 extern int viafb_DVI_ON; 919 extern int viafb_hotplug; 920 921 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, 922 struct VideoModeTable *video_mode, int bpp_byte, int set_iga); 923 924 void viafb_set_vclock(u32 CLK, int set_iga); 925 void viafb_load_reg(int timing_value, int viafb_load_reg_num, 926 struct io_register *reg, 927 int io_type); 928 void via_set_source(u32 devices, u8 iga); 929 void via_set_state(u32 devices, u8 state); 930 void via_set_sync_polarity(u32 devices, u8 polarity); 931 u32 via_parse_odev(char *input, char **end); 932 void via_odev_to_seq(struct seq_file *m, u32 odev); 933 void init_ad9389(void); 934 /* Access I/O Function */ 935 void viafb_lock_crt(void); 936 void viafb_unlock_crt(void); 937 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga); 938 void viafb_write_regx(struct io_reg RegTable[], int ItemNum); 939 u32 viafb_get_clk_value(int clk); 940 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active); 941 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ 942 *p_gfx_dpa_setting); 943 944 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, 945 struct VideoModeTable *vmode_tbl1, int video_bpp1); 946 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh, 947 struct VideoModeTable *vmode_tbl); 948 void __devinit viafb_init_chip_info(int chip_type); 949 void __devinit viafb_init_dac(int set_iga); 950 int viafb_get_pixclock(int hres, int vres, int vmode_refresh); 951 int viafb_get_refresh(int hres, int vres, u32 float_refresh); 952 void viafb_update_device_setting(int hres, int vres, int bpp, int flag); 953 954 void viafb_set_iga_path(void); 955 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue); 956 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue); 957 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len); 958 959 #endif /* __HW_H__ */ 960