1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
3
4 #include "../include/drv_types.h"
5
odm_RX_HWAntDivInit(struct odm_dm_struct * dm_odm)6 static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm)
7 {
8 struct adapter *adapter = dm_odm->Adapter;
9 u32 value32;
10
11 /* MAC Setting */
12 value32 = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
13 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
14 /* Pin Settings */
15 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
16 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
17 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* Regb2c[22]=1'b0 disable CS/CG switch */
18 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
19 /* OFDM Settings */
20 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
21 /* CCK Settings */
22 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
23 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
24 ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
25 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */
26 }
27
odm_TRX_HWAntDivInit(struct odm_dm_struct * dm_odm)28 static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm)
29 {
30 struct adapter *adapter = dm_odm->Adapter;
31 u32 value32;
32
33 /* MAC Setting */
34 value32 = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
35 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
36 /* Pin Settings */
37 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
38 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
39 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
40 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
41 /* OFDM Settings */
42 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
43 /* CCK Settings */
44 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
45 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
46 /* Tx Settings */
47 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
48 ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
49
50 /* antenna mapping table */
51 if (!dm_odm->bIsMPChip) { /* testchip */
52 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
53 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
54 } else { /* MPchip */
55 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */
56 }
57 }
58
odm_FastAntTrainingInit(struct odm_dm_struct * dm_odm)59 static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
60 {
61 struct adapter *adapter = dm_odm->Adapter;
62 u32 value32;
63
64 /* MAC Setting */
65 value32 = rtl8188e_PHY_QueryBBReg(adapter, 0x4c, bMaskDWord);
66 rtl8188e_PHY_SetBBReg(adapter, 0x4c, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
67 value32 = rtl8188e_PHY_QueryBBReg(adapter, 0x7B4, bMaskDWord);
68 rtl8188e_PHY_SetBBReg(adapter, 0x7b4, bMaskDWord, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
69
70 /* Match MAC ADDR */
71 rtl8188e_PHY_SetBBReg(adapter, 0x7b4, 0xFFFF, 0);
72 rtl8188e_PHY_SetBBReg(adapter, 0x7b0, bMaskDWord, 0);
73
74 rtl8188e_PHY_SetBBReg(adapter, 0x870, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
75 rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
76 rtl8188e_PHY_SetBBReg(adapter, 0xb2c, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
77 rtl8188e_PHY_SetBBReg(adapter, 0xb2c, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
78 rtl8188e_PHY_SetBBReg(adapter, 0xca4, bMaskDWord, 0x000000a0);
79
80 if (!dm_odm->bIsMPChip) { /* testchip */
81 rtl8188e_PHY_SetBBReg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
82 rtl8188e_PHY_SetBBReg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
83 } else { /* MPchip */
84 rtl8188e_PHY_SetBBReg(adapter, 0x914, bMaskByte0, 1);
85 rtl8188e_PHY_SetBBReg(adapter, 0x914, bMaskByte1, 2);
86 }
87
88 /* Default Ant Setting when no fast training */
89 rtl8188e_PHY_SetBBReg(adapter, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
90 rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX */
91 rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
92
93 /* Enter Training state */
94 rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), 1);
95 rtl8188e_PHY_SetBBReg(adapter, 0xc50, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
96 }
97
ODM_AntennaDiversityInit_88E(struct odm_dm_struct * dm_odm)98 void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm)
99 {
100 if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)
101 odm_RX_HWAntDivInit(dm_odm);
102 else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
103 odm_TRX_HWAntDivInit(dm_odm);
104 else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)
105 odm_FastAntTrainingInit(dm_odm);
106 }
107
ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct * dm_odm,u8 Ant)108 void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant)
109 {
110 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
111 struct adapter *adapter = dm_odm->Adapter;
112 u32 DefaultAnt, OptionalAnt;
113
114 if (dm_fat_tbl->RxIdleAnt != Ant) {
115 if (Ant == MAIN_ANT) {
116 DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
117 OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
118 } else {
119 DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
120 OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
121 }
122
123 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
124 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
125 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
126 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_CTRL_11N, BIT(14) | BIT(13) | BIT(12), DefaultAnt); /* Default TX */
127 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RESP_TX_11N, BIT(6) | BIT(7), DefaultAnt); /* Resp Tx */
128 } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
129 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
130 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
131 }
132 }
133 dm_fat_tbl->RxIdleAnt = Ant;
134 if (Ant != MAIN_ANT)
135 pr_info("RxIdleAnt=AUX_ANT\n");
136 }
137
odm_UpdateTxAnt_88E(struct odm_dm_struct * dm_odm,u8 Ant,u32 MacId)138 static void odm_UpdateTxAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant, u32 MacId)
139 {
140 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
141 u8 TargetAnt;
142
143 if (Ant == MAIN_ANT)
144 TargetAnt = MAIN_ANT_CG_TRX;
145 else
146 TargetAnt = AUX_ANT_CG_TRX;
147 dm_fat_tbl->antsel_a[MacId] = TargetAnt & BIT(0);
148 dm_fat_tbl->antsel_b[MacId] = (TargetAnt & BIT(1)) >> 1;
149 dm_fat_tbl->antsel_c[MacId] = (TargetAnt & BIT(2)) >> 2;
150 }
151
ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct * dm_odm,u8 * pDesc,u8 macId)152 void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *dm_odm, u8 *pDesc, u8 macId)
153 {
154 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
155
156 if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) {
157 SET_TX_DESC_ANTSEL_A_88E(pDesc, dm_fat_tbl->antsel_a[macId]);
158 SET_TX_DESC_ANTSEL_B_88E(pDesc, dm_fat_tbl->antsel_b[macId]);
159 SET_TX_DESC_ANTSEL_C_88E(pDesc, dm_fat_tbl->antsel_c[macId]);
160 }
161 }
162
ODM_AntselStatistics_88E(struct odm_dm_struct * dm_odm,u8 antsel_tr_mux,u32 MacId,u8 RxPWDBAll)163 void ODM_AntselStatistics_88E(struct odm_dm_struct *dm_odm, u8 antsel_tr_mux, u32 MacId, u8 RxPWDBAll)
164 {
165 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
166 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
167 if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
168 dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
169 dm_fat_tbl->MainAnt_Cnt[MacId]++;
170 } else {
171 dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
172 dm_fat_tbl->AuxAnt_Cnt[MacId]++;
173 }
174 } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
175 if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
176 dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll;
177 dm_fat_tbl->MainAnt_Cnt[MacId]++;
178 } else {
179 dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll;
180 dm_fat_tbl->AuxAnt_Cnt[MacId]++;
181 }
182 }
183 }
184
odm_HWAntDiv(struct odm_dm_struct * dm_odm)185 static void odm_HWAntDiv(struct odm_dm_struct *dm_odm)
186 {
187 u32 i, MinRSSI = 0xFF, AntDivMaxRSSI = 0, MaxRSSI = 0, LocalMinRSSI, LocalMaxRSSI;
188 u32 Main_RSSI, Aux_RSSI;
189 u8 RxIdleAnt = 0, TargetAnt = 7;
190 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
191 struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable;
192 struct sta_info *pEntry;
193
194 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
195 pEntry = dm_odm->pODM_StaInfo[i];
196 if (IS_STA_VALID(pEntry)) {
197 /* 2 Caculate RSSI per Antenna */
198 Main_RSSI = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ? (dm_fat_tbl->MainAnt_Sum[i] / dm_fat_tbl->MainAnt_Cnt[i]) : 0;
199 Aux_RSSI = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ? (dm_fat_tbl->AuxAnt_Sum[i] / dm_fat_tbl->AuxAnt_Cnt[i]) : 0;
200 TargetAnt = (Main_RSSI >= Aux_RSSI) ? MAIN_ANT : AUX_ANT;
201 /* 2 Select MaxRSSI for DIG */
202 LocalMaxRSSI = (Main_RSSI > Aux_RSSI) ? Main_RSSI : Aux_RSSI;
203 if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
204 AntDivMaxRSSI = LocalMaxRSSI;
205 if (LocalMaxRSSI > MaxRSSI)
206 MaxRSSI = LocalMaxRSSI;
207
208 /* 2 Select RX Idle Antenna */
209 if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
210 Main_RSSI = Aux_RSSI;
211 else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
212 Aux_RSSI = Main_RSSI;
213
214 LocalMinRSSI = (Main_RSSI > Aux_RSSI) ? Aux_RSSI : Main_RSSI;
215 if (LocalMinRSSI < MinRSSI) {
216 MinRSSI = LocalMinRSSI;
217 RxIdleAnt = TargetAnt;
218 }
219 /* 2 Select TRX Antenna */
220 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
221 odm_UpdateTxAnt_88E(dm_odm, TargetAnt, i);
222 }
223 dm_fat_tbl->MainAnt_Sum[i] = 0;
224 dm_fat_tbl->AuxAnt_Sum[i] = 0;
225 dm_fat_tbl->MainAnt_Cnt[i] = 0;
226 dm_fat_tbl->AuxAnt_Cnt[i] = 0;
227 }
228
229 /* 2 Set RX Idle Antenna */
230 ODM_UpdateRxIdleAnt_88E(dm_odm, RxIdleAnt);
231
232 pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
233 pDM_DigTable->RSSI_max = MaxRSSI;
234 }
235
ODM_AntennaDiversity_88E(struct odm_dm_struct * dm_odm)236 void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm)
237 {
238 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
239 struct adapter *adapter = dm_odm->Adapter;
240
241 if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))
242 return;
243 if (!dm_odm->bLinked) {
244 if (dm_fat_tbl->bBecomeLinked) {
245 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); /* RegC50[7]=1'b1 enable HW AntDiv */
246 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 0); /* Enable CCK AntDiv */
247 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
248 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
249 dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
250 }
251 return;
252 } else {
253 if (!dm_fat_tbl->bBecomeLinked) {
254 /* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */
255 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
256 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 1); /* Enable CCK AntDiv */
257 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
258 rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
259 dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
260 }
261 }
262 if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV))
263 odm_HWAntDiv(dm_odm);
264 }
265