1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) Realtek Semiconductor Corp. */
3 
4 #include "../include/drv_types.h"
5 
6 static u8 RETRY_PENALTY[PERENTRY][RETRYSIZE + 1] = {
7 		{5, 4, 3, 2, 0, 3},      /* 92 , idx = 0 */
8 		{6, 5, 4, 3, 0, 4},      /* 86 , idx = 1 */
9 		{6, 5, 4, 2, 0, 4},      /* 81 , idx = 2 */
10 		{8, 7, 6, 4, 0, 6},      /* 75 , idx = 3 */
11 		{10, 9, 8, 6, 0, 8},     /* 71	, idx = 4 */
12 		{10, 9, 8, 4, 0, 8},     /* 66	, idx = 5 */
13 		{10, 9, 8, 2, 0, 8},     /* 62	, idx = 6 */
14 		{10, 9, 8, 0, 0, 8},     /* 59	, idx = 7 */
15 		{18, 17, 16, 8, 0, 16},  /* 53 , idx = 8 */
16 		{26, 25, 24, 16, 0, 24}, /* 50	, idx = 9 */
17 		{34, 33, 32, 24, 0, 32}, /* 47	, idx = 0x0a */
18 		{34, 31, 28, 20, 0, 32}, /* 43	, idx = 0x0b */
19 		{34, 31, 27, 18, 0, 32}, /* 40 , idx = 0x0c */
20 		{34, 31, 26, 16, 0, 32}, /* 37 , idx = 0x0d */
21 		{34, 30, 22, 16, 0, 32}, /* 32 , idx = 0x0e */
22 		{34, 30, 24, 16, 0, 32}, /* 26 , idx = 0x0f */
23 		{49, 46, 40, 16, 0, 48}, /* 20	, idx = 0x10 */
24 		{49, 45, 32, 0, 0, 48},  /* 17 , idx = 0x11 */
25 		{49, 45, 22, 18, 0, 48}, /* 15	, idx = 0x12 */
26 		{49, 40, 24, 16, 0, 48}, /* 12	, idx = 0x13 */
27 		{49, 32, 18, 12, 0, 48}, /* 9 , idx = 0x14 */
28 		{49, 22, 18, 14, 0, 48}, /* 6 , idx = 0x15 */
29 		{49, 16, 16, 0, 0, 48}
30 	}; /* 3, idx = 0x16 */
31 
32 static u8 PT_PENALTY[RETRYSIZE + 1] = {34, 31, 30, 24, 0, 32};
33 
34 /*  wilson modify */
35 static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {
36 		{4, 4, 4, 5, 4, 4, 5, 7, 7, 7, 8, 0x0a,	       /*  SS>TH */
37 		4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d,
38 		5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f},			   /*  0329 R01 */
39 		{0x0a, 0x0a, 0x0b, 0x0c, 0x0a,
40 		0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x14,	   /*  SS<TH */
41 		0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x11, 0x13, 0x15,
42 		9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13}
43 	};
44 
45 static u8 RETRY_PENALTY_UP_IDX[RATESIZE] = {
46 		0x0c, 0x0d, 0x0d, 0x0f, 0x0d, 0x0e,
47 		0x0f, 0x0f, 0x10, 0x12, 0x13, 0x14,	       /*  SS>TH */
48 		0x0f, 0x10, 0x10, 0x12, 0x12, 0x13, 0x14, 0x15,
49 		0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15};
50 
51 static u8 RSSI_THRESHOLD[RATESIZE] = {
52 		0, 0, 0, 0,
53 		0, 0, 0, 0, 0, 0x24, 0x26, 0x2a,
54 		0x18, 0x1a, 0x1d, 0x1f, 0x21, 0x27, 0x29, 0x2a,
55 		0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c};
56 
57 static u16 N_THRESHOLD_HIGH[RATESIZE] = {
58 		4, 4, 8, 16,
59 		24, 36, 48, 72, 96, 144, 192, 216,
60 		60, 80, 100, 160, 240, 400, 560, 640,
61 		300, 320, 480, 720, 1000, 1200, 1600, 2000};
62 static u16 N_THRESHOLD_LOW[RATESIZE] = {
63 		2, 2, 4, 8,
64 		12, 18, 24, 36, 48, 72, 96, 108,
65 		30, 40, 50, 80, 120, 200, 280, 320,
66 		150, 160, 240, 360, 500, 600, 800, 1000};
67 
68 static u8 DROPING_NECESSARY[RATESIZE] = {
69 		1, 1, 1, 1,
70 		1, 2, 3, 4, 5, 6, 7, 8,
71 		1, 2, 3, 4, 5, 6, 7, 8,
72 		5, 6, 7, 8, 9, 10, 11, 12};
73 
74 static u8 PendingForRateUpFail[5] = {2, 10, 24, 40, 60};
75 static u16 DynamicTxRPTTiming[6] = {
76 	0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0x927c}; /*  200ms-1200ms */
77 
78 /*  End Rate adaptive parameters */
79 
odm_SetTxRPTTiming_8188E(struct odm_dm_struct * dm_odm,struct odm_ra_info * pRaInfo,u8 extend)80 static void odm_SetTxRPTTiming_8188E(
81 		struct odm_dm_struct *dm_odm,
82 		struct odm_ra_info *pRaInfo,
83 		u8 extend
84 	)
85 {
86 	u8 idx = 0;
87 
88 	for (idx = 0; idx < 5; idx++)
89 		if (DynamicTxRPTTiming[idx] == pRaInfo->RptTime)
90 			break;
91 
92 	if (extend == 0) { /*  back to default timing */
93 		idx = 0;  /* 200ms */
94 	} else if (extend == 1) {/*  increase the timing */
95 		idx += 1;
96 		if (idx > 5)
97 			idx = 5;
98 	} else if (extend == 2) {/*  decrease the timing */
99 		if (idx != 0)
100 			idx -= 1;
101 	}
102 	pRaInfo->RptTime = DynamicTxRPTTiming[idx];
103 }
104 
odm_RateDown_8188E(struct odm_dm_struct * dm_odm,struct odm_ra_info * pRaInfo)105 static int odm_RateDown_8188E(struct odm_dm_struct *dm_odm, struct odm_ra_info *pRaInfo)
106 {
107 	u8 RateID, LowestRate, HighestRate;
108 	u8 i;
109 
110 	if (NULL == pRaInfo)
111 		return -1;
112 	RateID = pRaInfo->PreRate;
113 	LowestRate = pRaInfo->LowestRate;
114 	HighestRate = pRaInfo->HighestRate;
115 
116 	if (RateID > HighestRate) {
117 		RateID = HighestRate;
118 	} else if (pRaInfo->RateSGI) {
119 		pRaInfo->RateSGI = 0;
120 	} else if (RateID > LowestRate) {
121 		if (RateID > 0) {
122 			for (i = RateID - 1; i > LowestRate; i--) {
123 				if (pRaInfo->RAUseRate & BIT(i)) {
124 					RateID = i;
125 					goto RateDownFinish;
126 				}
127 			}
128 		}
129 	} else if (RateID <= LowestRate) {
130 		RateID = LowestRate;
131 	}
132 RateDownFinish:
133 	if (pRaInfo->RAWaitingCounter == 1) {
134 		pRaInfo->RAWaitingCounter += 1;
135 		pRaInfo->RAPendingCounter += 1;
136 	} else if (pRaInfo->RAWaitingCounter == 0) {
137 		;
138 	} else {
139 		pRaInfo->RAWaitingCounter = 0;
140 		pRaInfo->RAPendingCounter = 0;
141 	}
142 
143 	if (pRaInfo->RAPendingCounter >= 4)
144 		pRaInfo->RAPendingCounter = 4;
145 
146 	pRaInfo->DecisionRate = RateID;
147 	odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 2);
148 	return 0;
149 }
150 
odm_RateUp_8188E(struct odm_dm_struct * dm_odm,struct odm_ra_info * pRaInfo)151 static int odm_RateUp_8188E(
152 		struct odm_dm_struct *dm_odm,
153 		struct odm_ra_info *pRaInfo
154 	)
155 {
156 	u8 RateID, HighestRate;
157 	u8 i;
158 
159 	if (NULL == pRaInfo)
160 		return -1;
161 	RateID = pRaInfo->PreRate;
162 	HighestRate = pRaInfo->HighestRate;
163 	if (pRaInfo->RAWaitingCounter == 1) {
164 		pRaInfo->RAWaitingCounter = 0;
165 		pRaInfo->RAPendingCounter = 0;
166 	} else if (pRaInfo->RAWaitingCounter > 1) {
167 		pRaInfo->PreRssiStaRA = pRaInfo->RssiStaRA;
168 		goto RateUpfinish;
169 	}
170 	odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 0);
171 
172 	if (RateID < HighestRate) {
173 		for (i = RateID + 1; i <= HighestRate; i++) {
174 			if (pRaInfo->RAUseRate & BIT(i)) {
175 				RateID = i;
176 				goto RateUpfinish;
177 			}
178 		}
179 	} else if (RateID == HighestRate) {
180 		if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1))
181 			pRaInfo->RateSGI = 1;
182 		else if ((pRaInfo->SGIEnable) != 1)
183 			pRaInfo->RateSGI = 0;
184 	} else {
185 		RateID = HighestRate;
186 	}
187 RateUpfinish:
188 	if (pRaInfo->RAWaitingCounter == (4 + PendingForRateUpFail[pRaInfo->RAPendingCounter]))
189 		pRaInfo->RAWaitingCounter = 0;
190 	else
191 		pRaInfo->RAWaitingCounter++;
192 
193 	pRaInfo->DecisionRate = RateID;
194 	return 0;
195 }
196 
odm_ResetRaCounter_8188E(struct odm_ra_info * pRaInfo)197 static void odm_ResetRaCounter_8188E(struct odm_ra_info *pRaInfo)
198 {
199 	u8 RateID;
200 
201 	RateID = pRaInfo->DecisionRate;
202 	pRaInfo->NscUp = (N_THRESHOLD_HIGH[RateID] + N_THRESHOLD_LOW[RateID]) >> 1;
203 	pRaInfo->NscDown = (N_THRESHOLD_HIGH[RateID] + N_THRESHOLD_LOW[RateID]) >> 1;
204 }
205 
odm_RateDecision_8188E(struct odm_dm_struct * dm_odm,struct odm_ra_info * pRaInfo)206 static void odm_RateDecision_8188E(struct odm_dm_struct *dm_odm,
207 		struct odm_ra_info *pRaInfo
208 	)
209 {
210 	u8 RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0;
211 	/* u32 pool_retry; */
212 	static u8 DynamicTxRPTTimingCounter;
213 
214 	if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) { /*  STA used and data packet exits */
215 		if ((pRaInfo->RssiStaRA < (pRaInfo->PreRssiStaRA - 3)) ||
216 		    (pRaInfo->RssiStaRA > (pRaInfo->PreRssiStaRA + 3))) {
217 			pRaInfo->RAWaitingCounter = 0;
218 			pRaInfo->RAPendingCounter = 0;
219 		}
220 		/*  Start RA decision */
221 		if (pRaInfo->PreRate > pRaInfo->HighestRate)
222 			RateID = pRaInfo->HighestRate;
223 		else
224 			RateID = pRaInfo->PreRate;
225 		if (pRaInfo->RssiStaRA > RSSI_THRESHOLD[RateID])
226 			RtyPtID = 0;
227 		else
228 			RtyPtID = 1;
229 		PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; /* TODO by page */
230 
231 		pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0];
232 		pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1];
233 		pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2];
234 		pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3];
235 		pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4];
236 		if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]))
237 			pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5];
238 		else
239 			pRaInfo->NscDown = 0;
240 
241 		/*  rate up */
242 		PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID];
243 		pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0];
244 		pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1];
245 		pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2];
246 		pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3];
247 		pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4];
248 		if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]))
249 			pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5];
250 		else
251 			pRaInfo->NscUp = 0;
252 
253 		if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||
254 		    (pRaInfo->DROP > DROPING_NECESSARY[RateID]))
255 			odm_RateDown_8188E(dm_odm, pRaInfo);
256 		else if (pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])
257 			odm_RateUp_8188E(dm_odm, pRaInfo);
258 
259 		if (pRaInfo->DecisionRate > pRaInfo->HighestRate)
260 			pRaInfo->DecisionRate = pRaInfo->HighestRate;
261 
262 		if ((pRaInfo->DecisionRate) == (pRaInfo->PreRate))
263 			DynamicTxRPTTimingCounter += 1;
264 		else
265 			DynamicTxRPTTimingCounter = 0;
266 
267 		if (DynamicTxRPTTimingCounter >= 4) {
268 			odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 1);
269 			DynamicTxRPTTimingCounter = 0;
270 		}
271 
272 		pRaInfo->PreRate = pRaInfo->DecisionRate;  /* YJ, add, 120120 */
273 
274 		odm_ResetRaCounter_8188E(pRaInfo);
275 	}
276 }
277 
odm_ARFBRefresh_8188E(struct odm_dm_struct * dm_odm,struct odm_ra_info * pRaInfo)278 static int odm_ARFBRefresh_8188E(struct odm_dm_struct *dm_odm, struct odm_ra_info *pRaInfo)
279 {  /*  Wilson 2011/10/26 */
280 	u32 MaskFromReg;
281 	s8 i;
282 	int res;
283 
284 	switch (pRaInfo->RateID) {
285 	case RATR_INX_WIRELESS_NGB:
286 		pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff015;
287 		break;
288 	case RATR_INX_WIRELESS_NG:
289 		pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff010;
290 		break;
291 	case RATR_INX_WIRELESS_NB:
292 		pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff005;
293 		break;
294 	case RATR_INX_WIRELESS_N:
295 		pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff000;
296 		break;
297 	case RATR_INX_WIRELESS_GB:
298 		pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x00000ff5;
299 		break;
300 	case RATR_INX_WIRELESS_G:
301 		pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x00000ff0;
302 		break;
303 	case RATR_INX_WIRELESS_B:
304 		pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0000000d;
305 		break;
306 	case 12:
307 		res = rtw_read32(dm_odm->Adapter, REG_ARFR0, &MaskFromReg);
308 		if (res)
309 			return res;
310 
311 		pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
312 		break;
313 	case 13:
314 		res = rtw_read32(dm_odm->Adapter, REG_ARFR1, &MaskFromReg);
315 		if (res)
316 			return res;
317 
318 		pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
319 		break;
320 	case 14:
321 		res = rtw_read32(dm_odm->Adapter, REG_ARFR2, &MaskFromReg);
322 		if (res)
323 			return res;
324 
325 		pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
326 		break;
327 	case 15:
328 		res = rtw_read32(dm_odm->Adapter, REG_ARFR3, &MaskFromReg);
329 		if (res)
330 			return res;
331 
332 		pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg;
333 		break;
334 	default:
335 		pRaInfo->RAUseRate = (pRaInfo->RateMask);
336 		break;
337 	}
338 	/*  Highest rate */
339 	if (pRaInfo->RAUseRate) {
340 		for (i = RATESIZE; i >= 0; i--) {
341 			if ((pRaInfo->RAUseRate) & BIT(i)) {
342 				pRaInfo->HighestRate = i;
343 				break;
344 			}
345 		}
346 	} else {
347 		pRaInfo->HighestRate = 0;
348 	}
349 	/*  Lowest rate */
350 	if (pRaInfo->RAUseRate) {
351 		for (i = 0; i < RATESIZE; i++) {
352 			if ((pRaInfo->RAUseRate) & BIT(i)) {
353 				pRaInfo->LowestRate = i;
354 				break;
355 			}
356 		}
357 	} else {
358 		pRaInfo->LowestRate = 0;
359 	}
360 	if (pRaInfo->HighestRate > 0x13)
361 		pRaInfo->PTModeSS = 3;
362 	else if (pRaInfo->HighestRate > 0x0b)
363 		pRaInfo->PTModeSS = 2;
364 	else if (pRaInfo->HighestRate > 0x03)
365 		pRaInfo->PTModeSS = 1;
366 	else
367 		pRaInfo->PTModeSS = 0;
368 
369 	if (pRaInfo->DecisionRate > pRaInfo->HighestRate)
370 		pRaInfo->DecisionRate = pRaInfo->HighestRate;
371 
372 	return 0;
373 }
374 
odm_PTTryState_8188E(struct odm_ra_info * pRaInfo)375 static void odm_PTTryState_8188E(struct odm_ra_info *pRaInfo)
376 {
377 	pRaInfo->PTTryState = 0;
378 	switch (pRaInfo->PTModeSS) {
379 	case 3:
380 		if (pRaInfo->DecisionRate >= 0x19)
381 			pRaInfo->PTTryState = 1;
382 		break;
383 	case 2:
384 		if (pRaInfo->DecisionRate >= 0x11)
385 			pRaInfo->PTTryState = 1;
386 		break;
387 	case 1:
388 		if (pRaInfo->DecisionRate >= 0x0a)
389 			pRaInfo->PTTryState = 1;
390 		break;
391 	case 0:
392 		if (pRaInfo->DecisionRate >= 0x03)
393 			pRaInfo->PTTryState = 1;
394 		break;
395 	default:
396 		pRaInfo->PTTryState = 0;
397 		break;
398 	}
399 
400 	if (pRaInfo->RssiStaRA < 48) {
401 		pRaInfo->PTStage = 0;
402 	} else if (pRaInfo->PTTryState == 1) {
403 		if ((pRaInfo->PTStopCount >= 10) ||
404 		    (pRaInfo->PTPreRssi > pRaInfo->RssiStaRA + 5) ||
405 		    (pRaInfo->PTPreRssi < pRaInfo->RssiStaRA - 5) ||
406 		    (pRaInfo->DecisionRate != pRaInfo->PTPreRate)) {
407 			if (pRaInfo->PTStage == 0)
408 				pRaInfo->PTStage = 1;
409 			else if (pRaInfo->PTStage == 1)
410 				pRaInfo->PTStage = 3;
411 			else
412 				pRaInfo->PTStage = 5;
413 
414 			pRaInfo->PTPreRssi = pRaInfo->RssiStaRA;
415 			pRaInfo->PTStopCount = 0;
416 		} else {
417 			pRaInfo->RAstage = 0;
418 			pRaInfo->PTStopCount++;
419 		}
420 	} else {
421 		pRaInfo->PTStage = 0;
422 		pRaInfo->RAstage = 0;
423 	}
424 	pRaInfo->PTPreRate = pRaInfo->DecisionRate;
425 }
426 
odm_PTDecision_8188E(struct odm_ra_info * pRaInfo)427 static void odm_PTDecision_8188E(struct odm_ra_info *pRaInfo)
428 {
429 	u8 j;
430 	u8 temp_stage;
431 	u32 numsc;
432 	u32 num_total;
433 	u8 stage_id;
434 
435 	numsc  = 0;
436 	num_total = pRaInfo->TOTAL * PT_PENALTY[5];
437 	for (j = 0; j <= 4; j++) {
438 		numsc += pRaInfo->RTY[j] * PT_PENALTY[j];
439 		if (numsc > num_total)
440 			break;
441 	}
442 
443 	j = j >> 1;
444 	temp_stage = (pRaInfo->PTStage + 1) >> 1;
445 	if (temp_stage > j)
446 		stage_id = temp_stage - j;
447 	else
448 		stage_id = 0;
449 
450 	pRaInfo->PTSmoothFactor = (pRaInfo->PTSmoothFactor >> 1) + (pRaInfo->PTSmoothFactor >> 2) + stage_id * 16 + 2;
451 	if (pRaInfo->PTSmoothFactor > 192)
452 		pRaInfo->PTSmoothFactor = 192;
453 	stage_id = pRaInfo->PTSmoothFactor >> 6;
454 	temp_stage = stage_id * 2;
455 	if (temp_stage != 0)
456 		temp_stage -= 1;
457 	if (pRaInfo->DROP > 3)
458 		temp_stage = 0;
459 	pRaInfo->PTStage = temp_stage;
460 }
461 
462 static void
odm_RATxRPTTimerSetting(struct odm_dm_struct * dm_odm,u16 minRptTime)463 odm_RATxRPTTimerSetting(
464 		struct odm_dm_struct *dm_odm,
465 		u16 minRptTime
466 )
467 {
468 	if (dm_odm->CurrminRptTime != minRptTime) {
469 		rtw_rpt_timer_cfg_cmd(dm_odm->Adapter, minRptTime);
470 		dm_odm->CurrminRptTime = minRptTime;
471 	}
472 }
473 
ODM_RAInfo_Init(struct odm_dm_struct * dm_odm,u8 macid)474 int ODM_RAInfo_Init(struct odm_dm_struct *dm_odm, u8 macid)
475 {
476 	struct odm_ra_info *pRaInfo = &dm_odm->RAInfo[macid];
477 	u8 WirelessMode = 0xFF; /* invalid value */
478 	u8 max_rate_idx = 0x13; /* MCS7 */
479 	if (dm_odm->pWirelessMode)
480 		WirelessMode = *dm_odm->pWirelessMode;
481 
482 	if (WirelessMode != 0xFF) {
483 		if (WirelessMode & ODM_WM_N24G)
484 			max_rate_idx = 0x13;
485 		else if (WirelessMode & ODM_WM_G)
486 			max_rate_idx = 0x0b;
487 		else if (WirelessMode & ODM_WM_B)
488 			max_rate_idx = 0x03;
489 	}
490 
491 	pRaInfo->DecisionRate = max_rate_idx;
492 	pRaInfo->PreRate = max_rate_idx;
493 	pRaInfo->HighestRate = max_rate_idx;
494 	pRaInfo->LowestRate = 0;
495 	pRaInfo->RateID = 0;
496 	pRaInfo->RateMask = 0xffffffff;
497 	pRaInfo->RssiStaRA = 0;
498 	pRaInfo->PreRssiStaRA = 0;
499 	pRaInfo->SGIEnable = 0;
500 	pRaInfo->RAUseRate = 0xffffffff;
501 	pRaInfo->NscDown = (N_THRESHOLD_HIGH[0x13] + N_THRESHOLD_LOW[0x13]) / 2;
502 	pRaInfo->NscUp = (N_THRESHOLD_HIGH[0x13] + N_THRESHOLD_LOW[0x13]) / 2;
503 	pRaInfo->RateSGI = 0;
504 	pRaInfo->Active = 1;	/* Active is not used at present. by page, 110819 */
505 	pRaInfo->RptTime = 0x927c;
506 	pRaInfo->DROP = 0;
507 	pRaInfo->RTY[0] = 0;
508 	pRaInfo->RTY[1] = 0;
509 	pRaInfo->RTY[2] = 0;
510 	pRaInfo->RTY[3] = 0;
511 	pRaInfo->RTY[4] = 0;
512 	pRaInfo->TOTAL = 0;
513 	pRaInfo->RAWaitingCounter = 0;
514 	pRaInfo->RAPendingCounter = 0;
515 	pRaInfo->PTActive = 1;   /*  Active when this STA is use */
516 	pRaInfo->PTTryState = 0;
517 	pRaInfo->PTStage = 5; /*  Need to fill into HW_PWR_STATUS */
518 	pRaInfo->PTSmoothFactor = 192;
519 	pRaInfo->PTStopCount = 0;
520 	pRaInfo->PTPreRate = 0;
521 	pRaInfo->PTPreRssi = 0;
522 	pRaInfo->PTModeSS = 0;
523 	pRaInfo->RAstage = 0;
524 	return 0;
525 }
526 
ODM_RAInfo_Init_all(struct odm_dm_struct * dm_odm)527 int ODM_RAInfo_Init_all(struct odm_dm_struct *dm_odm)
528 {
529 	u8 macid = 0;
530 
531 	dm_odm->CurrminRptTime = 0;
532 
533 	for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++)
534 		ODM_RAInfo_Init(dm_odm, macid);
535 
536 	return 0;
537 }
538 
ODM_RA_GetShortGI_8188E(struct odm_dm_struct * dm_odm,u8 macid)539 u8 ODM_RA_GetShortGI_8188E(struct odm_dm_struct *dm_odm, u8 macid)
540 {
541 	if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
542 		return 0;
543 	return dm_odm->RAInfo[macid].RateSGI;
544 }
545 
ODM_RA_GetDecisionRate_8188E(struct odm_dm_struct * dm_odm,u8 macid)546 u8 ODM_RA_GetDecisionRate_8188E(struct odm_dm_struct *dm_odm, u8 macid)
547 {
548 	u8 DecisionRate = 0;
549 
550 	if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
551 		return 0;
552 	DecisionRate = (dm_odm->RAInfo[macid].DecisionRate);
553 	return DecisionRate;
554 }
555 
ODM_RA_GetHwPwrStatus_8188E(struct odm_dm_struct * dm_odm,u8 macid)556 u8 ODM_RA_GetHwPwrStatus_8188E(struct odm_dm_struct *dm_odm, u8 macid)
557 {
558 	u8 PTStage = 5;
559 
560 	if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
561 		return 0;
562 	PTStage = (dm_odm->RAInfo[macid].PTStage);
563 	return PTStage;
564 }
565 
ODM_RA_UpdateRateInfo_8188E(struct odm_dm_struct * dm_odm,u8 macid,u8 RateID,u32 RateMask,u8 SGIEnable)566 void ODM_RA_UpdateRateInfo_8188E(struct odm_dm_struct *dm_odm, u8 macid, u8 RateID, u32 RateMask, u8 SGIEnable)
567 {
568 	struct odm_ra_info *pRaInfo = NULL;
569 
570 	if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
571 		return;
572 
573 	pRaInfo = &dm_odm->RAInfo[macid];
574 	pRaInfo->RateID = RateID;
575 	pRaInfo->RateMask = RateMask;
576 	pRaInfo->SGIEnable = SGIEnable;
577 	odm_ARFBRefresh_8188E(dm_odm, pRaInfo);
578 }
579 
ODM_RA_SetRSSI_8188E(struct odm_dm_struct * dm_odm,u8 macid,u8 Rssi)580 void ODM_RA_SetRSSI_8188E(struct odm_dm_struct *dm_odm, u8 macid, u8 Rssi)
581 {
582 	struct odm_ra_info *pRaInfo = NULL;
583 
584 	if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM))
585 		return;
586 
587 	pRaInfo = &dm_odm->RAInfo[macid];
588 	pRaInfo->RssiStaRA = Rssi;
589 }
590 
ODM_RA_Set_TxRPT_Time(struct odm_dm_struct * dm_odm,u16 minRptTime)591 void ODM_RA_Set_TxRPT_Time(struct odm_dm_struct *dm_odm, u16 minRptTime)
592 {
593 	rtw_write16(dm_odm->Adapter, REG_TX_RPT_TIME, minRptTime);
594 }
595 
ODM_RA_TxRPT2Handle_8188E(struct odm_dm_struct * dm_odm,u8 * TxRPT_Buf,u16 TxRPT_Len,u32 macid_entry0,u32 macid_entry1)596 void ODM_RA_TxRPT2Handle_8188E(struct odm_dm_struct *dm_odm, u8 *TxRPT_Buf, u16 TxRPT_Len, u32 macid_entry0, u32 macid_entry1)
597 {
598 	struct odm_ra_info *pRAInfo = NULL;
599 	u8 MacId = 0;
600 	u8 *pBuffer = NULL;
601 	u32 valid = 0, ItemNum = 0;
602 	u16 minRptTime = 0x927c;
603 
604 	ItemNum = TxRPT_Len >> 3;
605 	pBuffer = TxRPT_Buf;
606 
607 	do {
608 		if (MacId >= ODM_ASSOCIATE_ENTRY_NUM)
609 			valid = 0;
610 		else if (MacId >= 32)
611 			valid = (1 << (MacId - 32)) & macid_entry1;
612 		else
613 			valid = (1 << MacId) & macid_entry0;
614 
615 		pRAInfo = &dm_odm->RAInfo[MacId];
616 		if (valid) {
617 			pRAInfo->RTY[0] = le16_to_cpup((__le16 *)pBuffer);
618 			pRAInfo->RTY[1] = pBuffer[2];
619 			pRAInfo->RTY[2] = pBuffer[3];
620 			pRAInfo->RTY[3] = pBuffer[4];
621 			pRAInfo->RTY[4] = pBuffer[5];
622 			pRAInfo->DROP = pBuffer[6];
623 			pRAInfo->TOTAL = pRAInfo->RTY[0] + pRAInfo->RTY[1] +
624 					 pRAInfo->RTY[2] + pRAInfo->RTY[3] +
625 					 pRAInfo->RTY[4] + pRAInfo->DROP;
626 			if (pRAInfo->TOTAL != 0) {
627 				if (pRAInfo->PTActive) {
628 					if (pRAInfo->RAstage < 5)
629 						odm_RateDecision_8188E(dm_odm, pRAInfo);
630 					else if (pRAInfo->RAstage == 5) /*  Power training try state */
631 						odm_PTTryState_8188E(pRAInfo);
632 					else /*  RAstage == 6 */
633 						odm_PTDecision_8188E(pRAInfo);
634 
635 					/*  Stage_RA counter */
636 					if (pRAInfo->RAstage <= 5)
637 						pRAInfo->RAstage++;
638 					else
639 						pRAInfo->RAstage = 0;
640 				} else {
641 					odm_RateDecision_8188E(dm_odm, pRAInfo);
642 				}
643 			}
644 		}
645 
646 		if (minRptTime > pRAInfo->RptTime)
647 			minRptTime = pRAInfo->RptTime;
648 
649 		pBuffer += TX_RPT2_ITEM_SIZE;
650 		MacId++;
651 	} while (MacId < ItemNum);
652 
653 	odm_RATxRPTTimerSetting(dm_odm, minRptTime);
654 }
655