1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell Octeon EP (EndPoint) Ethernet Driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #ifndef _OCTEP_MAIN_H_
9 #define _OCTEP_MAIN_H_
10
11 #include "octep_tx.h"
12 #include "octep_rx.h"
13 #include "octep_ctrl_mbox.h"
14
15 #define OCTEP_DRV_NAME "octeon_ep"
16 #define OCTEP_DRV_STRING "Marvell Octeon EndPoint NIC Driver"
17
18 #define OCTEP_PCIID_CN93_PF 0xB200177d
19 #define OCTEP_PCIID_CN93_VF 0xB203177d
20
21 #define OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200
22 #define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203
23
24 #define OCTEP_PCI_DEVICE_ID_CNF95N_PF 0xB400 //95N PF
25
26 #define OCTEP_MAX_QUEUES 63
27 #define OCTEP_MAX_IQ OCTEP_MAX_QUEUES
28 #define OCTEP_MAX_OQ OCTEP_MAX_QUEUES
29 #define OCTEP_MAX_VF 64
30
31 #define OCTEP_MAX_MSIX_VECTORS OCTEP_MAX_OQ
32
33 /* Flags to disable and enable Interrupts */
34 #define OCTEP_INPUT_INTR (1)
35 #define OCTEP_OUTPUT_INTR (2)
36 #define OCTEP_MBOX_INTR (4)
37 #define OCTEP_ALL_INTR 0xff
38
39 #define OCTEP_IQ_INTR_RESEND_BIT 59
40 #define OCTEP_OQ_INTR_RESEND_BIT 59
41
42 #define OCTEP_MMIO_REGIONS 3
43 /* PCI address space mapping information.
44 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
45 * Octeon gets mapped to different physical address spaces in
46 * the kernel.
47 */
48 struct octep_mmio {
49 /* The physical address to which the PCI address space is mapped. */
50 u8 __iomem *hw_addr;
51
52 /* Flag indicating the mapping was successful. */
53 int mapped;
54 };
55
56 struct octep_pci_win_regs {
57 u8 __iomem *pci_win_wr_addr;
58 u8 __iomem *pci_win_rd_addr;
59 u8 __iomem *pci_win_wr_data;
60 u8 __iomem *pci_win_rd_data;
61 };
62
63 struct octep_hw_ops {
64 void (*setup_iq_regs)(struct octep_device *oct, int q);
65 void (*setup_oq_regs)(struct octep_device *oct, int q);
66 void (*setup_mbox_regs)(struct octep_device *oct, int mbox);
67
68 irqreturn_t (*non_ioq_intr_handler)(void *ioq_vector);
69 irqreturn_t (*ioq_intr_handler)(void *ioq_vector);
70 int (*soft_reset)(struct octep_device *oct);
71 void (*reinit_regs)(struct octep_device *oct);
72 u32 (*update_iq_read_idx)(struct octep_iq *iq);
73
74 void (*enable_interrupts)(struct octep_device *oct);
75 void (*disable_interrupts)(struct octep_device *oct);
76 bool (*poll_non_ioq_interrupts)(struct octep_device *oct);
77
78 void (*enable_io_queues)(struct octep_device *oct);
79 void (*disable_io_queues)(struct octep_device *oct);
80 void (*enable_iq)(struct octep_device *oct, int q);
81 void (*disable_iq)(struct octep_device *oct, int q);
82 void (*enable_oq)(struct octep_device *oct, int q);
83 void (*disable_oq)(struct octep_device *oct, int q);
84 void (*reset_io_queues)(struct octep_device *oct);
85 void (*dump_registers)(struct octep_device *oct);
86 };
87
88 /* Octeon mailbox data */
89 struct octep_mbox_data {
90 u32 cmd;
91 u32 total_len;
92 u32 recv_len;
93 u32 rsvd;
94 u64 *data;
95 };
96
97 /* Octeon device mailbox */
98 struct octep_mbox {
99 /* A spinlock to protect access to this q_mbox. */
100 spinlock_t lock;
101
102 u32 q_no;
103 u32 state;
104
105 /* SLI_MAC_PF_MBOX_INT for PF, SLI_PKT_MBOX_INT for VF. */
106 u8 __iomem *mbox_int_reg;
107
108 /* SLI_PKT_PF_VF_MBOX_SIG(0) for PF,
109 * SLI_PKT_PF_VF_MBOX_SIG(1) for VF.
110 */
111 u8 __iomem *mbox_write_reg;
112
113 /* SLI_PKT_PF_VF_MBOX_SIG(1) for PF,
114 * SLI_PKT_PF_VF_MBOX_SIG(0) for VF.
115 */
116 u8 __iomem *mbox_read_reg;
117
118 struct octep_mbox_data mbox_data;
119 };
120
121 /* Tx/Rx queue vector per interrupt. */
122 struct octep_ioq_vector {
123 char name[OCTEP_MSIX_NAME_SIZE];
124 struct napi_struct napi;
125 struct octep_device *octep_dev;
126 struct octep_iq *iq;
127 struct octep_oq *oq;
128 cpumask_t affinity_mask;
129 };
130
131 /* Octeon hardware/firmware offload capability flags. */
132 #define OCTEP_CAP_TX_CHECKSUM BIT(0)
133 #define OCTEP_CAP_RX_CHECKSUM BIT(1)
134 #define OCTEP_CAP_TSO BIT(2)
135
136 /* Link modes */
137 enum octep_link_mode_bit_indices {
138 OCTEP_LINK_MODE_10GBASE_T = 0,
139 OCTEP_LINK_MODE_10GBASE_R,
140 OCTEP_LINK_MODE_10GBASE_CR,
141 OCTEP_LINK_MODE_10GBASE_KR,
142 OCTEP_LINK_MODE_10GBASE_LR,
143 OCTEP_LINK_MODE_10GBASE_SR,
144 OCTEP_LINK_MODE_25GBASE_CR,
145 OCTEP_LINK_MODE_25GBASE_KR,
146 OCTEP_LINK_MODE_25GBASE_SR,
147 OCTEP_LINK_MODE_40GBASE_CR4,
148 OCTEP_LINK_MODE_40GBASE_KR4,
149 OCTEP_LINK_MODE_40GBASE_LR4,
150 OCTEP_LINK_MODE_40GBASE_SR4,
151 OCTEP_LINK_MODE_50GBASE_CR2,
152 OCTEP_LINK_MODE_50GBASE_KR2,
153 OCTEP_LINK_MODE_50GBASE_SR2,
154 OCTEP_LINK_MODE_50GBASE_CR,
155 OCTEP_LINK_MODE_50GBASE_KR,
156 OCTEP_LINK_MODE_50GBASE_LR,
157 OCTEP_LINK_MODE_50GBASE_SR,
158 OCTEP_LINK_MODE_100GBASE_CR4,
159 OCTEP_LINK_MODE_100GBASE_KR4,
160 OCTEP_LINK_MODE_100GBASE_LR4,
161 OCTEP_LINK_MODE_100GBASE_SR4,
162 OCTEP_LINK_MODE_NBITS
163 };
164
165 /* Hardware interface link state information. */
166 struct octep_iface_link_info {
167 /* Bitmap of Supported link speeds/modes. */
168 u64 supported_modes;
169
170 /* Bitmap of Advertised link speeds/modes. */
171 u64 advertised_modes;
172
173 /* Negotiated link speed in Mbps. */
174 u32 speed;
175
176 /* MTU */
177 u16 mtu;
178
179 /* Autonegotation state. */
180 #define OCTEP_LINK_MODE_AUTONEG_SUPPORTED BIT(0)
181 #define OCTEP_LINK_MODE_AUTONEG_ADVERTISED BIT(1)
182 u8 autoneg;
183
184 /* Pause frames setting. */
185 #define OCTEP_LINK_MODE_PAUSE_SUPPORTED BIT(0)
186 #define OCTEP_LINK_MODE_PAUSE_ADVERTISED BIT(1)
187 u8 pause;
188
189 /* Admin state of the link (ifconfig <iface> up/down */
190 u8 admin_up;
191
192 /* Operational state of the link: physical link is up down */
193 u8 oper_up;
194 };
195
196 /* The Octeon device specific private data structure.
197 * Each Octeon device has this structure to represent all its components.
198 */
199 struct octep_device {
200 struct octep_config *conf;
201
202 /* Octeon Chip type. */
203 u16 chip_id;
204 u16 rev_id;
205
206 /* Device capabilities enabled */
207 u64 caps_enabled;
208 /* Device capabilities supported */
209 u64 caps_supported;
210
211 /* Pointer to basic Linux device */
212 struct device *dev;
213 /* Linux PCI device pointer */
214 struct pci_dev *pdev;
215 /* Netdev corresponding to the Octeon device */
216 struct net_device *netdev;
217
218 /* memory mapped io range */
219 struct octep_mmio mmio[OCTEP_MMIO_REGIONS];
220
221 /* MAC address */
222 u8 mac_addr[ETH_ALEN];
223
224 /* Tx queues (IQ: Instruction Queue) */
225 u16 num_iqs;
226 /* pkind value to be used in every Tx hardware descriptor */
227 u8 pkind;
228 /* Pointers to Octeon Tx queues */
229 struct octep_iq *iq[OCTEP_MAX_IQ];
230
231 /* Rx queues (OQ: Output Queue) */
232 u16 num_oqs;
233 /* Pointers to Octeon Rx queues */
234 struct octep_oq *oq[OCTEP_MAX_OQ];
235
236 /* Hardware port number of the PCIe interface */
237 u16 pcie_port;
238
239 /* PCI Window registers to access some hardware CSRs */
240 struct octep_pci_win_regs pci_win_regs;
241 /* Hardware operations */
242 struct octep_hw_ops hw_ops;
243
244 /* IRQ info */
245 u16 num_irqs;
246 u16 num_non_ioq_irqs;
247 char *non_ioq_irq_names;
248 struct msix_entry *msix_entries;
249 /* IOq information of it's corresponding MSI-X interrupt. */
250 struct octep_ioq_vector *ioq_vector[OCTEP_MAX_QUEUES];
251
252 /* Hardware Interface Tx statistics */
253 struct octep_iface_tx_stats iface_tx_stats;
254 /* Hardware Interface Rx statistics */
255 struct octep_iface_rx_stats iface_rx_stats;
256
257 /* Hardware Interface Link info like supported modes, aneg support */
258 struct octep_iface_link_info link_info;
259
260 /* Mailbox to talk to VFs */
261 struct octep_mbox *mbox[OCTEP_MAX_VF];
262
263 /* Work entry to handle Tx timeout */
264 struct work_struct tx_timeout_task;
265
266 /* control mbox over pf */
267 struct octep_ctrl_mbox ctrl_mbox;
268
269 /* offset for iface stats */
270 u32 ctrl_mbox_ifstats_offset;
271
272 /* Work entry to handle ctrl mbox interrupt */
273 struct work_struct ctrl_mbox_task;
274 /* Wait queue for host to firmware requests */
275 wait_queue_head_t ctrl_req_wait_q;
276 /* List of objects waiting for h2f response */
277 struct list_head ctrl_req_wait_list;
278
279 /* Enable non-ioq interrupt polling */
280 bool poll_non_ioq_intr;
281 /* Work entry to poll non-ioq interrupts */
282 struct delayed_work intr_poll_task;
283
284 /* Firmware heartbeat timer */
285 struct timer_list hb_timer;
286 /* Firmware heartbeat miss count tracked by timer */
287 atomic_t hb_miss_cnt;
288 /* Task to reset device on heartbeat miss */
289 struct delayed_work hb_task;
290 };
291
OCTEP_MAJOR_REV(struct octep_device * oct)292 static inline u16 OCTEP_MAJOR_REV(struct octep_device *oct)
293 {
294 u16 rev = (oct->rev_id & 0xC) >> 2;
295
296 return (rev == 0) ? 1 : rev;
297 }
298
OCTEP_MINOR_REV(struct octep_device * oct)299 static inline u16 OCTEP_MINOR_REV(struct octep_device *oct)
300 {
301 return (oct->rev_id & 0x3);
302 }
303
304 /* Octeon CSR read/write access APIs */
305 #define octep_write_csr(octep_dev, reg_off, value) \
306 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off))
307
308 #define octep_write_csr64(octep_dev, reg_off, val64) \
309 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off))
310
311 #define octep_read_csr(octep_dev, reg_off) \
312 readl((octep_dev)->mmio[0].hw_addr + (reg_off))
313
314 #define octep_read_csr64(octep_dev, reg_off) \
315 readq((octep_dev)->mmio[0].hw_addr + (reg_off))
316
317 /* Read windowed register.
318 * @param oct - pointer to the Octeon device.
319 * @param addr - Address of the register to read.
320 *
321 * This routine is called to read from the indirectly accessed
322 * Octeon registers that are visible through a PCI BAR0 mapped window
323 * register.
324 * @return - 64 bit value read from the register.
325 */
326 static inline u64
OCTEP_PCI_WIN_READ(struct octep_device * oct,u64 addr)327 OCTEP_PCI_WIN_READ(struct octep_device *oct, u64 addr)
328 {
329 u64 val64;
330
331 addr |= 1ull << 53; /* read 8 bytes */
332 writeq(addr, oct->pci_win_regs.pci_win_rd_addr);
333 val64 = readq(oct->pci_win_regs.pci_win_rd_data);
334
335 dev_dbg(&oct->pdev->dev,
336 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val64);
337
338 return val64;
339 }
340
341 /* Write windowed register.
342 * @param oct - pointer to the Octeon device.
343 * @param addr - Address of the register to write
344 * @param val - Value to write
345 *
346 * This routine is called to write to the indirectly accessed
347 * Octeon registers that are visible through a PCI BAR0 mapped window
348 * register.
349 * @return Nothing.
350 */
351 static inline void
OCTEP_PCI_WIN_WRITE(struct octep_device * oct,u64 addr,u64 val)352 OCTEP_PCI_WIN_WRITE(struct octep_device *oct, u64 addr, u64 val)
353 {
354 writeq(addr, oct->pci_win_regs.pci_win_wr_addr);
355 writeq(val, oct->pci_win_regs.pci_win_wr_data);
356
357 dev_dbg(&oct->pdev->dev,
358 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val);
359 }
360
361 extern struct workqueue_struct *octep_wq;
362
363 int octep_device_setup(struct octep_device *oct);
364 int octep_setup_iqs(struct octep_device *oct);
365 void octep_free_iqs(struct octep_device *oct);
366 void octep_clean_iqs(struct octep_device *oct);
367 int octep_setup_oqs(struct octep_device *oct);
368 void octep_free_oqs(struct octep_device *oct);
369 void octep_oq_dbell_init(struct octep_device *oct);
370 void octep_device_setup_cn93_pf(struct octep_device *oct);
371 int octep_iq_process_completions(struct octep_iq *iq, u16 budget);
372 int octep_oq_process_rx(struct octep_oq *oq, int budget);
373 void octep_set_ethtool_ops(struct net_device *netdev);
374
375 #endif /* _OCTEP_MAIN_H_ */
376