1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1999 by Ralf Baechle 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 */ 9 #ifndef _ASM_SERIAL_H 10 #define _ASM_SERIAL_H 11 12 #include <linux/config.h> 13 #include <asm/jazz.h> 14 15 /* 16 * This assumes you have a 1.8432 MHz clock for your UART. 17 * 18 * It'd be nice if someone built a serial card with a 24.576 MHz 19 * clock, since the 16550A is capable of handling a top speed of 1.5 20 * megabits/second; but this requires the faster clock. 21 */ 22 #define BASE_BAUD ( 1843200 / 16 ) 23 24 #ifndef CONFIG_OLIVETTI_M700 25 /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know 26 exactly which ones ... XXX */ 27 #define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */ 28 #else 29 /* but the M700 isn't such a strange beast */ 30 #define JAZZ_BASE_BAUD BASE_BAUD 31 #endif 32 33 /* Standard COM flags (except for COM4, because of the 8514 problem) */ 34 #ifdef CONFIG_SERIAL_DETECT_IRQ 35 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) 36 #define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) 37 #else 38 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) 39 #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 40 #endif 41 42 #ifdef CONFIG_SERIAL_MANY_PORTS 43 #define FOURPORT_FLAGS ASYNC_FOURPORT 44 #define ACCENT_FLAGS 0 45 #define BOCA_FLAGS 0 46 #define HUB6_FLAGS 0 47 #define RS_TABLE_SIZE 64 48 #else 49 #define RS_TABLE_SIZE 50 #endif 51 52 /* 53 * The following define the access methods for the HUB6 card. All 54 * access is through two ports for all 24 possible chips. The card is 55 * selected through the high 2 bits, the port on that card with the 56 * "middle" 3 bits, and the register on that port with the bottom 57 * 3 bits. 58 * 59 * While the access port and interrupt is configurable, the default 60 * port locations are 0x302 for the port control register, and 0x303 61 * for the data read/write register. Normally, the interrupt is at irq3 62 * but can be anything from 3 to 7 inclusive. Note that using 3 will 63 * require disabling com2. 64 */ 65 66 #define C_P(card,port) (((card)<<6|(port)<<3) + 1) 67 68 #ifdef CONFIG_MIPS_JAZZ 69 #define _JAZZ_SERIAL_INIT(int, base) \ 70 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \ 71 .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \ 72 .io_type = SERIAL_IO_MEM } 73 #define JAZZ_SERIAL_PORT_DEFNS \ 74 _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \ 75 _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE), 76 #else 77 #define JAZZ_SERIAL_PORT_DEFNS 78 #endif 79 80 #ifdef CONFIG_MIPS_ATLAS 81 #include <asm/mips-boards/atlas.h> 82 #include <asm/mips-boards/atlasint.h> 83 #define ATLAS_SERIAL_PORT_DEFNS \ 84 /* UART CLK PORT IRQ FLAGS */ \ 85 { 0, ATLAS_BASE_BAUD, ATLAS_UART_REGS_BASE, ATLASINT_UART, STD_COM_FLAGS }, /* ttyS0 */ 86 #else 87 #define ATLAS_SERIAL_PORT_DEFNS 88 #endif 89 90 #ifdef CONFIG_MIPS_SEAD 91 #include <asm/mips-boards/sead.h> 92 #include <asm/mips-boards/seadint.h> 93 #define SEAD_SERIAL_PORT_DEFNS \ 94 /* UART CLK PORT IRQ FLAGS */ \ 95 { 0, SEAD_BASE_BAUD, SEAD_UART0_REGS_BASE, SEADINT_UART0, STD_COM_FLAGS }, /* ttyS0 */ 96 #else 97 #define SEAD_SERIAL_PORT_DEFNS 98 #endif 99 100 #ifdef CONFIG_MIPS_COBALT 101 #include <asm/cobalt/cobalt.h> 102 #define COBALT_BASE_BAUD (18432000 / 16) 103 #define COBALT_SERIAL_PORT_DEFNS \ 104 /* UART CLK PORT IRQ FLAGS */ \ 105 { 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS }, /* ttyS0 */ 106 #else 107 #define COBALT_SERIAL_PORT_DEFNS 108 #endif 109 110 /* 111 * Both Galileo boards have the same UART mappings. 112 */ 113 #if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120) 114 #include <asm/gt64120/gt64120.h> 115 #include <asm/galileo-boards/ev96100int.h> 116 #define EV96100_SERIAL_PORT_DEFNS \ 117 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \ 118 .flags = STD_COM_FLAGS, \ 119 .iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \ 120 .io_type = SERIAL_IO_MEM }, \ 121 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \ 122 .flags = STD_COM_FLAGS, \ 123 .iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \ 124 .io_type = SERIAL_IO_MEM }, 125 #else 126 #define EV96100_SERIAL_PORT_DEFNS 127 #endif 128 129 #ifdef CONFIG_MIPS_ITE8172 130 #include <asm/it8172/it8172.h> 131 #include <asm/it8172/it8172_int.h> 132 #include <asm/it8712.h> 133 #define ITE_SERIAL_PORT_DEFNS \ 134 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \ 135 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \ 136 { .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \ 137 .irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .type = 0x3 }, \ 138 /* Smart Card Reader 0 */ \ 139 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \ 140 .irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \ 141 /* Smart Card Reader 1 */ \ 142 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \ 143 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, 144 #else 145 #define ITE_SERIAL_PORT_DEFNS 146 #endif 147 148 #ifdef CONFIG_MIPS_IVR 149 #include <asm/it8172/it8172.h> 150 #include <asm/it8172/it8172_int.h> 151 #define IVR_SERIAL_PORT_DEFNS \ 152 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \ 153 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \ 154 /* Smart Card Reader 1 */ \ 155 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \ 156 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, 157 #else 158 #define IVR_SERIAL_PORT_DEFNS 159 #endif 160 161 #ifdef CONFIG_AU1X00_UART 162 #include <asm/au1000.h> 163 #ifdef CONFIG_SOC_AU1000 164 #define AU1000_SERIAL_PORT_DEFNS \ 165 { .baud_base = 0, .port = UART0_ADDR, .irq = AU1000_UART0_INT, \ 166 .flags = STD_COM_FLAGS, .type = 1 }, \ 167 { .baud_base = 0, .port = UART1_ADDR, .irq = AU1000_UART1_INT, \ 168 .flags = STD_COM_FLAGS, .type = 1 }, \ 169 { .baud_base = 0, .port = UART2_ADDR, .irq = AU1000_UART2_INT, \ 170 .flags = STD_COM_FLAGS, .type = 1 }, \ 171 { .baud_base = 0, .port = UART3_ADDR, .irq = AU1000_UART3_INT, \ 172 .flags = STD_COM_FLAGS, .type = 1 }, 173 #endif 174 175 #ifdef CONFIG_SOC_AU1500 176 #define AU1000_SERIAL_PORT_DEFNS \ 177 { .baud_base = 0, .port = UART0_ADDR, .irq = AU1500_UART0_INT, \ 178 .flags = STD_COM_FLAGS, .type = 1 }, \ 179 { .baud_base = 0, .port = UART3_ADDR, .irq = AU1500_UART3_INT, \ 180 .flags = STD_COM_FLAGS, .type = 1 }, 181 #endif 182 183 #ifdef CONFIG_SOC_AU1100 184 #define AU1000_SERIAL_PORT_DEFNS \ 185 { .baud_base = 0, .port = UART0_ADDR, .irq = AU1100_UART0_INT, \ 186 .flags = STD_COM_FLAGS, .type = 1 }, \ 187 { .baud_base = 0, .port = UART1_ADDR, .irq = AU1100_UART1_INT, \ 188 .flags = STD_COM_FLAGS, .type = 1 }, \ 189 { .baud_base = 0, .port = UART3_ADDR, .irq = AU1100_UART3_INT, \ 190 .flags = STD_COM_FLAGS, .type = 1 }, 191 #endif 192 193 #ifdef CONFIG_SOC_AU1550 194 #define AU1000_SERIAL_PORT_DEFNS \ 195 { .baud_base = 0, .port = UART0_ADDR, .irq = AU1550_UART0_INT, \ 196 .flags = STD_COM_FLAGS, .type = 1 }, \ 197 { .baud_base = 0, .port = UART1_ADDR, .irq = AU1550_UART1_INT, \ 198 .flags = STD_COM_FLAGS, .type = 1 }, \ 199 { .baud_base = 0, .port = UART3_ADDR, .irq = AU1550_UART3_INT, \ 200 .flags = STD_COM_FLAGS, .type = 1 }, 201 #endif 202 203 #ifdef CONFIG_SOC_AU1200 204 #define AU1000_SERIAL_PORT_DEFNS \ 205 { .baud_base = 0, .port = UART0_ADDR, .irq = AU1200_UART0_INT, \ 206 .flags = STD_COM_FLAGS, .type = 1 }, \ 207 { .baud_base = 0, .port = UART1_ADDR, .irq = AU1200_UART1_INT, \ 208 .flags = STD_COM_FLAGS, .type = 1 }, 209 #endif 210 211 #else 212 #define AU1000_SERIAL_PORT_DEFNS 213 #endif 214 215 #ifdef CONFIG_TOSHIBA_JMR3927 216 #include <asm/jmr3927/jmr3927.h> 217 #define TXX927_SERIAL_PORT_DEFNS \ 218 { .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT, \ 219 .flags = UART0_FLAGS, .type = 1 }, \ 220 { .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT, \ 221 .flags = UART1_FLAGS, .type = 1 }, 222 #else 223 #define TXX927_SERIAL_PORT_DEFNS 224 #endif 225 226 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT 227 #define STD_SERIAL_PORT_DEFNS \ 228 /* UART CLK PORT IRQ FLAGS */ \ 229 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 230 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 231 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 232 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 233 234 #ifdef CONFIG_SERIAL_MANY_PORTS 235 #define EXTRA_SERIAL_PORT_DEFNS \ 236 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \ 237 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \ 238 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \ 239 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \ 240 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \ 241 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \ 242 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \ 243 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \ 244 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \ 245 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \ 246 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \ 247 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \ 248 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \ 249 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \ 250 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \ 251 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \ 252 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \ 253 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \ 254 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \ 255 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \ 256 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \ 257 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \ 258 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \ 259 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \ 260 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \ 261 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \ 262 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \ 263 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */ 264 #else /* CONFIG_SERIAL_MANY_PORTS */ 265 #define EXTRA_SERIAL_PORT_DEFNS 266 #endif /* CONFIG_SERIAL_MANY_PORTS */ 267 268 #else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ 269 #define STD_SERIAL_PORT_DEFNS 270 #define EXTRA_SERIAL_PORT_DEFNS 271 #endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ 272 273 /* You can have up to four HUB6's in the system, but I've only 274 * included two cards here for a total of twelve ports. 275 */ 276 #if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS)) 277 #define HUB6_SERIAL_PORT_DFNS \ 278 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \ 279 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \ 280 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \ 281 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \ 282 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \ 283 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \ 284 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \ 285 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \ 286 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \ 287 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \ 288 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \ 289 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */ 290 #else 291 #define HUB6_SERIAL_PORT_DFNS 292 #endif 293 294 #ifdef CONFIG_MCA 295 #define MCA_SERIAL_PORT_DFNS \ 296 { 0, BASE_BAUD, 0x3220, 3, STD_COM_FLAGS }, \ 297 { 0, BASE_BAUD, 0x3228, 3, STD_COM_FLAGS }, \ 298 { 0, BASE_BAUD, 0x4220, 3, STD_COM_FLAGS }, \ 299 { 0, BASE_BAUD, 0x4228, 3, STD_COM_FLAGS }, \ 300 { 0, BASE_BAUD, 0x5220, 3, STD_COM_FLAGS }, \ 301 { 0, BASE_BAUD, 0x5228, 3, STD_COM_FLAGS }, 302 #else 303 #define MCA_SERIAL_PORT_DFNS 304 #endif 305 306 #ifdef CONFIG_MOMENCO_OCELOT 307 /* Ordinary NS16552 duart with a 20MHz crystal. */ 308 #define OCELOT_BASE_BAUD ( 20000000 / 16 ) 309 310 #define OCELOT_SERIAL1_IRQ 4 311 #define OCELOT_SERIAL1_BASE 0xe0001020 312 313 #define _OCELOT_SERIAL_INIT(int, base) \ 314 { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \ 315 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \ 316 .io_type = SERIAL_IO_MEM } 317 #define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ 318 _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE) 319 #else 320 #define MOMENCO_OCELOT_SERIAL_PORT_DEFNS 321 #endif 322 323 #ifdef CONFIG_MOMENCO_OCELOT_G 324 /* Ordinary NS16552 duart with a 20MHz crystal. */ 325 #define OCELOT_G_BASE_BAUD ( 20000000 / 16 ) 326 327 #define OCELOT_G_SERIAL1_IRQ 4 328 #if 0 329 #define OCELOT_G_SERIAL1_BASE 0xe0001020 330 #else 331 #define OCELOT_G_SERIAL1_BASE 0xfd000020 332 #endif 333 334 #define _OCELOT_G_SERIAL_INIT(int, base) \ 335 { .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\ 336 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \ 337 .io_type = SERIAL_IO_MEM } 338 #define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ 339 _OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE) 340 #else 341 #define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS 342 #endif 343 344 #ifdef CONFIG_MOMENCO_OCELOT_C 345 /* Ordinary NS16552 duart with a 20MHz crystal. */ 346 #define OCELOT_C_BASE_BAUD ( 20000000 / 16 ) 347 348 #define OCELOT_C_SERIAL1_IRQ 80 349 #define OCELOT_C_SERIAL1_BASE 0xfd000020 350 351 #define OCELOT_C_SERIAL2_IRQ 81 352 #define OCELOT_C_SERIAL2_BASE 0xfd000000 353 354 #define _OCELOT_C_SERIAL_INIT(int, base) \ 355 { baud_base: OCELOT_C_BASE_BAUD, irq: int, flags: STD_COM_FLAGS,\ 356 iomem_base: (u8 *) base, iomem_reg_shift: 2, \ 357 io_type: SERIAL_IO_MEM } 358 #define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ 359 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \ 360 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE) 361 #else 362 #define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS 363 #endif 364 365 #ifdef CONFIG_PMC_STRETCH 366 /* 16550 Compatible. FIXME: Need to get the defines below */ 367 368 #define PMC_STRETCH_BASE_BAUD ( 1843200 / 16 ) 369 #define PMC_STRETCH_IRQ 0 370 #define PMC_STRETCH_BASE_ADDRESS 0xbd110000 371 372 #define _PMC_STRETCH_SERIAL_INIT(int, base) \ 373 { baud_base: PMC_STRETCH_BASE_BAUD, irq: int, \ 374 flags: STD_COM_FLAGS, iomem_base: (u8 *) base, \ 375 iomem_reg_shift: 2, io_type: SERIAL_IO_MEM } 376 377 #define PMC_STRETCH_SERIAL_PORT_DEFNS \ 378 _PMC_STRETCH_SERIAL_INIT(PMC_STRETCH_IRQ, PMC_STRETCH_BASE_ADDRESS) 379 #else 380 #define PMC_STRETCH_SERIAL_PORT_DEFNS 381 #endif 382 383 #ifdef CONFIG_MOMENCO_JAGUAR_ATX 384 /* Ordinary NS16552 duart with a 20MHz crystal. */ 385 #define JAGUAR_ATX_BASE_BAUD ( 20000000 / 16 ) 386 387 #define JAGUAR_ATX_SERIAL1_IRQ 7 388 #define JAGUAR_ATX_SERIAL1_BASE 0xfffffffffd000020 389 390 #define _JAGUAR_ATX_SERIAL_INIT(int, base) \ 391 { baud_base: JAGUAR_ATX_BASE_BAUD, irq: int, \ 392 flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 393 iomem_base: (u8 *) base, iomem_reg_shift: 2, \ 394 io_type: SERIAL_IO_MEM } 395 #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \ 396 _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE) 397 #else 398 #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS 399 #endif 400 401 #ifdef CONFIG_TITAN_SERIAL 402 /* 16552 20 MHz crystal */ 403 #define TITAN_SERIAL_BASE_BAUD ( 20000000 / 16 ) 404 #define TITAN_SERIAL_IRQ XXX 405 #define TITAN_SERIAL_BASE 0xffffffff 406 407 #define _TITAN_SERIAL_INIT(int, base) \ 408 { baud_base: TITAN_SERIAL_BASE_BAUD, irq: int, \ 409 flags: STD_COM_FLAGS, iomem_base: (u8 *) base, \ 410 iomem_reg_shift: 2, io_type: SERIAL_IO_MEM \ 411 } 412 413 #define TITAN_SERIAL_PORT_DEFNS \ 414 _TITAN_SERIAL_INIT(TITAN_SERIAL_IRQ, TITAN_SERIAL_BASE) 415 #else 416 #define TITAN_SERIAL_PORT_DEFNS 417 #endif 418 419 #ifdef CONFIG_SGI_IP27 420 421 /* 422 * Note about serial ports and consoles: 423 * For console output, everyone uses the IOC3 UARTA (offset 0x178) 424 * connected to the master node (look in ip27_setup_console() and 425 * ip27prom_console_write()). 426 * 427 * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port 428 * addresses on a partitioned machine. Since we currently use the ioc3 429 * serial ports, we use dynamic serial port discovery that the serial.c 430 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3 431 * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater 432 * than UARTB's, although UARTA on o200s has traditionally been known as 433 * port 0. So, we just use one serial port from each ioc3 (since the 434 * serial driver adds addresses to get to higher ports). 435 * 436 * The first one to do a register_console becomes the preferred console 437 * (if there is no kernel command line console= directive). /dev/console 438 * (ie 5, 1) is then "aliased" into the device number returned by the 439 * "device" routine referred to in this console structure 440 * (ip27prom_console_dev). 441 * 442 * Also look in ip27-pci.c:pci_fixuop_ioc3() for some comments on working 443 * around ioc3 oddities in this respect. 444 * 445 * The IOC3 serials use a 22MHz clock rate with an additional divider by 3. 446 * (IOC3_BAUD = (22000000 / (3*16))) 447 * 448 * At the moment this is only a skeleton definition as we register all serials 449 * at runtime. 450 */ 451 452 #define IP27_SERIAL_PORT_DEFNS 453 #else 454 #define IP27_SERIAL_PORT_DEFNS 455 #endif /* CONFIG_SGI_IP27 */ 456 457 #ifdef CONFIG_DDB5477 458 #include <asm/ddb5xxx/ddb5477.h> 459 #define DDB5477_SERIAL_PORT_DEFNS \ 460 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \ 461 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \ 462 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \ 463 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \ 464 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \ 465 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, 466 #else 467 #define DDB5477_SERIAL_PORT_DEFNS 468 #endif 469 470 #define SERIAL_PORT_DFNS \ 471 ATLAS_SERIAL_PORT_DEFNS \ 472 AU1000_SERIAL_PORT_DEFNS \ 473 COBALT_SERIAL_PORT_DEFNS \ 474 DDB5477_SERIAL_PORT_DEFNS \ 475 EV96100_SERIAL_PORT_DEFNS \ 476 EXTRA_SERIAL_PORT_DEFNS \ 477 HUB6_SERIAL_PORT_DFNS \ 478 ITE_SERIAL_PORT_DEFNS \ 479 IVR_SERIAL_PORT_DEFNS \ 480 JAZZ_SERIAL_PORT_DEFNS \ 481 MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ 482 MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ 483 MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ 484 MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \ 485 PMC_STRETCH_SERIAL_PORT_DEFNS \ 486 SEAD_SERIAL_PORT_DEFNS \ 487 STD_SERIAL_PORT_DEFNS \ 488 TITAN_SERIAL_PORT_DEFNS \ 489 TXX927_SERIAL_PORT_DEFNS 490 491 #endif /* _ASM_SERIAL_H */ 492